On 24/12/22 16:18, Richard Henderson wrote:
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 39 ---
1 file changed, 32 insertions(+), 7 deletions(-)
On 24/12/22 16:18, Richard Henderson wrote:
Because we allow lockless lookups, we have to be careful
when it is freed. Use rcu to delay the free until safe.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
On Sat, Dec 24, 2022 at 7:49 PM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> We should stop if the GET_IOVA_RANGE ioctl failed.
Acked-by: Jason Wang
Thanks
>
> Signed-off-by: Longpeng
> ---
> net/vhost-vdpa.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/ne
On Sat, Dec 24, 2022 at 7:49 PM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> In commit a585fad26b ("vdpa: request iova_range only once") we remove
> GET_IOVA_RANGE form vhost_vdpa_init, the generic vdpa device will start
> without iova_range populated, so the device won't work. Let's call
> GET_I
sorry for that, i will try again with git.sr.th.
-- 原始邮件 --
发件人: "Alistair Francis";
发件时间: 2022-12-28 13:46
收件人: "Elta"<503386...@qq.com>;
收件人:
"qemu-devel";"palmer";"alistair.francis";"bin.meng";"qemu-riscv";
主题: Re: [PATCH] target/riscv/cpu.c: Fix elen check
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode| 18 +++
target/riscv/insn_trans/trans_rvzce.c.inc | 189 +-
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 4 ++
target/riscv/cpu_bit
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4f421130aa..bc954d9b85 100644
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode | 8
target/riscv/insn_trans/trans_rvf.c.inc | 18 +
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9
To test Zc* implementation, spe
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
disas/riscv.c | 228 +-
1 file changed, 227 insertions(+), 1 deletion(-)
di
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Wilfred Mallawa
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c
Add encode and trans* functions support for Zcb instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode| 24 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 100 +
On Fri, Dec 16, 2022 at 1:10 AM Elta <503386...@qq.com> wrote:
>
> Should be cpu->cfg.elen in range [8, 64].
>
> Signed-off-by: Dongxue Zhang
Thanks for the patch!
I'm seeing weird formatting issues though, it looks like the encoding
is incorrect.
Did you use `git send-email` to send the patch?
On Wed, Nov 30, 2022 at 5:53 PM Weiwei Li wrote:
>
> This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version
> instructions.
>
> Specification:
> https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
>
> The port is available here:
> https://github.com/plctlab/p
On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote:
>
> On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote:
> >
> > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote:
> > >
> > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis
> > > wrote:
> > > >
> > > > On Thu, Dec 8, 2022 at 6:41 PM Anu
On Tue, Dec 27, 2022 at 4:55 PM Bin Meng wrote:
>
> Rename previous riscv_find_firmware() to riscv_find_bios(), and
> introduce a new riscv_find_firmware() to implement the first half
> part of the work done in riscv_find_and_load_firmware().
>
> This new API is helpful for machine that wants to k
On Tue, Dec 27, 2022 at 4:54 PM Bin Meng wrote:
>
> Spike machine now supports OpenSBI plain binary bios image, so the
> comments are no longer valid.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/spike.c | 5 -
> 1 file changed, 5 deletions(-)
>
>
On Tue, Dec 27, 2022 at 4:49 PM Bin Meng wrote:
>
> At present the HTIF proxy syscall is unsupported. On RV32, only
> device 0 is supported so there is no console device for RV32.
> The only way to implement console funtionality on RV32 is to
> support the SYS_WRITE syscall.
>
> With this commit,
On Tue, Dec 27, 2022 at 4:56 PM Bin Meng wrote:
>
> There are forward declarations for 'vmstate_htif' and 'htif_io_ops'
> in riscv_htif.h however there are no definitions in the C codes.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> include/hw/char/riscv_htif.h
On Wed, Dec 28, 2022 at 1:59 PM Bin Meng wrote:
>
> Hi Daniel,
>
> On Wed, Dec 28, 2022 at 1:52 AM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 12/27/22 03:48, Bin Meng wrote:
> > > At present the 32-bit OpenSBI generic firmware image does not boot on
> > > Spike, only 64-bit image can. Th
On Tue, Dec 27, 2022 at 4:55 PM Bin Meng wrote:
>
> At present for some unknown reason the HTIF registers (fromhost &
> tohost) are defined in the RISC-V CPUArchState. It should really
> be put in the HTIFState struct as it is only meaningful to HTIF.
>
> Signed-off-by: Bin Meng
Reviewed-by: Ali
Hi Daniel,
On Wed, Dec 28, 2022 at 1:52 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 12/27/22 03:48, Bin Meng wrote:
> > At present the 32-bit OpenSBI generic firmware image does not boot on
> > Spike, only 64-bit image can. This is due to the HTIF emulation does
> > not implement the proxy sysca
On Tue, Dec 27, 2022 at 4:52 PM Bin Meng wrote:
>
> QEMU source codes tend to use 's' to represent the hardware state.
> Let's use it for HTIFState.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/char/riscv_htif.c | 64 ++--
On Tue, Dec 27, 2022 at 4:50 PM Bin Meng wrote:
>
> struct HTIFState has 3 members for address space and memory region,
> and are initialized during htif_mm_init(). But they are actually
> useless. Drop them.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> includ
On Tue, Dec 27, 2022 at 4:50 PM Bin Meng wrote:
>
> The Spike HTIF is poorly documented. The only relevant info we can
> get from the internet is from Andrew Waterman at [1].
>
> Add a comment block before htif_handle_tohost_write() to explain
> the tohost register format, and use meaningful macro
On Tue, Dec 27, 2022 at 4:56 PM Bin Meng wrote:
>
> These are not used anywhere. Drop them.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> include/hw/char/riscv_htif.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/include/hw/char/riscv_htif.h b/inclu
Hi, Paolo,
Sorry for mistaken expression.
Without this patch, HAXM v7.8.0 will break support for QEMU and the HAXM
versions older than 7.8.0 still can support QEMU with this patch. It will work
on any version besides HAXM v7.8.0.
Best Regards,
Wenchao
From: Wang, Wenchao
Sent: Wednesday, Dec
In theory gsi base can start from 0 on loongarch virt machine,
however gsi base is hard-coded in linux kernel loongarch system,
else system fails to boot.
This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE,
keeps value unchanged. GSI base is common concept in acpi spec
and easy to unde
On Tue, Dec 27, 2022 at 02:36:54PM +0100, Jason A. Donenfeld wrote:
> On Mon, Dec 26, 2022 at 05:57:30PM +0100, Jason A. Donenfeld wrote:
> > On Mon, Dec 26, 2022 at 03:43:04PM +0100, Jason A. Donenfeld wrote:
> > > On Mon, Dec 26, 2022 at 03:24:07PM +0100, Jason A. Donenfeld wrote:
> > > > Hi,
> >
Hi, Paolo,
Thanks for your reply.
The reason why the variable xcr0 must be added to the header file of QEMU is
because HAXM needs QEMU to allocate memory from user space and pass it to the
kernel. This patch is only used to expand the buffer size of the structure, and
HAXM will use and maintai
在 2022/12/25 上午1:24, Richard Henderson 写道:
On 12/24/22 00:15, Song Gao wrote:
+union fpr_t {
+ uint64_t d;
+ vec_t vec;
+};
+
struct LoongArchTLB {
uint64_t tlb_misc;
/* Fields corresponding to CSR_TLBELO0/1 */
@@ -251,7 +267,7 @@ typedef struct CPUArchState {
uint64_
在 2022/12/24 下午11:39, Richard Henderson 写道:
On 12/24/22 00:15, Song Gao wrote:
Hi, Merry Christmas!
This series adds LoongArch LSX instructions, Since the LoongArch
Vol2 is not open, So we use 'RFC' title.
That is unfortunate, as it makes reviewing this difficult.
Is there a timeline for th
Hi Daniel,
On 12/21/22 15:22, Daniel Henrique Barboza wrote:
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_B
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/idef-parser/README.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/idef-parser/README.rst
b/target/hexagon/idef-parser/README.rst
index 65e6bf4ee5..ff6d14150a 100644
--- a/target/hexagon/idef-
Bin,
On 12/26/22 10:56, Bin Meng wrote:
On Sat, Dec 24, 2022 at 11:52 AM Bin Meng wrote:
Hi,
On Fri, Dec 23, 2022 at 2:25 PM Bin Meng wrote:
Hi Anup,
On Fri, Dec 23, 2022 at 12:56 AM Anup Patel wrote:
On Thu, Dec 22, 2022 at 6:27 PM Bin Meng wrote:
On Thu, Dec 22, 2022 at 6:47 PM Danie
On Tue, Dec 27, 2022 at 05:51:47PM +0100, Philippe Mathieu-Daudé wrote:
> On 27/12/22 08:20, Longpeng(Mike) wrote:
> > From: Longpeng
> >
> > This allows the vhost-vdpa device to batch the setup of all its MRs of
> > host notifiers.
> >
> > This significantly reduces the device starting time, e.
On Tue, Dec 27, 2022 at 05:43:57PM +0100, Philippe Mathieu-Daudé wrote:
> On 27/12/22 08:20, Longpeng(Mike) wrote:
> > From: Longpeng
> >
> > This allows the vhost device to batch the setup of all its host notifiers.
> > This significantly reduces the device starting time, e.g. the time spend
> >
On 12/27/22 03:48, Bin Meng wrote:
At present the 32-bit OpenSBI generic firmware image does not boot on
Spike, only 64-bit image can. This is due to the HTIF emulation does
not implement the proxy syscall interface which is required for the
32-bit HTIF console output.
An OpenSBI bug fix [1]
On 12/27/22 03:48, Bin Meng wrote:
Rename previous riscv_find_firmware() to riscv_find_bios(), and
introduce a new riscv_find_firmware() to implement the first half
part of the work done in riscv_find_and_load_firmware().
This new API is helpful for machine that wants to know the final
chosen
On 12/27/22 03:48, Bin Meng wrote:
Spike machine now supports OpenSBI plain binary bios image, so the
comments are no longer valid.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/spike.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/riscv/spik
On 12/27/22 03:48, Bin Meng wrote:
At present the HTIF proxy syscall is unsupported. On RV32, only
device 0 is supported so there is no console device for RV32.
The only way to implement console funtionality on RV32 is to
support the SYS_WRITE syscall.
With this commit, the Spike machine is a
On 12/27/22 03:48, Bin Meng wrote:
There are forward declarations for 'vmstate_htif' and 'htif_io_ops'
in riscv_htif.h however there are no definitions in the C codes.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Barboza
include/hw/char/riscv_htif.h | 3 ---
1 file chang
On 12/27/22 03:48, Bin Meng wrote:
At present for some unknown reason the HTIF registers (fromhost &
tohost) are defined in the RISC-V CPUArchState. It should really
be put in the HTIFState struct as it is only meaningful to HTIF.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Ba
On 12/27/22 03:48, Bin Meng wrote:
QEMU source codes tend to use 's' to represent the hardware state.
Let's use it for HTIFState.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Barboza
hw/char/riscv_htif.c | 64 ++--
1 file changed,
On 12/27/22 03:48, Bin Meng wrote:
struct HTIFState has 3 members for address space and memory region,
and are initialized during htif_mm_init(). But they are actually
useless. Drop them.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Barboza
include/hw/char/riscv_htif.h |
On 12/27/22 03:48, Bin Meng wrote:
These are not used anywhere. Drop them.
Signed-off-by: Bin Meng
---
Reviewed-by: Daniel Henrique Barboza
include/hw/char/riscv_htif.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
i
On 12/27/22 03:48, Bin Meng wrote:
The Spike HTIF is poorly documented. The only relevant info we can
get from the internet is from Andrew Waterman at [1].
Add a comment block before htif_handle_tohost_write() to explain
the tohost register format, and use meaningful macros intead of
s/intea
Richard Henderson writes:
> From: Ilya Leoshkevich
>
> Add a test that locklessly changes and exercises page protection bits
> from various threads. This helps catch race conditions in the VMA
> handling.
>
> Signed-off-by: Ilya Leoshkevich
> Message-Id: <20221223120252.513319-1-...@linux.ibm
On 27/12/22 08:20, Longpeng(Mike) wrote:
From: Longpeng
This allows the vhost-vdpa device to batch the setup of all its MRs of
host notifiers.
This significantly reduces the device starting time, e.g. the time spend
on setup the host notifier MRs reduce from 423ms to 32ms for a VM with
64 vCPU
On 27/12/22 08:20, Longpeng(Mike) wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host notifiers.
This significantly reduces the device starting time, e.g. the time spend
on enabling notifiers reduce from 376ms to 9.1ms for a VM with 64 vCPUs
and 3 vhost-vDPA ge
While mouse is grabbed, window title contains a hint for the user what
keyboard keys to press to release the mouse. Make that hint text a bit
more user friendly for a Mac user:
- Replace "Ctrl" and "Alt" by appropriate symbols for those keyboard
keys typically displayed for them on a Mac (enco
This patch fixes the issue originally reported in
this thread:
https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html
The root cause of the issue is a bug in the hexagon specific
logic for saving & restoring context during signal delivery.
The CPU state has two different representati
The patch renames the identifier of the 32bit register
HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED.
This change is to intended to provide some warning that
HEX_REG_P3_0 is an aliased register which has multiple
representations in CPU state and therefore might require
special handling in some contexts. Th
This patchset is to fix the issue discovered in this thread
when hexagon toolchain was upgraded to a newer version.
https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html
Investigation revealed that the bug was not in the
toolchain as suspected in the above thread, but in the
hexagon
Il lun 28 nov 2022, 09:12 Wang, Wenchao ha scritto:
> Hi, Philippe,
>
> It is just the full patch. Currently, the implementation of HAXM is
> simple, we did not synchronize the vCPU register for xcr0 from QEMU. HAXM
> will handle the xcr0 state within the kernel space, including
> initialization,
Hi Bin,
On 12/27/22 03:48, Bin Meng wrote:
At present create_fdt() calls htif_uses_elf_symbols() to determine
whether to insert a property for the HTIF. This unfortunately
creates a hidden dependency to riscv_load_{firmware,kernel} that
create_fdt() must be called after the ELF {firmware,kernel
On 25.12.2022 14:18, Ben Dooks wrote:
On Wed, Dec 21, 2022 at 06:36:02PM +0100, Cédric Le Goater wrote:
On 12/21/22 13:22, Guenter Roeck wrote:
Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
xxd -p /sys/bus/spi/devices/spi0.0/
On Mon, Dec 26, 2022 at 05:57:30PM +0100, Jason A. Donenfeld wrote:
> On Mon, Dec 26, 2022 at 03:43:04PM +0100, Jason A. Donenfeld wrote:
> > On Mon, Dec 26, 2022 at 03:24:07PM +0100, Jason A. Donenfeld wrote:
> > > Hi,
> > >
> > > I'm currently stumped at the moment, so adding linux-mm@ and x86@.
Hi, Philippe,
As nobody made any comment on this change, could you help to merge the patch
with a generic target cleanup series? The patch has been attached below. Thanks
in advance.
Best Regards,
Wenchao
-
From b1789f2523d06798b8883664bfa9a9df797bfccf Mon Sep
As I found it introduced from commit: 7d37d351dffee60fc7048bbfd8573421f15eb724
From the code you look at, g_free should belongs to the lable config_assign_error. this code patch has been revert, latest code lable is 'assign_error' and we tested, it's also happend in 6.2.0. but in 7.1.0 or 7.2.
proxy->vector_irqfd did not free when kvm_virtio_pci_vector_use or
msix_set_vector_notifiers failed in virtio_pci_set_guest_notifiers.
Fixes: 7d37d351
Signed-off-by: Lei Xiang
Tested-by: Zeng Chi
Suggested-by: Xie Ming
---
hw/virtio/virtio-pci.c | 2 ++
1 file changed, 2 insertions(+)
diff -
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