On 10.10.2022 18:32, Peter Maydell wrote:
On Mon, 10 Oct 2022 at 16:21, Jason A. Donenfeld wrote:
On Mon, Oct 10, 2022 at 11:54:50AM +0100, Peter Maydell wrote:
The error is essentially the record-and-replay subsystem saying "the
replay just asked for a random number at point when the recordi
On Mon, Oct 3, 2022 at 2:16 PM Jim Shu wrote:
>
> The maximum priority level is hard-coded when writing to interrupt
> priority register. However, when writing to priority threshold register,
> the maximum priority level is from num_priorities Property which is
> configured by platform.
>
> Also c
David Hildenbrand writes:
> Let's make it easier to pin threads created via a ThreadContext to
> all CPUs currently belonging to a given set of NUMA nodes -- which is the
> common case.
>
> "node-affinity" is simply a shortcut for setting "cpu-affinity" manually
> to the list of CPUs belonging to
David Hildenbrand writes:
> Setting the CPU affinity of QEMU threads is a bit problematic, because
> QEMU doesn't always have permissions to set the CPU affinity itself,
> for example, with seccomp after initialized by QEMU:
> -sandbox enable=on,resourcecontrol=deny
>
> General information ab
On Mon, Oct 3, 2022 at 5:07 PM Clément Chigot wrote:
>
> On Mon, Oct 3, 2022 at 6:14 AM Jim Shu wrote:
> >
> > PLIC spec [1] requires interrupt source priority registers are WARL
> > field and the number of supported priority is power-of-2 to simplify SW
> > discovery.
> >
> > Existing QEMU RISC-
Gentle ping.
It's a patch for fix and spec alignment of PLIC.
On Mon, Oct 3, 2022 at 12:14 PM Jim Shu wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
> * f
On Mon, Oct 10, 2022 at 6:53 PM Miguel Luis wrote:
>
> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
> specification adding the field "Hypervisor Vendor Identity" that was missing.
>
> This field's description states the following: "64-bit identifier of
> hypervisor
>
On Wed, Oct 5, 2022 at 1:11 AM Richard Henderson
wrote:
>
> Now that we have collected all of the page data into
> CPUTLBEntryFull, provide an interface to record that
> all in one go, instead of using 4 arguments. This interface
> allows CPUTLBEntryFull to be extended without having to
> change
Remove the unused extioi system memory region and we only
support the extioi iocsr memory region now.
Signed-off-by: Xiaojuan Yang
---
hw/intc/loongarch_extioi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index a703dd30de..44fbe9
When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the index of 's->coreisr' is
current cpu number. Using MemTxAttrs' requester_type and id
to get the cpu index.
Based-on: <20220927141504.3886314-1-alex.ben...@linaro.org>
Signed-off-by: Xiaojuan Yang
---
h
This series add memmap table and fix extioi, ipi device
emulation for LoongArch virt machine.
The 'Fix LoongArch extioi function' patch based on:
20220927141504.3886314-1-alex.ben...@linaro.org
Changes for v5:
These changes are following Philippe Mathieu-Daude's advice.
1. Add trace_bad_read/writ
We had only been reporting the stage2 page size. This causes
problems if stage1 is using a larger page size (16k, 2M, etc),
but stage2 is using a smaller page size, because cputlb does
not set large_page_{addr,mask} properly.
Fix by using the max of the two page sizes.
Reported-by: Marc Zyngier
Both GP and DBM are in the upper attribute block.
Extend the computation of attrs to include them,
then simplify the setting of guarded.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/tar
Perform the atomic update for hardware management of the access flag.
Signed-off-by: Richard Henderson
---
v4: Raise permission fault if pte read-only and atomic update reqd.
Split out dirty bit portion.
Prepare for a single update for AF + DB.
---
docs/system/arm/emulation.rst | 1 +
Leave the upper and lower attributes in the place they originate
from in the descriptor. Shifting them around is confusing, since
one cannot read the bit numbers out of the manual. Also, new
attributes have been added which would alter the shifts.
Reviewed-by: Peter Maydell
Signed-off-by: Richa
Always overriding fi->type was incorrect, as we would not properly
propagate the fault type from S1_ptw_translate, or arm_ldq_ptw.
Simplify things by providing a new label for a translation fault.
For other faults, store into fi directly.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderso
Perform the atomic update for hardware management of the dirty bit.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 2 +-
target/arm/ptw.c | 20
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fe1369fe
The unconditional loop was used both to iterate over levels
and to control parsing of attributes. Use an explicit goto
in both cases.
While this appears less clean for iterating over levels, we
will need to jump back into the middle of this loop for
atomic updates, which is even uglier.
Reviewed
This fault type is to be used with FEAT_HAFDBS when
the guest enables hw updates, but places the tables
in memory where atomic updates are unsupported.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 4
1 file changed, 4 insertions(+)
diff --git a/
Separate S1 translation from the actual lookup.
Will enable lpae hardware updates.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/arm/ptw.c b/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 ++
target/arm/helper.c| 8 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c3c3920ded..76ec7ee8cc 100644
--- a/target/arm/i
The return type of the functions is already bool, but in a few
instances we used an integer type with the return statement.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 191 +--
1 file changed, 100 insertions(+), 91 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8f41d285b7..dd6556560a 100644
--- a/target/arm/ptw.c
Before using softmmu page tables for the ptw, plumb down
a debug parameter so that we can query page table entries
from gdbstub without modifying cpu state.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v4: Add debug to S1Translate, and plumb the S1Translate structure down
So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and
arm_ldq_ptw. Use probe_access_full to find the host address,
and if so use a host load. If the probe fails, we've got our
fault info already. On the off chance that page tables are not
in RAM, continue to use the address_space_ld* fu
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performing it only once.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 53 +
Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8fa0088d98..c58788ac69 100644
--- a/t
We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
Flush the tlb when invalidating stage 1+2 translations. Re-use
alle1_tlbmask() for other instances of EL1&0 + Stage2.
Signed-off-by: Richard Henderson
---
v4: Implement the IPAS2 and RIPAS2 tlb flushing insns;
Reuse alle1_tlb
The MMFR1 field may indicate support for hardware update of
access flag alone, or access flag and dirty bit.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
Consolidate most of the inputs and outputs of S1_ptw_translate
into a single structure. Plumb this through arm_ld*_ptw from
the controlling get_phys_addr_* routine.
Signed-off-by: Richard Henderson
---
v4: Replaces a different S1TranslateResult patch, and plumbs the
structure further out in
Compare only the VMID field when considering whether we need to flush.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 18c51bb777..c672903f43 100644
--- a/target/arm/h
Not yet used, but add mmu indexes for 1-1 mapping
to physical addresses.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 7 ++-
target/arm/ptw.c | 19 +--
3 files changed, 24 insertions(+), 4 del
The CPUTLBEntryFull structure now stores the original pte attributes, as
well as the physical address. Therefore, we no longer need a separate
bit in MemTxAttrs, nor do we need to walk the tree of memory regions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
Copy attrs and shareability, into the TLB. This will eventually
be used by S1_ptw_translate to report stage1 translation failures,
and by do_ats_write to fill in PAR_EL1.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 12
target/arm/tlb_h
Changes for v4:
* Rebase on today's target-arm.next pull, including 21 patches.
* Split AF and DB enablement into two patches.
* Perform only one atomic update per PTE.
* Raise Permission fault if atomic update reqd to read-only PTE.
* More use of S1Translate struct, which is perhaps now
Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
In is_guarded_page, use probe_access_full instead of just guessing
that the tlb entry is still present. Also handles the FIXME about
executing from device memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tar
在 2022/10/10 23:34, Peter Maydell 写道:
+int get_risuop(struct reginfo *ri)
+{
+/* Return the risuop we have been asked to do
+ * (or -1 if this was a SIGILL for a non-risuop insn)
+ */
+uint32_t insn = ri->faulting_insn;
+uint32_t op = insn & 0xf;
+uint32_t key = insn & ~0
On 2022/5/31 1:07, Avihai Horon wrote:
> If vfio_migration_set_state() fails to set the device in the requested
> state it tries to put it in a recover state. If setting the device in
> the recover state fails as well, hw_error is triggered and the VM is
> aborted.
>
> To improve user experience a
I've pushed 5 new commits to this branch here (@Jonathan I've also made
a merge request to pull them into your branch).
https://gitlab.com/gourry.memverge/qemu/-/commits/cxl-2022-10-09
They're built on top of Jonathan's extensions for the CDAT since the
CDAT has memory region relevant entries a
On Mon, Oct 10, 2022 at 04:16:33PM -0700, David Woodhouse wrote:
> On Mon, 2022-10-10 at 15:08 -0400, Peter Xu wrote:
> > On Mon, Oct 10, 2022 at 10:39:52AM -0700, David Woodhouse wrote:
> > > On Mon, 2022-10-10 at 13:30 -0400, Michael S. Tsirkin wrote:
> > > > From: Peter Xu <
> > > > pet...@redha
On Mon, 2022-10-10 at 15:08 -0400, Peter Xu wrote:
> On Mon, Oct 10, 2022 at 10:39:52AM -0700, David Woodhouse wrote:
> > On Mon, 2022-10-10 at 13:30 -0400, Michael S. Tsirkin wrote:
> > > From: Peter Xu <
> > > pet...@redhat.com
> > >
> > >
> > > It's true that when vcpus<=255 we don't require t
On Mon, Oct 10, 2022 at 03:29:38PM -0700, Ira wrote:
> From: Ira Weiny
>
> CXL Event records inform the OS of various CXL device events. Thus far CXL
> memory devices are emulated and therefore don't naturally have events which
> will occur.
>
> Add mock events and a HMP trigger mechanism to fa
From: Ira Weiny
CXL Event records inform the OS of various CXL device events. Thus far CXL
memory devices are emulated and therefore don't naturally have events which
will occur.
Add mock events and a HMP trigger mechanism to facilitate guest OS testing of
event support.
This support requires
From: Ira Weiny
Replace the stubbed out CXL Get/Clear Event mailbox commands with
commands which return the mock event information.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-device-utils.c | 1 +
hw/cxl/cxl-mailbox-utils.c | 103 +++--
2 files changed, 101 inse
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
---
include/qemu/uuid.h | 12
1 file changed, 12 insertions(+)
From: Ira Weiny
To facilitate testing of guest software add mock events and code to
support iterating through the event logs.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-events.c | 248
hw/cxl/meson.build | 1 +
include/hw/cxl/cxl_device.h |
From: Ira Weiny
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Signed-off-by: Ira Weiny
---
hw/cxl/cxl-mailbox-utils.c | 129 ++--
include/hw/cxl/cxl_eve
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Signed-off-by: Ira Weiny
---
include/qemu/bswap.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index 346d05f2aab3..08e607821102 100644
--- a
From: Ira Weiny
To facilitate testing of event interrupt support add a QMP HMP command
to reset the event logs and issue interrupts when the guest has enabled
those interrupts.
Signed-off-by: Ira Weiny
---
hmp-commands.hx | 14 +++
hw/cxl/cxl-events.c | 82 +
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved VPRTYBW and VPRTYBD to use gvec and both of them and VPRTYBQ to
decodetree. VPRTYBW and VPRTYBD now also use .fni4 and .fni8,
respectively.
vprtybw:
reptloopmaster patch
8
Hang tight, I'm whipping up a multi-region patch that will support a
vmem and pmem region and such. Finally got oriented enough to figure
out the DPA decoding a bit. I will probably need some help validating
the decoder logic and the CDAT table logic.
I will integrate the suggestions below int
From: "Lucas Mateus Castro (alqotel)"
Used gvec to translate XVTSTDCSP and XVTSTDCDP.
xvtstdcsp:
reptloopimm prev versioncurrent version
25 40000 0,0475500,040820 (-14.2%)
25 40001 0,0695200,053520 (-23.0%)
25 4000
On Mon, 10 Oct 2022, Davidlohr Bueso wrote:
This hides requirement details as to the necessary changes that are needed for
volatile support - for example, build_dvsecs(). Imo using two backends (without
breaking current configs, of course) should be the initial version, not
something
to leave p
From: "Lucas Mateus Castro (alqotel)"
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now that part was
moved to the decodetree with the rest.
xvts
On 10/10/2022 16:42, Richard Henderson wrote:
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
+/* test if +Inf or -Inf */
+static void gen_is_any_inf(unsigned vece, TCGv_vec t, TCGv_vec b)
+{
+ uint64_t exp_msk = (vece == MO_32) ? (uint32_t)EXP_MASK_SP :
EXP_MASK_DP;
+ uint64_t
From: "Lucas Mateus Castro (alqotel)"
Moved XVTSTDCSP and XVTSTDCDP to decodetree an restructured the helper
to be simpler and do all decoding in the decodetree (so XB, XT and DCMX
are all calculated outside the helper).
Obs: The tests in this one are slightly different, these are the sum of
the
From: "Lucas Mateus Castro (alqotel)"
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to
translate them.
vabsdub:
reptloopmaster patch
8 12500 0,03601600 0,00688500 (-80.9%)
25 40000,03651000 0,00532100 (-85.4%)
100 10000
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now th
From: "Lucas Mateus Castro (alqotel)"
Moved the instructions VAVGUB, VAVGUH, VAVGUW, VAVGSB, VAVGSH, VAVGSW,
to decodetree and use gvec with them. For these one the right shift
had to be made before the sum as to avoid an overflow, so add 1 at the
end if any of the entries had 1 in its LSB as to
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
+/* test if +Inf or -Inf */
+static void gen_is_any_inf(unsigned vece, TCGv_vec t, TCGv_vec b)
+{
+uint64_t exp_msk = (vece == MO_32) ? (uint32_t)EXP_MASK_SP : EXP_MASK_DP;
+uint64_t sgn_msk = (vece == MO_32) ? (uint32_t)SGN_MASK_SP :
From: "Lucas Mateus Castro (alqotel)"
Patches missing review: 3,5,9,11,12
v1 -> v2:
- Implemented instructions with fni4/fni8 and dropped the helper:
* VSUBCUW
* VADDCUW
* VPRTYBW
* VPRTYBD
- Reworked patch12 to only use gvec implementation with a few
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
From: "Lucas Mateus Castro (alqotel)"
Moved the instructions VNEGW and VNEGD to decodetree and used gvec to
decode it.
vnegw:
reptloopmaster patch
8 12500 0,01053200 0,00548400 (-47.9%)
25 40000,01030500 0,0039 (-62.2%)
100 10000,0
From: "Lucas Mateus Castro (alqotel)"
Moved XVCPSGNSP and XVCPSGNDP to decodetree and used gvec to translate
them.
xvcpsgnsp:
reptloopmaster patch
8 12500 0,00561400 0,00537900 (-4.2%)
25 40000,00562100 0,0040 (-28.8%)
100 10000,00
On Mon, Oct 10, 2022 at 10:39:52AM -0700, David Woodhouse wrote:
> On Mon, 2022-10-10 at 13:30 -0400, Michael S. Tsirkin wrote:
> > From: Peter Xu <
> > pet...@redhat.com
> > >
> >
> > It's true that when vcpus<=255 we don't require the length of 32bit APIC
> > IDs. However here since we already
From: "Lucas Mateus Castro (alqotel)"
Moved XVABSSP, XVABSDP, XVNABSSP,XVNABSDP, XVNEGSP and XVNEGDP to
decodetree and used gvec to translate them.
xvabssp:
reptloopmaster patch
8 12500 0,00477900 0,00476000 (-0.4%)
25 40000,00442800 0,0035330
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved XVCPSGNSP and XVCPSGNDP to decodetree and used gvec to translate
them.
xvcpsgnsp:
reptloopmaster patch
8 12500 0,00561400 0,00537900 (-4.2%)
25 40000,0
In R/W mode, files with spaces were never created on host side.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1176
Fixes: c79e243ed67683d6d06692bd7040f7394da178b0
Signed-off-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Kevin Wolf
---
block/vvfat.c | 2 +-
1 f
Hi,
When testing vvfat in read-write mode, I came across some blocking
problems when using Windows guests.
This patchset is not here to fix all problems of vvfat, but only the
main ones I encountered.
First patch allows setting/resetting the 'volume dirty' flag on
boosector, and the second one al
From: "Lucas Mateus Castro (alqotel)"
Moved VPRTYBW and VPRTYBD to use gvec and both of them and VPRTYBQ to
decodetree. VPRTYBW and VPRTYBD now also use .fni4 and .fni8,
respectively.
vprtybw:
reptloopmaster patch
8 12500 0,00991200 0,00626300 (-36.8%)
25
'reserved1' field in bootsector is used to mark volume dirty, or need to verify.
Allow writes to bootsector which only changes the 'reserved1' field.
This fixes I/O errors on Windows guests.
Resolves: https://bugs.launchpad.net/qemu/+bug/1889421
Signed-off-by: Hervé Poussineau
---
block/vvfat.c
From: "Lucas Mateus Castro (alqotel)"
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1. It also implemented a .fni4 version of thos
On Wed, Sep 7, 2022 at 18:18 Ani Sinha wrote:
> On Wed, Aug 31, 2022 at 10:23 AM Ani Sinha wrote:
> >
> > e820 reserved entries were used before the dynamic entries with fw
> config files
> > were intoduced. Please see the following change:
> > 7d67110f2d9a6("pc: add etc/e820 fw_cfg file")
> >
>
From: "Lucas Mateus Castro (alqotel)"
This patch moves VMHADDSHS and VMHRADDSHS to decodetree I couldn't find
a satisfactory implementation with TCG inline.
vmhaddshs:
reptloopmaster patch
8 12500 0,02983400 0,02648500 (-11.2%)
25 40000,02946000
From: "Lucas Mateus Castro (alqotel)"
This patch moves VMLADDUHM to decodetree a creates a gvec implementation
using mul_vec and add_vec.
reptloopmaster patch
8 12500 0,01810500 0,00903100 (-50.1%)
25 40000,01739400 0,00747700 (-57.0%)
100
On Thu, 06 Oct 2022, Gregory Price wrote:
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index bc1bb18844..dfec11a1b5 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -138,7 +138,7 @@ static ret_code cmd_firmware_update_get_info(struct cxl_cmd
*c
From: Igor Mammedov
align _DSM method in empty slot descriptor with
a populated slot position.
Expected change:
+Device (SE8)
+{
+Name (_ADR, 0x001D) // _ADR: Address
+Name (ASUN, 0x1D)
Method (_DSM, 4, Serial
On Mon, 2022-10-10 at 13:30 -0400, Michael S. Tsirkin wrote:
> From: Peter Xu <
> pet...@redhat.com
> >
>
> It's true that when vcpus<=255 we don't require the length of 32bit APIC
> IDs. However here since we already have EIM=ON it means the hypervisor
> will declare the VM as x2apic supported (
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-9-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/test
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-15-imamm...@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-
From: Igor Mammedov
Expected change:
+Device (SE8)
+{
+Name (_ADR, 0x001D) // _ADR: Address
+Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific
Method
From: Igor Mammedov
Numer of possible arguments to pass to a method is limited
in ACPI. The following patches will need to pass over more
parameters to PDSM method, will hit that limit.
Prepare for this by passing structure (Package) to method,
which let us workaround arguments limitation.
Pass
From: Igor Mammedov
No functional changes nor AML bytecode changes.
Consolidate code that generates empty and populated slot
descriptors. Besides eliminating duplication,
it helps consolidate conditions for generating
parts of Device{} desriptor in one place, which makes
code more compact and eas
From: Igor Mammedov
add ASUN variable to hotpluggable slots and use it
instead of _SUN which has the same value to reuse
_DMS code on both branches (hot- and non-hotpluggable).
No functional change.
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-10-imamm...@redhat.com>
Reviewed
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-5-imamm...@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 34 +
1 file changed, 34 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-t
From: Igor Mammedov
no functional change, align order of fields in empty slot
descriptor with a populated slot ordering.
Expected diff:
-Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+Name (_SUN, 0xX)
From: Igor Mammedov
HPET AML doesn't depend on piix4 nor q35, move code buiding it
to common scope to avoid duplication.
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-3-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-b
On Mon, 10 Oct 2022, Jonathan Cameron wrote:
I wonder if we care to emulate beyond 1 volatile and 1 persistent.
Sure devices might exist, but if we can exercise all the code paths
with a simpler configuration, perhaps we don't need to handle the
more complex ones?
Yes, I completely agree. 1 of
From: Igor Mammedov
An intermediate blobs update to keep changes (last 2 patches)
reviewable.
Includes refactored PDSM that uses Package argument for custom
parameters.
= PDSM taking package as arguments
Return (Local0)
}
-Method (PDSM, 6, Serialized)
+
From: Igor Mammedov
Expected change:
-Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+Name (_SUN, 0xX) // _SUN: Slot User Number
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-14-imam
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-2-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 32
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-12-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1
From: Peter Maydell
Coverity complains that in functions like pci_set_word_by_mask()
we might end up shifting by more than 31 bits. This is true,
but only if the caller passes in a zero mask. Help Coverity out
by asserting that the mask argument is valid.
Fixes: CID 1487168
Reviewed-by: Richard
From: Igor Mammedov
It's expected that hotpluggable slots will, get ASUN variable
and use that instead of _SUN with its _DSM method.
For example:
@@ -979,8 +979,9 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
Device (S18)
{
-
From: Igor Mammedov
.., it will help with code readability and make easier
to extend method in followup patches
Signed-off-by: Igor Mammedov
Message-Id: <20220701133515.137890-6-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-build.c |
From: Hal Martin
PATCH v1: add support for SMBIOS type 8 to qemu
PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
internal_reference: internal reference designator
external_reference: external reference designator
connector_type: hex value for port connector type (se
From: Laurent Vivier
Display feature names instead of bitmaps for host, guest, and
backend for VirtIODevices.
Display status names instead of bitmaps for VirtIODevices.
Display feature names instead of bitmaps for backend, protocol,
acked, and features (hdev->features) for vhost devices.
Decod
From: Laurent Vivier
This patch implements the HMP versions of the virtio QMP commands.
[Jonah: Adjusted hmp monitor output format for features / statuses
with their descriptions.]
Signed-off-by: Laurent Vivier
Signed-off-by: Jonah Palmer
Message-Id: <1660220684-24909-7-git-send-email
From: Laurent Vivier
These new commands show the internal status of a VirtIODevice's
VirtQueue and a vhost device's vhost_virtqueue (if active).
Signed-off-by: Laurent Vivier
Signed-off-by: Jonah Palmer
Message-Id: <1660220684-24909-5-git-send-email-jonah.pal...@oracle.com>
Reviewed-by: Michae
From: Igor Mammedov
HPET AML moved after PCI host bridge description (no functional change)
diff example for PC machine:
@@ -54,47 +54,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
}
}
-Scope (_SB)
-{
-Device (HPET)
-{
-
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