On Mon, Oct 3, 2022 at 2:16 PM Jim Shu <jim....@sifive.com> wrote:
>
> The maximum priority level is hard-coded when writing to interrupt
> priority register. However, when writing to priority threshold register,
> the maximum priority level is from num_priorities Property which is
> configured by platform.
>
> Also change interrupt priority register to use num_priorities Property
> in maximum priority level.
>
> Signed-off-by: Emmanuel Blot <emmanuel.b...@sifive.com>
> Signed-off-by: Jim Shu <jim....@sifive.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/intc/sifive_plic.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index af4ae3630e..f864efa761 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr,
> uint64_t value,
> if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
> uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
>
> - plic->source_priority[irq] = value & 7;
> - sifive_plic_update(plic);
> + if (value <= plic->num_priorities) {
> + plic->source_priority[irq] = value;
> + sifive_plic_update(plic);
> + }
> } else if (addr_between(addr, plic->pending_base,
> plic->num_sources >> 3)) {
> qemu_log_mask(LOG_GUEST_ERROR,
> --
> 2.17.1
>
>
