On Mon, Jan 10, 2022 at 10:31 PM Cédric Le Goater wrote:
>
> On 1/10/22 08:21, Troy Lee wrote:
> > This patch includes i3c instance in ast2600 soc.
> >
> > v2: Rebase to mainline QEMU
> >
> > Signed-off-by: Troy Lee
> > ---
> > hw/arm/aspeed_ast2600.c | 19 ++-
> > include/
Legacy PIC (8259) cannot be supported for TDX guests since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Make PIC the property of common x86
Hi Cedric,
On Mon, Jan 10, 2022 at 10:25 PM Cédric Le Goater wrote:
>
> Hello Troy,
>
> On 1/10/22 08:21, Troy Lee wrote:
> > Introduce a dummy AST2600 I3C model.
> >
> > Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
> > to reset the device controller and setup through d
For PIT, it's straightforward to merge microvm::pit and
pc_machine::pit_enabled into x86ms::pit
For PIC, move microvm::pic to x86ms:pic, which gives PC machine the
ability to dis-/en-able PIC and it's the preparation for future TDX
support.
Xiaoyao Li (2):
hw/i386: Make pit a property of common
Both pc and microvm have pit property individually. Let's just make it
the property of common x86 base machine type.
Signed-off-by: Xiaoyao Li
---
hw/i386/microvm.c | 27 +--
hw/i386/pc.c | 24 +++-
hw/i386/x86.c | 25 +
From: Wilfred Mallawa
The following change was made to rectify incorrectly set stride length
on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
discovered whilst attempting to fix a bug where a timer_interrupt was
not serviced on TockOS-OpenTitan.
[1] https://docs.opentitan
To record screencast, AVAssetWriter APIs were called for each
cocoa_update call.
Commands for start/stop recording were added to View menu.
AVFoundation, CoreMedia and CoreVideo were added as linking
dependencies.
Signed-off-by: Zhang Chen
---
meson.build| 6 +++
ui/cocoa.m | 132 +++
From: Wilfred Mallawa
The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
The CTRL register is @ 0x04.
This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS
Le 10/01/2022 à 20:17, Peter Maydell a écrit :
The clang in Ubuntu 18.04 (10.0.0-4ubuntu1) produces a warning
on the code added in commit f5ef0e518d03 where we use a
shifted expression in a boolean context:
../../linux-user/elfload.c:2423:16: error: converting the result of '<<' to a
boolean al
On Mon, Jan 10, 2022 at 04:36:13PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:32 PM
> >
> > Kernel mechanism for dynamically enabled XSAVE features
>
> there is no definition of "dynamically-enabled XSAVE features).
>
Thanks!
> > asks userspace VMM r
The default block size is same as to the THP size, which is either
retrieved from "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size"
or hardcoded to 2MB. There are flaws in both mechanisms and this
intends to fix them up.
* When "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size" is
used
This supports virtio-mem-pci device on "virt" platform, by simply
following the implementation on x86.
* This implements the hotplug handlers to support virtio-mem-pci
device hot-add, while the hot-remove isn't supported as we have
on x86.
* The block size is 512MB on ARM64 instea
This series supports virtio-mem-pci device, by simply following the
implementation on x86. The exception is the block size is 512MB on
ARM64 instead of 128MB on x86, compatible with the memory section
size in linux guest.
The work was done by David Hildenbrand and then Jonathan Cameron. I'm
taking
Anup Patel 於 2021年12月30日 週四 下午8:41寫道：
> From: Anup Patel
>
> The AIA specificaiton adds interrupt filtering support for M-mode
> and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
> take local interrupt 13 or above and selectively inject same local
> interrupt to lower privilege mo
On Mon, Jan 10, 2022 at 04:38:18PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:32 PM
> >
> > From: Jing Liu
> >
> > Intel introduces XFD faulting mechanism for extended
> > XSAVE features to dynamically enable the features in
> > runtime. If CPUID (EAX=0Dh,
On 1/11/2022 10:30 AM, Tian, Kevin wrote:
From: Zeng, Guang
Sent: Monday, January 10, 2022 5:47 PM
On 1/10/2022 4:40 PM, Tian, Kevin wrote:
From: Zhong, Yang
Sent: Friday, January 7, 2022 5:32 PM
From: Jing Liu
Extended feature has large state while current
kvm_xsave only allows 4KB. Use n
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 446 ++
target/riscv/helper.h | 37 ++
target/riscv/insn32.decode | 42 +++
target/riscv/in
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++
include/crypto/sm4.h | 6 +
targ
- reuse partial instructions of Zbb/Zbc extensions
- add brev8, packh, unzip, zip, etc.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 74 ++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode
This patchset implements RISC-V scalar crypto extension v1.0.0 version
instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
To test rvk imple
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b487a8282c..628a782ba9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -694,9 +694,23 @@ stat
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 +
target/riscv/csr.c | 74 +
target/riscv/p
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..b487a8282c 10064
Hi,
I found this brings an inconsistency and a flaw to scanout semantics and
think the inconsistency should be fixed or this should be reverted
before the next release comes up.
The inconsistency is in the handling of the console size. A guest
hardware (especially I'm looking at virtio-gpu-v
The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.
Suggested-by: Richard Henderson
Signed-off-by: Yanan Wang
---
Based on: softmmu/device_tree: Silence compiler warning with --enabl
On Mon, Jan 10, 2022 at 04:20:41PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:31 PM
> >
> > From: Jing Liu
> >
> > The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
> > are all zero, while spec actually introduces that bit 01
> > should indicate if
On Mon, Jan 10, 2022 at 04:23:47PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:31 PM
> >
> > From: Jing Liu
> >
> > AMX XTILECFG and XTILEDATA are managed by XSAVE feature
> > set. State component 17 is used for 64-byte TILECFG register
> > (XTILECFG state)
On Mon, Jan 10, 2022 at 03:15:44PM -0300, Fabiano Rosas wrote:
> powerpc_excp_40x applies only to the 405, so remove HV code and
> references to BookE.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 26 ++
> 1 file changed
On Mon, Jan 10, 2022 at 03:15:45PM -0300, Fabiano Rosas wrote:
> 405 has no MSR_HV and EPR is BookE only so we can remove it all.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 37 -
> 1 file changed, 37 deleti
On Mon, Jan 10, 2022 at 03:15:41PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
> ---
> I copied powerpc_excp_legacy verbatim in this commit so the next
> one has a clean diff. We can squash both commits before merging.
I think copying it verbatim then simplifying is a good idea, ev
On Mon, Jan 10, 2022 at 03:15:40PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
> ---
> target/ppc/cpu_init.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index a50ddaeaae..9097948e67 100644
> --- a/target/ppc/cpu_init.c
On Mon, Jan 10, 2022 at 03:15:39PM -0300, Fabiano Rosas wrote:
> Some bits described in the user manual are missing from msr_mask. Add
> them.
>
> Signed-off-by: Fabiano Rosas
> ---
> target/ppc/cpu_init.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/
On Mon, Jan 10, 2022 at 03:15:43PM -0300, Fabiano Rosas wrote:
> In powerpc_excp_40x the Critical exception is now for 405 only, so we
> can remove the BookE and G2 blocks.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 17 ++---
> 1
On Mon, Jan 10, 2022 at 03:15:46PM -0300, Fabiano Rosas wrote:
> There's no sc 1.
>
> We also only used env->nip because of the vhyp code, so change to
> 'vector' now.
I don't think this is right. The point with the env->nip change is
changing the PC as it appeared *before* saving it to SRR0, so
On Tue, Jan 11, 2022 at 01:04:14PM +1100, David Gibson wrote:
> On Mon, Jan 10, 2022 at 03:15:39PM -0300, Fabiano Rosas wrote:
> > Some bits described in the user manual are missing from msr_mask. Add
> > them.
> >
> > Signed-off-by: Fabiano Rosas
> > ---
> > target/ppc/cpu_init.c | 6 +-
> >
> From: Zeng, Guang
> Sent: Monday, January 10, 2022 5:47 PM
>
> On 1/10/2022 4:40 PM, Tian, Kevin wrote:
> >> From: Zhong, Yang
> >> Sent: Friday, January 7, 2022 5:32 PM
> >>
> >> From: Jing Liu
> >>
> >> Extended feature has large state while current
> >> kvm_xsave only allows 4KB. Use new X
On Tue, Jan 11, 2022 at 12:49 AM Peter Maydell wrote:
>
> On Mon, 10 Jan 2022 at 03:40, Jason Wang wrote:
> >
> > The following changes since commit df722e33d5da26ea8604500ca8f509245a0ea524:
> >
> > Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into
> > staging (2022-01-08 09
ping?
Thank you very much!
Dongli Zhang
On 12/10/21 6:16 AM, Dongli Zhang wrote:
> This patchset fixes the issue on passing 'host_status' to the guest kernel.
>
> The 1st patch fixes the erroneous usage of req->host_status.
>
> The 2nd patch is to pass the SCSI_HOST_ERROR to the guest kernel w
This patch introduces pnv-phb4 user creatable devices that are created
in a similar manner as pnv-phb3 devices, allowing the user to interact
with the PHBs directly instead of creating PCI Express Controllers that
will create a certain amount of PHBs per controller index.
We accomplish this by doi
Its only callers are inside pnv_phb4.c.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 52 +-
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/
Moving all phb4 properties setup to stk_realize() keeps this logic in
a single place instead of having it scattered between stk_realize() and
pec_realize().
'phb->index' can be retrieved using stack->stack_no and
pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that
was being used
Hi,
This new version contains the remaining v3 patches that weren't accepted
yet, which is the case of patches 10, 2 and 3.
There are fewer patches this time due to 2 design changes made: move the
phb property setup to stk_realize() and all XSCOM initialization to
phb4_realize().
As a note/TODO,
The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on
'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init()
and add_subregion() to phb4_realize() time is a natural thing to do
since it's strictly PHB related.
The remaining XSCOM initialization is also related to
At this moment, stack->phb is the plain PnvPHB4 device itself instead of
a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user creatable device.
We can't get rid of this attribute, sim
On Mon, Jan 10, 2022 at 11:52 AM Yifei Jiang via wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. Add kvm_riscv.h to place riscv specific interface.
>
> In addition, PLIC is created without M-mode PLIC contexts when KVM
> is enabled.
>
> Signed-off-by:
On Mon, Jan 10, 2022 at 6:29 PM John Snow wrote:
> Based-on: <20220110232521.1922962-1-js...@redhat.com>
> (jsnow/python staging branch)
>
Sorry, I goofed. This series accidentally re-includes these patches. You
can ignore the first four patches, or apply directly on top of
origin/mast
Thank you for your service!
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/PACKAGE.rst | 4 +-
python/README.rst | 2 +-
python/qemu/qmp/README.rst | 9 -
python/qemu/qmp/__init__.py | 396 --
Copy the docstrings out of qemu.qmp, adjusting them as necessary to
more accurately reflect the current state of this class.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/aqmp/legacy.py | 110 ++---
Now that we are fully switched over to the new QMP library, move it back
over the old namespace. This is being done primarily so that we may
upload this package simply as "qemu.qmp" without introducing confusion
over whether or not "aqmp" is a new protocol or not.
The trade-off is increased confus
Simply import the type defition from the new location.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
tests/qemu-iotests/iotests.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-i
After this patch, qemu.aqmp.legacy.QEMUMonitorProtocol no longer
inherits from qemu.qmp.QEMUMonitorProtocol. To do this, several
inherited methods need to be explicitly re-defined.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/aqmp
Shift these definitions over from the qmp package to the async qmp
package.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/aqmp/aqmp_tui.py | 3 +--
python/qemu/aqmp/legacy.py | 30 ++
python/qemu/qmp/
The next several commits copy some code from qemu.qmp to qemu.aqmp, then
delete qemu.qmp. In the interim, to prevent test failures, the duplicate
code detection needs to be silenced to prevent bisect problems with CI
testing.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
Note: I still need to adjust the logging. The problem now is that the
logging messages include the PID of the test process, so they need to be
filtered out. I'll investigate that for a follow-up.
Signed-off-by: John Snow
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
scripts/cpu-x86-uarch-abi.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/scripts/cpu-x86-uarch-abi.py b/scripts/cpu-x86-uarch-abi.py
inde
With the old library gone, there's nothing duplicated in the tree, so
the warning suppression can be removed.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/setup.cfg | 1 -
1 file changed, 1 deletion(-)
diff --git a/python/setup.cfg b/
For this commit, we only need to remove accommodations for the
synchronous QMP library.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
scripts/simplebench/bench_block_job.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/
This is the last vestige of the "aqmp" moniker surviving in the tree; remove it.
Signed-off-by: John Snow
---
python/qemu/qmp/{aqmp_tui.py => qmp_tui.py} | 12 ++--
python/setup.cfg| 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
rename python/qe
Signed-off-by: John Snow
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
scripts/cpu-x86-uarch-abi.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/scripts/cpu-x86-uarch-abi.py b/scripts/cpu-x86-uarch-abi.py
index 08acc52a81..8963d90f0b 1006
Async QMP always raises a "ConnectError" on any connection error which
houses the cause in a second exception. We can check if this root cause
was python's ConnectionError to determine a fairly similar condition to
the original error check here.
Signed-off-by: John Snow
Reviewed-by: Vladimir Seme
Creating an instance of qemu.aqmp.ExecuteError is too involved here, so
just drop the specificity down to a generic QMPError.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
scripts/render_block_graph.py | 8 +++-
1 file changed, 3 insertion
Remove the QEMU_PYTHON_LEGACY_QMP environment variable, making the
switch permanent. Update Exceptions and import paths as necessary.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/machine/machine.py | 18 +++---
python/
Copy the remaining type definitions from QMP into the qemu.aqmp.legacy
module. Now, users that require the legacy interface don't need to
import anything else but qemu.aqmp.legacy wrapper.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
python/qemu/aqmp/legacy.py | 22 +
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/qmp/qom.py| 5 +++--
python/qemu/qmp/qom_common.py | 3 ++-
python/qemu/qmp/qom_fuse.py | 11 ++-
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/pyth
We have a replacement for async QMP, but it doesn't have feature parity
yet. For now, then, port the old tool onto the new backend.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
python/qemu/aqmp/legacy.py | 3 +++
python/qemu/qmp/qmp_shell.py | 31 +--
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/README.rst | 2 +-
python/qemu/{qmp => aqmp}/qmp_shell.py | 0
python/setup.cfg | 2 +-
scripts/qmp/qmp-shell | 2 +-
4 files chang
asyncio can complain *very* loudly if you forget to back out of things
gracefully before the garbage collector starts destroying objects that
contain live references to asyncio Tasks.
The usual fix is just to remember to call aqmp.disconnect(), but for the
sake of the legacy wrapper and quick, one
This is in preparation for renaming qemu.aqmp to qemu.qmp. I should have
done this from this from the very beginning, but it's a convenient time
to make sure this churn is taken care of.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
python/qemu/aqmp/__init__.py | 6 +
In order to upload a QMP package to PyPI, I want to remove any scripts
that I am not 100% confident I want to support upstream, beyond our
castle walls.
Move most of our QMP utilities into the utils package so we can split
them out from the PyPI upload.
Signed-off-by: John Snow
Reviewed-by: Vlad
Reported-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: John Snow
---
python/qemu/aqmp/__init__.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/python/qemu/aqmp/__init__.py b/python/qemu/aqmp/__init__.py
index 880d5b6fa7..173556404d 100644
--- a/python/qemu/aqmp/__init__.
From: Stefan Weil
Fixes: b2fcb0c5754c2554b8406376e99a75e9e0a6b7bd
Signed-off-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: John Snow
Message-id: 20220107153019.504124-1...@weilnetz.de
Signed-off-by: John Snow
---
scripts/simplebench/bench-example.py | 2 +-
1 file changed,
This exception can be injected into any await statement. If we are
canceled via timeout, we want to clear the pending execution record on
our way out.
Signed-off-by: John Snow
Reviewed-by: Beraldo Leal
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
python/qemu/aqmp/qmp_client.py | 8 ++--
1
Cleanup related to commit ccd3b3b8112b670f, "qemu-option: warn for
short-form boolean options".
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Daniel P. Berrangé
---
python/qemu/qmp/qemu_ga_client.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
Based-on: <20220110232521.1922962-1-js...@redhat.com>
(jsnow/python staging branch)
GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-qmp-legacy-switch
CI: https://gitlab.com/jsnow/qemu/-/pipelines/445163212
Hi, this series is part of an effort to publish the qemu.qmp package on
PyP
Mypy 0.930, released Dec 22, changes the way argparse objects are
considered. Crafting a definition that works under Python 3.6 and an
older mypy alongside newer versions simultaneously is ... difficult,
so... eh. Stub it out with an 'Any' definition to get the CI moving
again.
Oh well.
Signed-of
It's a commonly needed definition, it can be re-exported by the root.
Signed-off-by: John Snow
Reviewed-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Beraldo Leal
---
python/qemu/aqmp/__init__.py | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/python/qemu/aqmp/__i
0.920 (Released 2021-12-15) is not entirely happy with the
way that I was defining _FutureT:
qemu/aqmp/protocol.py:601: error: Item "object" of the upper bound
"Optional[Future[Any]]" of type variable "_FutureT" has no attribute
"done"
Update it with something a little mechanically simpler that w
0.920 (Released 2021-12-15) is not entirely happy with the
way that I was defining _FutureT:
qemu/aqmp/protocol.py:601: error: Item "object" of the upper bound
"Optional[Future[Any]]" of type variable "_FutureT" has no attribute
"done"
Update it with something a little mechanically simpler that w
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec
31 and Jan 3) that appear to erroneously expect the qemu namespace to
have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but
appears to not understand a relative import within a namespace package.
Update the
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec
31 and Jan 3) that appear to erroneously expect the qemu namespace to
have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but
appears to not understand a relative import within a namespace package.
Update the
Mypy 0.930, released Dec 22, changes the way argparse objects are
considered. Crafting a definition that works under Python 3.6 and an
older mypy alongside newer versions simultaneously is ... difficult,
so... eh. Stub it out with an 'Any' definition to get the CI moving
again.
Oh well.
Signed-of
From: Stefan Weil
Fixes: b2fcb0c5754c2554b8406376e99a75e9e0a6b7bd
Signed-off-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: John Snow
Message-id: 20220107153019.504124-1...@weilnetz.de
Signed-off-by: John Snow
---
scripts/simplebench/bench-example.py | 2 +-
1 file changed,
The following changes since commit de3f5223fa4cf8bfc5e3fe1fd495ddf468edcdf7:
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7.0-pull-request'
into staging (2022-01-10 14:43:03 +)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/python-pull-reque
On Mon, 2022-01-10 at 15:34 +0800, Bin Meng wrote:
> CAUTION: This email originated from outside of Western Digital. Do
> not click on links or open attachments unless you recognize the
> sender and know that the content is safe.
>
>
> On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
> wrote:
>
On Mon, Jan 10, 2022 at 11:48 AM Yifei Jiang via wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> Reviewed-by: A
On Mon, Jan 10, 2022 at 11:57 AM Yifei Jiang via wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> Reviewed-by: Anup Patel
> ---
> target/riscv/kvm.c | 104 +
Thanks for looking at this Michael, I've an inline response below.
eric
On 1/6/22 04:45, Michael S. Tsirkin wrote:
On Wed, Dec 15, 2021 at 10:38:11AM -0500, Eric DeVolder wrote:
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeV
> On 11 Jan 2022, at 00:55, Alistair Francis wrote:
>
> they are referred to internally,
Ok, so things are a bit more complicated than I hoped.
I'll search for the names in the source code, and keep those referred
internally.
Thank you,
Liviu
On Sun, Jan 9, 2022 at 11:55 PM Bin Meng wrote:
>
> On Fri, Jan 7, 2022 at 10:27 AM Atish Patra wrote:
> >
> > Qemu virt machine can support few cache events and cycle/instret counters.
> > It also supports counter overflow for these events.
> >
> > Add a DT node so that OpenSBI/Linux kernel is a
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 188 +
1 file changed, 188 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index bb6c
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 845 ++
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h b/include/hw/acpi
On Mon, Jan 10, 2022 at 11:02 PM Liviu Ionescu wrote:
>
>
>
> > On 10 Jan 2022, at 14:10, Alistair Francis wrote:
> >
> > My guess would be keep *arm*/*aarch64*, keymaps, npcm7xx_bootrom.bin,
> > efi-* and linuxboot*/multiboot*. That should ensure that everything
> > works for you, but I'm just g
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
tests/qtest/bios-tables-test.c | 54 ++
1 file changed, 54 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bi
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
tests/data/acpi/mi
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
hw/i386/acpi-build.c | 15 +++
hw/i386/acpi-microvm.c | 15 +++
include/hw/acpi/erst.h | 5 +
3 files changed, 35 insertions(+)
diff --git a/hw/i386/acpi
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
tests/qtest/erst-test.c | 172
tests/qtest/meson.build | 2 +
2 files c
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
Acked-by: Ani Sinha
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 483d5c7..19db80e 100644
-
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.rst, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v12: 10jan2022
- Converted macros in build_
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