[PULL v2 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.16

[PULL v2 01/21] target/riscv: Update the ePMP CSR address

From: Alistair Francis Update the ePMP CSRs to match the 0.9.3 ePMP spec https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git

[PULL v2 05/21] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8

[PULL v2 00/21] riscv-to-apply queue

From: Alistair Francis The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac: Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-09-20 16:17:05 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git ta

[PULL v2 03/21] target/riscv: Expose interrupt pending bits as GPIO lines

From: Alistair Francis Expose the 12 interrupt pending bits in MIP as GPIO lines. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git

[PULL v2 02/21] target/riscv: Fix satp write

From: LIU Zhiwei These variables should be target_ulong. If truncated to int, the bool conditions they indicate will be wrong. As satp is very important for Linux, this bug almost fails every boot. Signed-off-by: LIU Zhiwei Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 2021

Re: [PATCH 21/30] tcg/loongarch: Implement tcg_out_call

Hi Richard, On 9/21/21 00:35, Richard Henderson wrote: On 9/20/21 9:31 AM, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +    } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { +    /* long jump: +/- 2GiB */ +    tcg_out_opc_pcaddu12i(s, TCG_REG_TMP

Re: [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64

Hi Richard, On 9/20/21 23:11, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +    case INDEX_op_bswap32_i32: +    tcg_out_opc_revb_2h(s, a0, a1); +    tcg_out_opc_rotri_w(s, a0, a0, 16); +    break; +    case INDEX_op_bswap64_i64: +    tcg_out_opc_revb_d(s, a0,

Re: [PATCH REBASED v5 2/2] spapr: nvdimm: Introduce spapr-nvdimm device

On Wed, Jul 07, 2021 at 09:57:31PM -0500, Shivaprasad G Bhat wrote: > If the device backend is not persistent memory for the nvdimm, there is > need for explicit IO flushes on the backend to ensure persistence. > > On SPAPR, the issue is addressed by adding a new hcall to request for > an explicit

Re: Rust in Qemu BoF followup: Rust vs. qemu platform support

On Mon, Sep 20, 2021 at 09:13:44AM +0100, Peter Maydell wrote: > On Mon, 20 Sept 2021 at 06:07, David Gibson > wrote: > > On Sat, Sep 18, 2021 at 01:01:35PM -0700, Richard Henderson wrote: > > > We dropped host support for sparcv8 (true 32-bit) a long time ago. > > > We only support sparcv9 in il

Re: [PATCH REBASED v5 1/2] spapr: nvdimm: Implement H_SCM_FLUSH hcall

On Wed, Jul 07, 2021 at 09:57:21PM -0500, Shivaprasad G Bhat wrote: > The patch adds support for the SCM flush hcall for the nvdimm devices. > To be available for exploitation by guest through the next patch. > > The hcall expects the semantics such that the flush to return > with one of H_LONG_BU

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Hi Richard, On 9/21/21 01:23, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   configure   | 4 +++-   meson.build | 4 +++-   2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1043ccce4f..f1bc85e71b 100755

Re: [PATCH 2/3] scsi: make io_timeout configurable

On 9/20/21 8:56 PM, Paolo Bonzini wrote: On Mon, Nov 16, 2020 at 7:31 PM Hannes Reinecke wrote: The current code sets an infinite timeout on SG_IO requests, causing the guest to stall if the host experiences a frame loss. This patch adds an 'io_timeout' parameter for SCSIDevice to make the SG_I

Re: [PATCH v2 38/53] qapi: introduce x-query-lapic QMP command

Hi Daniel, On 9/14/21 7:20 AM, Daniel P. Berrangé wrote: > This is a counterpart to the HMP "info lapic" command. It is being > added with an "x-" prefix because this QMP command is intended as an > adhoc debugging tool and will thus not be modelled in QAPI as fully > structured data, nor will it

Re: [PATCH 1/2] meson: introduce modules_arch

Hi, > But, in anyway, I'll still need to store the target architecture that > can use such core module, like I did here in this patch. Otherwise, > if I compile different targets at the same time, I'll end up with the > same problem of targets trying to load wrong modules. That all works just f

Re: [PATCH v2 23/23] test-clone-visitor: Correct an accidental rename

On 9/17/21 16:31, Markus Armbruster wrote: > Commit b359f4b203 "tests: Rename UserDefNativeListUnion to > UserDefListUnion" renamed test_clone_native_list() to > test_clone_list_union(). The function has nothing to do with unions. > Rename it to test_clone_list(). > > Signed-off-by: Markus Armbru

Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote: > The reset value of IPIDR should be zero for Freescale chipset, per > the following 2 manuals I checked: > > - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM) > - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)

Re: [PATCH v4 3/4] target/ppc: Convert debug to trace events (decrementer and IRQ)

On Mon, Sep 20, 2021 at 09:42:25AM +0200, Cédric Le Goater wrote: > On 9/20/21 09:34, David Gibson wrote: > > On Mon, Sep 20, 2021 at 08:12:02AM +0200, Cédric Le Goater wrote: > > > Signed-off-by: Cédric Le Goater > > > > So.. all the functions here are called *set_irq*, but you've named the > >

Re: [PATCH v9 0/7] pSeries FORM2 affinity support

On Mon, Sep 20, 2021 at 02:49:40PM -0300, Daniel Henrique Barboza wrote: > Hi, > > This version has a changed asked by Greg in patch 4, along with > Greg's R-bs. > > Changes from v8: > - added Greg's reviewed-by in patches 3, 5, 6 and 7 > - patch 4: > * changed get_associativity() to return a c

Re: [PATCH v9 7/7] spapr_numa.c: handle auto NUMA node with no distance info

On Mon, Sep 20, 2021 at 02:49:47PM -0300, Daniel Henrique Barboza wrote: > numa_complete_configuration() in hw/core/numa.c always adds a NUMA node > for the pSeries machine if none was specified, but without node distance > information for the single node created. > > NUMA FORM1 affinity code didn

Re: [PATCH v4 4/4] target/ppc: Fix 64-bit decrementer

On Mon, Sep 20, 2021 at 08:12:03AM +0200, Cédric Le Goater wrote: > The current way the mask is built can overflow with a 64-bit decrementer. > Use sextract64() to extract the signed values and remove the logic to > handle negative values which has become useless. > > Cc: Luis Fernando Fujita Pire

Re: [PATCH v9 6/7] spapr_numa.c: FORM2 NUMA affinity support

On Mon, Sep 20, 2021 at 02:49:46PM -0300, Daniel Henrique Barboza wrote: > The main feature of FORM2 affinity support is the separation of NUMA > distances from ibm,associativity information. This allows for a more > flexible and straightforward NUMA distance assignment without relying on > complex

[PULL 09/10] hw/core: Make do_unaligned_access noreturn

While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 3 ++- tar

[PULL 07/10] tcg/sparc: Drop inline markers

Let the compiler decide about inlining. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 45 +++--- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-tar

[PULL 05/10] tcg/mips: Unset TCG_TARGET_HAS_direct_jump

Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 12 +--- tcg/mips/tcg-target.c.inc | 23 +-- 2 files changed

[PULL 08/10] tcg/sparc: Introduce tcg_out_mov_delay

This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc/tcg

[PULL 04/10] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr

Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 6 +

[PULL 10/10] tcg/riscv: Remove add with zero on user-only memory access

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c16f96b401..dc8d8f1de2 1

[PULL 01/10] include/exec: Move cpu_signal_handler declaration

There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 13 + ta

[PULL 00/10] tcg patch queue, v2

: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210920 for you to fetch changes up to b21ba5dfe3f4a367910d490d10fa7c9fa76f1504: tcg/riscv: Remove add with zero on user-only memory access (2021-09-20 14:17:54 -0700) ---

[PULL 02/10] accel/tcg: Restrict cpu_handle_halt() to sysemu

From: Philippe Mathieu-Daudé Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn(): case EXCP_HALTED: /* during start-up the vCPU is reset and the thread is * kicked several times. If we don't ensu

[PULL 06/10] tcg/mips: Drop special alignment for code_gen_buffer

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/region.c | 91 1 file changed, 91 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index e64c3ea230..9cc30d4922 100644 --- a/tcg/region.c +++ b/tcg/region.c @@

[PULL 03/10] tcg/mips: Drop inline markers

Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 76 ++- 1 file changed, 27 insertions(+), 49 deletions(-) diff --g

[PATCH v3] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

From: Frank Chang When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is cal

Re: [PATCH v3 23/30] Hexagon HVX (target/hexagon) helper overrides - vector stores

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 218 +++ target/hexagon/helper.h | 1 + target/hexagon/op_helper.c | 5 + 3 files changed, 224 insertions(+) Acked-by: Richard Hende

Re: [PATCH v3 25/30] Hexagon HVX (target/hexagon) instruction decoding

On 9/20/21 2:24 PM, Taylor Simpson wrote: Add new file to target/hexagon/meson.build Signed-off-by: Taylor Simpson --- target/hexagon/mmvec/decode_ext_mmvec.h | 24 target/hexagon/decode.c | 24 +++- target/hexagon/mmvec/decode_ext_mmvec.c | 236 +++

Re: [PATCH v3 24/30] Hexagon HVX (target/hexagon) import semantics

On 9/20/21 2:24 PM, Taylor Simpson wrote: Imported from the Hexagon architecture library imported/allext.idef Top level file for all extensions imported/mmvec/ext.idefHVX instruction definitions Support functions added to target/hexagon/genptr.c Acked-by: Richard He

Re: [PATCH v3 22/30] Hexagon HVX (target/hexagon) helper overrides - vector loads

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 150 +++ 1 file changed, 150 insertions(+) Acked-by: Richard Henderson r~

Re: [PATCH v3 21/30] Hexagon HVX (target/hexagon) helper overrides - vector splat and abs

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 26 ++ 1 file changed, 26 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 20/30] Hexagon HVX (target/hexagon) helper overrides - vector compares

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 103 +++ 1 file changed, 103 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 19/30] Hexagon HVX (target/hexagon) helper overrides - vector logical ops

On 9/20/21 2:24 PM, Taylor Simpson wrote: +#define fGEN_TCG_V6_pred_xor(SHORTCODE) \ +tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_or_n(SHORTCODE) \ +do { \ +intptr_t tmpoff = offsetof(CPUHex

Re: [PATCH v3 18/30] Hexagon HVX (target/hexagon) helper overrides - vector max/min

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 34 ++ 1 file changed, 34 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 17/30] Hexagon HVX (target/hexagon) helper overrides - vector shifts

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 122 +++ 1 file changed, 122 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 15/30] Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 31 +++ 1 file changed, 31 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 16/30] Hexagon HVX (target/hexagon) helper overrides - vector add & sub

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 50 1 file changed, 50 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 0/9] optimize the downtime for vfio migration

Hi guys, Ping... I just sent out V3, please review on V3, thanks! 在 2021/9/9 14:06, Longpeng(Mike) 写道: > Hi guys, > > In vfio migration resume phase, the cost would increase if the > vfio device has more unmasked vectors. We try to optimize it in > this series. > > You can see the commit mess

[PATCH v3 9/9] vfio: defer to commit kvm irq routing when enable msi/msix

In migration resume phase, all unmasked msix vectors need to be setup when load the VF state. However, the setup operation would take longer if the VM has more VFs and each VF has more unmasked vectors. The hot spot is kvm_irqchip_commit_routes, it'll scan and update all irqfds that already assign

[PATCH v3 7/9] vfio: add infrastructure to commit the deferred kvm routing

'defer_kvm_irq_routing' indicates whether we should defer to commit the kvm routing. Signed-off-by: Longpeng(Mike) --- hw/vfio/pci.c | 43 ++- hw/vfio/pci.h | 1 + 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.

Re: [PATCH v3 08/30] Hexagon HVX (target/hexagon) semantics generator - part 2

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_helper_funcs.py | 112 ++-- target/hexagon/gen_helper_protos.py | 16 ++- target/hexagon/gen_tcg_funcs.py | 258 ++-- 3 files changed, 364 insertio

[PATCH v3 4/9] msix: simplify the conditional in msix_set/unset_vector_notifiers

'msix_function_masked' is synchronized with the device's config, we can use it to replace the complex conditional statementis in msix_set/unset_vector_notifiers. Signed-off-by: Longpeng(Mike) --- hw/pci/msix.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/pci/msix.

[PATCH v3 2/9] vfio: move re-enabling INTX out of the common helper

Move re-enabling INTX out, and the callers should decide to re-enable it or not. Signed-off-by: Longpeng(Mike) --- hw/vfio/pci.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index f7a3a13fb0..1e6797fd4b 100644 --- a/hw/vfio/

Re: [PATCH v3 09/30] Hexagon HVX (target/hexagon) C preprocessor for decode tree

On 9/20/21 2:24 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/gen_dectree_import.c | 13 + 1 file changed, 13 insertions(+) Acked-by: Richard Henderson r~

[PATCH v3 1/9] vfio: simplify the conditional statements in vfio_msi_enable

It's unnecessary to test against the specific return value of VFIO_DEVICE_SET_IRQS, since any positive return is an error indicating the number of vectors we should retry with. Signed-off-by: Longpeng(Mike) --- hw/vfio/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a

[PATCH v3 0/9] optimize the downtime for vfio migration

Hi guys, In vfio migration resume phase, the cost would increase if the vfio device has more unmasked vectors. We try to optimize it in this series. You can see the commit message in PATCH 9 for details. Patch 1-5 are simple cleanups and fixup. Patch 6-8 are the preparations for the optimization

[PATCH v3 8/9] Revert "vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration"

Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration") avoid inefficiently disabling and enabling vectors repeatedly and let the unmasked vectors to be enabled one by one. But we want to batch multiple routes and defer the commit, and only commit once out s

[PATCH v3 5/9] msix: reset poll_notifier to NULL if fail to set notifiers

'msix_vector_poll_notifier' should be reset to NULL in the error path in msix_set_vector_notifiers(). Signed-off-by: Longpeng(Mike) --- hw/pci/msix.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 67682289af..805770942b 100644 --- a/hw/pci/msix.c +++ b/hw

[PATCH v3 6/9] kvm: irqchip: extract kvm_irqchip_add_deferred_msi_route

Extract a common helper that add MSI route for specific vector but does not commit immediately. Signed-off-by: Longpeng(Mike) --- accel/kvm/kvm-all.c | 15 +-- include/sysemu/kvm.h | 6 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/accel/kvm/kvm-all.c b/acc

[PATCH v3 3/9] vfio: simplify the failure path in vfio_msi_enable

Use vfio_msi_disable_common to simplify the error handling in vfio_msi_enable. Signed-off-by: Longpeng(Mike) --- hw/vfio/pci.c | 16 ++-- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 1e6797fd4b..8e97ca93cf 100644 --- a/hw/vfio/pci

Re: [PATCH v3 07/30] Hexagon HVX (target/hexagon) semantics generator

On 9/20/21 2:24 PM, Taylor Simpson wrote: Add HVX support to the semantics generator Signed-off-by: Taylor Simpson --- target/hexagon/gen_semantics.c | 33 + target/hexagon/hex_common.py | 13 + 2 files changed, 46 insertions(+) Acked-by: Richa

Re: [PATCH v3 06/30] Hexagon HVX (target/hexagon) import macro definitions

On 9/20/21 2:24 PM, Taylor Simpson wrote: Imported from the Hexagon architecture library imported/allext_macros.def Top level macro include for all extensions imported/macros.def Scalar core macros (some HVX here) imported/mmvec/macros.defHVX macro defini

Re: [PATCH v3 05/30] Hexagon HVX (target/hexagon) macros

On 9/20/21 2:24 PM, Taylor Simpson wrote: macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 22 +++ target/hexagon/mmvec/macros.h | 341 ++ 2 files chang

Re: [PATCH v3 04/30] Hexagon HVX (target/hexagon) instruction attributes

On 9/20/21 2:23 PM, Taylor Simpson wrote: Signed-off-by: Taylor Simpson --- target/hexagon/attribs_def.h.inc | 22 ++ 1 file changed, 22 insertions(+) Acked-by: Richard Henderson r~

Re: [PATCH v3 02/30] Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core

On 9/20/21 2:23 PM, Taylor Simpson wrote: HVX is a set of wide vector instructions. Machine state includes vector registers (VRegs) vector predicate registers (QRegs) temporary registers for intermediate values store buffer (masked stores and scatter/gather) Signed-off-by: T

Re: [PATCH v2 22/23] tests/qapi-schema: Rename flat-union-* test cases to union-*

On Fri, Sep 17, 2021 at 04:31:33PM +0200, Markus Armbruster wrote: > Signed-off-by: Markus Armbruster > --- > 65 files changed, 48 insertions(+), 48 deletions(-) The diff is harder to read in email (due to file rename comparison sometimes going astray on short and similar file contents) when co

[PATCH v5 31/31] accel: Add missing AccelOpsClass::has_work() and drop SysemuCPUOps one

cpu_common_has_work() is the default has_work() implementation and returns 'false'. Explicit it for the QTest / HAX / HVF / NVMM / Xen accelerators and remove cpu_common_has_work(). Since there are no more implementations of SysemuCPUOps::has_work, remove it along with the assertion in cpu_has_wo

Re: [PATCH v4 11/20] nubus-device: add romfile property for loading declaration ROMs

Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit : > The declaration ROM is located at the top-most address of the standard slot > space. > > Signed-off-by: Mark Cave-Ayland > --- > hw/nubus/nubus-device.c | 44 +++- > include/hw/nubus/nubus.h | 6 ++ > 2

[PATCH v5 29/31] target/tricore: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/cpu.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f04..419fa624bd5 100644 --- a/target/tr

RE: [PATCH v3 15/30] Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov

> -Original Message- > From: Philippe Mathieu-Daudé On > Behalf Of Philippe Mathieu-Daudé > Sent: Monday, September 20, 2021 4:59 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: a...@rev.ng; Brian Cain ; > richard.hender...@linaro.org > Subject: Re: [PATCH v3 15/30] Hexagon HVX (ta

[PATCH v5 24/31] target/rx: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 25a4aa2976d..ac6b40b2716 100644 --- a/target/rx/cpu.c +++ b/targ

Re: [PATCH v3 15/30] Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov

On 9/20/21 23:24, Taylor Simpson wrote: > Signed-off-by: Taylor Simpson > --- > target/hexagon/gen_tcg_hvx.h | 31 +++ > 1 file changed, 31 insertions(+) > > diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h > index eb29566..bcd53d4 100644 > ---

[PATCH v5 20/31] target/openrisc: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f9..3c368a1bde7 100644 --- a/target/o

Re: [PATCH v5 05/31] sysemu: Introduce AccelOpsClass::has_work()

On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote: -g_assert(cc->has_work); -return cc->has_work(cpu); +if (cc->has_work) { +return cc->has_work(cpu); +} +if (cpus_accel->has_work) { +return cpus_accel->has_work(cpu); +} +g_assert_not_reached(); This m

[PATCH v5 18/31] target/mips: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e4..3639c03f8ea 100644 --- a/target/mips/cpu.

Re: [PATCH v5 12/31] target/cris: Restrict has_work() handler to sysemu

On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote: Restrict has_work() to sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/cris/cpu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

[PATCH v5 16/31] target/m68k: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d11895..ad5d26b5c9e 100644 --- a/target/m68k/cpu.c ++

Re: [PATCH v5 10/31] target/arm: Restrict has_work() handler to sysemu and TCG

On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote: Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 7 +-- target/arm/cpu_tcg.c | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~

[PATCH v5 28/31] target/sparc: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e83e305aa9d..4a63ed12644 100644 --- a/target/sparc/cpu.

[PATCH v5 30/31] target/xtensa: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595e..5cb19a88819 100644 --- a/ta

Re: [PATCH v5 08/31] accel/tcg: Implement AccelOpsClass::has_work() as stub

On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote: +static bool tcg_cpu_has_work(CPUState *cpu) +{ +CPUClass *cc = CPU_GET_CLASS(cpu); + +g_assert(cc->tcg_ops->has_work); +return cc->tcg_ops->has_work(cpu); +} Now, you're expecting cc->has_work to disappear as cc->tcg_ops->has_work a

[PATCH v5 26/31] target/sh4: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03c..fb2116dc52e 100644 --- a/target/sh4/cpu.c +++

[PATCH v5 22/31] target/ppc: Restrict has_work() handlers to sysemu and TCG

Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work() - SysemuCPUOps::has_work() implementation - to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu-qom.h | 4 +++- target/ppc/cpu_init.c | 24 ++-- 2 files changed,

[PATCH v5 09/31] target/alpha: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb4..1ca601cac5b 100644 --- a/target/alpha/cpu.

[PATCH v5 27/31] target/sparc: Remove pointless use of CONFIG_TCG definition

The SPARC target only support TCG acceleration. Remove the CONFIG_TCG definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé -

[PATCH v5 21/31] target/ppc: Introduce PowerPCCPUClass::has_work()

We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is a const structure, so to avoid creating multiple versions of the same structure, simply changing the has_work() handler, introduce yet another indirection with a has_work() handler in PowerPCCPUClass, and ppc_cpu_has_work() method which

Re: [PATCH v4 10/20] nubus-device: remove nubus_register_rom() and nubus_register_format_block()

Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit : > Since there is no need to generate a dummy declaration ROM, remove both > nubus_register_rom() and nubus_register_format_block(). These will shortly be > replaced with a mechanism to optionally load a declaration ROM from disk to > allow real imag

[PATCH v5 06/31] accel/kvm: Implement AccelOpsClass::has_work()

Implement KVM has_work() handler in AccelOpsClass and remove it from cpu_thread_is_idle() since cpu_has_work() is already called. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-accel-ops.c | 6 ++ softmmu/cpus.c| 2 +- 2 files changed, 7 i

[PATCH v5 25/31] target/s390x: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3a..df8ade9021d 100644 --- a/target/s390x/

[PATCH v5 04/31] hw/core: Un-inline cpu_has_work()

We want to make cpu_has_work() per-accelerator. Only declare its prototype and move its definition to softmmu/cpus.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 8 +--- softmmu/cpus.c| 8 2 files changed, 9 insertions(+)

[PATCH v5 14/31] target/hppa: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e8edd189bfc..be940ae2246 100644 --- a/target/hppa/cpu.c ++

[PATCH v5 05/31] sysemu: Introduce AccelOpsClass::has_work()

Introduce an accelerator-specific has_work() handler. Eventually call it from cpu_has_work(). Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/accel-ops.h | 5 + softmmu/cpus.c | 9 +++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/sysemu/a

[PATCH v5 03/31] hw/core: Restrict cpu_has_work() to sysemu

cpu_has_work() is only called from system emulation code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core

[PATCH v5 11/31] target/avr: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d70e34dd54..6d51f91ca2c 100644 --- a/target/avr/cpu.c +++ b/tar

[PATCH v5 23/31] target/riscv: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13575c14085..abb555a8bdb 100644 --- a/target/r

[PATCH v5 01/31] target/arm: Implement arm_v7m_cpu_has_work()

Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU. See the comments added in commit 7ecdaa4a963 ("armv7m: Fix condition check for taking exceptions") which eventually forgot to implement this has_work() handler: * ARMv7-M interrupt masking works differently than -A or -R. * There

[PATCH v5 19/31] target/nios2: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1e..9938d7c2919 100644 --- a/target/nios2/cpu.

Re: [PATCH v4 09/20] macfb: don't register declaration ROM

Le 20/09/2021 à 22:01, Laurent Vivier a écrit : > Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit : >> The macfb device is an on-board framebuffer and so is initialised by the >> system declaration ROM included within the MacOS toolbox ROM. >> >> Signed-off-by: Mark Cave-Ayland >> --- >> hw/displ

[PATCH v5 10/31] target/arm: Restrict has_work() handler to sysemu and TCG

Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 7 +-- target/arm/cpu_tcg.c | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ba0741b20e4..e11aa625a5f 100644 --- a/target/arm/cp

Re: [PATCH v3 2/3] monitor/hmp: add support for flag argument with value

On Mon, Sep 20, 2021 at 12:56:40PM +0200, Stefan Reiter wrote: > Adds support for the "-xS" parameter type, where "-x" denotes a flag > name and the "S" suffix indicates that this flag is supposed to take an > arbitrary string parameter. > > These parameters are always optional, the entry in the q

[PATCH v5 17/31] target/microblaze: Restrict has_work() handler to sysemu

Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925f..36e6e540483 100644 ---

[PATCH v5 00/31] accel: Move has_work() from SysemuCPUOps to AccelOpsClass

Missing review: - 0001-target-arm-Implement-arm_v7m_cpu_has_work.patch - 0005-sysemu-Introduce-AccelOpsClass-has_work.patch - 0008-accel-tcg-Implement-AccelOpsClass-has_work-as-stub.patch - 0010-target-arm-Restrict-has_work-handler-to-sysemu-and-T.patch - 0012-target-cris-Restrict-has_work-handler-

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