Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU.
See the comments added in commit 7ecdaa4a963 ("armv7m: Fix
condition check for taking exceptions") which eventually
forgot to implement this has_work() handler:
* ARMv7-M interrupt masking works differently than -A or -R.
* There is no FIQ/IRQ distinction.
The NVIC signal any pending interrupt by raising ARM_CPU_IRQ
(see commit 56b7c66f498: "armv7m: QOMify the armv7m container")
which ends setting the CPU_INTERRUPT_HARD bit in interrupt_request.
Thus arm_v7m_cpu_has_work() implementation is thus quite trivial,
we simply need to check for this bit.
Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Michael Davidsaver <mdavidsa...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/arm/cpu_tcg.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0d5adccf1a7..da348938407 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -23,6 +23,11 @@
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+static bool arm_v7m_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -920,6 +925,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->info = data;
#ifdef CONFIG_TCG
+ cc->has_work = arm_v7m_cpu_has_work;
cc->tcg_ops = &arm_v7m_tcg_ops;
#endif /* CONFIG_TCG */
--
2.31.1
