Re: A bug of Monitor Chardev ?

Hi Marc, 在 2021/5/22 0:59, Marc-André Lureau 写道: > Hi > > On Fri, May 21, 2021 at 8:56 PM Daniel P. Berrangé > wrote: > > On Fri, May 21, 2021 at 05:33:46PM +0100, Daniel P. Berrangé wrote: > > On Fri, May 21, 2021 at 10:43:36AM -0400, Peter Xu wrote: > >

Re: [PATCH_V3] Adding ifdefs to call the respective routines only when their configs are enabled

On 5/25/21 5:20 AM, Richard Henderson wrote: > On 5/24/21 7:58 PM, Swetha Joshi wrote: >> Signed-off-by: Swetha Joshi >> --- >>   target/arm/kvm64.c | 12 >>   1 file changed, 8 insertions(+), 4 deletions(-) > > You're still missing the commit message. > >> >> diff --git a/target/arm

Re: [PATCH] target/nios2: fix page-fit instruction count

ping On 11.05.2021 11:40, Pavel Dovgalyuk wrote: This patch fixes calculation of number of the instructions that fit the current page. It prevents creation of the translation blocks that cross the page boundaries. It is required for deterministic exception generation in icount mode. Signed-off-

Re: [PATCH] replay: fix watchpoint processing for reverse debugging

ping On 11.05.2021 12:11, Pavel Dovgalyuk wrote: This patch enables reverse debugging with watchpoints. Reverse continue scans the execution to find the breakpoints and watchpoints that should fire. It uses helper function replay_breakpoint() for that. But this function needs to access icount, w

[Bug 1891748] Re: qemu-arm-static 5.1 can't run gcc

I've been unable to replicate the crash with any of the instructions here. Certainly all the statically compiled unit tests work and I've just done a build of QEMU in an emulated Debian Buster (Armel) docker image. -- You received this bug notification because you are a member of qemu- devel-ml,

Re: [PATCH 0/2] vvfat: fix two crashes.

24.05.2021 20:33, Programmingkid wrote: On May 24, 2021, at 12:56 PM, Vladimir Sementsov-Ogievskiy wrote: 24.05.2021 19:06, Programmingkid wrote: On May 24, 2021, at 11:55 AM, Vladimir Sementsov-Ogievskiy wrote: 24.05.2021 18:41, Programmingkid wrote: On May 24, 2021, at 6:12 AM, Vladi

Re: [PATCH v3 4/6] gitlab-ci: Add ccache in $PATH and display statistics

On 5/24/21 3:51 PM, Stefan Hajnoczi wrote: > On Fri, May 21, 2021 at 01:52:13PM +0100, Daniel P. Berrangé wrote: >> On Fri, May 21, 2021 at 02:27:26PM +0200, Philippe Mathieu-Daudé wrote: >>> On 5/21/21 1:53 PM, Daniel P. Berrangé wrote: On Fri, May 21, 2021 at 01:02:51PM +0200, Thomas Huth wr

Re: [PATCH v3 4/6] gitlab-ci: Add ccache in $PATH and display statistics

On 5/21/21 4:21 PM, Philippe Mathieu-Daudé wrote: > On 5/21/21 2:52 PM, Daniel P. Berrangé wrote: >> On Fri, May 21, 2021 at 02:27:26PM +0200, Philippe Mathieu-Daudé wrote: >>> On 5/21/21 1:53 PM, Daniel P. Berrangé wrote: On Fri, May 21, 2021 at 01:02:51PM +0200, Thomas Huth wrote: > On 2

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On Mon, May 24, 2021 at 12:55:07PM +0200, BALATON Zoltan wrote: > On Mon, 24 May 2021, David Gibson wrote: > > On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: > > > On Sun, 23 May 2021, BALATON Zoltan wrote: > > > > On Sun, 23 May 2021, Alexey Kardashevskiy wrote: > > > > > One thin

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On Mon, May 24, 2021 at 10:46:26PM +1000, Alexey Kardashevskiy wrote: > > > On 24/05/2021 20:55, BALATON Zoltan wrote: > > On Mon, 24 May 2021, David Gibson wrote: > > > On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: > > > > On Sun, 23 May 2021, BALATON Zoltan wrote: > > > > > On

Re: [PATCH qemu v20] spapr: Implement Open Firmware client interface

On Mon, May 24, 2021 at 02:42:30PM +0200, BALATON Zoltan wrote: > On Mon, 24 May 2021, David Gibson wrote: > > On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: > > > On Sun, 23 May 2021, BALATON Zoltan wrote: > > > > On Sun, 23 May 2021, Alexey Kardashevskiy wrote: > > > > > One thin

[RFC v4 00/14] s390x cleanup

this is the next version of a cleanup series for s390x. v3 -> v4: take s390x part from Claudio and modify for the current master * "target/s390x: meson: add target_user_arch" - new patch, add target_user_arch to avoid the proliferation of #ifdef in target code. v2 -> v3: minor changes * "hw/s

Re: [PATCH v4 2/5] target/ppc: used ternary operator when registering MAS

On Mon, May 24, 2021 at 10:32:18AM -0700, Richard Henderson wrote: > On 5/24/21 6:59 AM, Bruno Larsen (billionai) wrote: > > The write calback decision when registering the MAS SPR has been turned > > into a ternary operation, rather than an if-then-else block. > > > > Signed-off-by: Bruno Larsen

Re: [PATCH v4 1/5] target/ppc: moved ppc_cpu_do_interrupt to cpu.c

On Mon, May 24, 2021 at 10:59:04AM -0300, Bruno Larsen (billionai) wrote: > Moved the ppc_cpu_do_interrupt function to cpu.c file, where it makes > more sense, and turned powerpc_excp not static, as it now needs to be > accessed from outside of excp_helper.c > > Signed-off-by: Bruno Larsen (billio

Re: [PATCH v3 01/33] block/nbd: fix channel object leak

25.05.2021 00:31, Eric Blake wrote: On Fri, Apr 16, 2021 at 11:08:39AM +0300, Vladimir Sementsov-Ogievskiy wrote: From: Roman Kagan nbd_free_connect_thread leaks the channel object if it hasn't been stolen. Unref it and fix the leak. Signed-off-by: Roman Kagan --- block/nbd.c | 1 + 1 fi

Re: [PATCH_V3] Adding ifdefs to call the respective routines only when their configs are enabled

On 5/24/21 8:23 PM, Swetha Joshi wrote: Where do I add the commit message? When you use git commit? About the outer if, so if config_arm_virt was enabled and if acpi_enabled Is true, we still need to make sure config_acpi_apei was enabled as well. Done in hw/arm/Kconfig: config ARM_VIRT ..

Re: [PATCH v1 2/8] gitlab: explicitly reference the upstream registry

On 5/20/21 7:42 PM, Alex Bennée wrote: > Since c8e6793903 ("containers.yml: build with docker.py tooling") we > don't need to manually pull stuff from the upstream repository. Just > set the -r field to explicitly use that rather than the current > registry. Yay! Reviewed-by: Philippe Mathieu-Dau

Re: [PATCH v1 7/8] gdbstub: tidy away reverse debugging check into function

Hi Alex, On 5/20/21 7:43 PM, Alex Bennée wrote: > In theory we don't need an actual record/replay to enact reverse > debugging on a purely deterministic system (i.e one with no external > inputs running under icount). Tidy away the logic into a little > function. > > Signed-off-by: Alex Bennée >

Re: [PATCH v1 3/8] gitlab: add special rule for the hexagon container

On 5/20/21 7:42 PM, Alex Bennée wrote: > The hexagon container is always manually built but of course not > everyone will be building it themselves and pushing to their > registries. We still need to create a "local" registry copy for the > actual gitlab tests to run. We don't build it in this case

Re: [PATCH v1 6/8] hmp-commands: expand type of icount to "l" in replay commands

On 5/20/21 7:43 PM, Alex Bennée wrote: > This is not a 32 bit number, it can (and most likely will) be quite a > big one. > > Signed-off-by: Alex Bennée > Reviewed-by: Pavel Dovgalyuk > --- > hmp-commands.hx | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Math

[PATCH v4 6/8] hw/arm/virt-acpi-build: Add explicit IORT idmap for smmuv3 node

From: Xingang Wang This add explicit IORT idmap info according to pci root bus number range, and only add smmu idmap for those which does not bypass iommu. For idmap directly to ITS node, this split the whole RID mapping to smmu idmap and its idmap. So this should cover the whole idmap for throu

[PATCH v4 7/8] hw/i386/acpi-build: Add explicit scope in DMAR table

From: Xingang Wang In DMAR table, the drhd is set to cover all pci devices when intel_iommu is on. This patch add explicit scope data, including only the pci devices that go through iommu. Signed-off-by: Xingang Wang --- hw/i386/acpi-build.c | 68 ++-- 1

[PATCH v4 4/8] hw/i386: Add a pc machine option to bypass iommu for primary bus

From: Xingang Wang Add a bypass_iommu pc machine option to bypass iommu translation for the primary root bus. The option can be used as manner: qemu-system-x86_64 -machine q35,bypass_iommu=true Signed-off-by: Xingang Wang --- hw/i386/pc.c | 18 ++ hw/pci-host/q35.c|

Re: [PATCH] hw/display/artist: Fix bug in coordinate extraction in artist_vram_read()

Hi Helge, On 5/24/21 10:23 PM, Helge Deller wrote: > The CDE desktop on HP-UX 10 shows wrongly rendered pixels when the local > screen > menu is closed. This bug was introduced by commit c7050f3f167b > ("hw/display/artist: Refactor x/y coordination extraction") which converted > the > coordinate

[PATCH v4 0/8] IOMMU: Add support for IOMMU Bypass Feature

From: Xingang Wang These patches add support for configure bypass_iommu on/off for pci root bus, including primary bus and pxb root bus. At present, all root bus will go through iommu when iommu is configured, which is not flexible, because in many situations the need for using iommu and bypass i

[PATCH v4 1/8] hw/pci/pci_host: Allow bypass iommu for pci host

From: Xingang Wang This add a bypass_iommu property for pci host, which indicates whether devices attached to the pci root bus will bypass iommu. In pci_device_iommu_address_space(), add a bypass_iommu check to avoid getting iommu address space for devices bypass iommu. Signed-off-by: Xingang Wa

[PATCH v4 8/8] hw/i386/acpi-build: Add bypass_iommu check when building IVRS table

From: Xingang Wang When building IVRS table, only devices which go through iommu will be scanned, and the corresponding ivhd will be inserted. Signed-off-by: Xingang Wang --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386

[PATCH v4 5/8] hw/pci: Add pci_bus_range to get bus number range

From: Xingang Wang This helps to get the bus number range of a pci bridge hierarchy. Signed-off-by: Xingang Wang --- hw/pci/pci.c | 15 +++ include/hw/pci/pci.h | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 27d588e268..7f18ea5ef5

[PATCH v4 3/8] hw/arm/virt: Add a machine option to bypass iommu for primary bus

From: Xingang Wang This add a bypass_iommu option for arm virt machine, the option can be used in this manner: qemu -machine virt,iommu=smmuv3,bypass_iommu=true Signed-off-by: Xingang Wang --- hw/arm/virt.c | 26 ++ include/hw/arm/virt.h | 1 + 2 files changed,

[PATCH v4 2/8] hw/pxb: Add a bypass iommu property

From: Xingang Wang This add a bypass_iommu property for pci_expander_bridge. The property can be used as: qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true Signed-off-by: Xingang Wang --- hw/pci-bridge/pci_expander_bridge.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/p

Re: [PATCH v3 4/9] target/ppc: overhauled and moved logic of storing fpscr

On Mon, May 24, 2021 at 07:01:20PM -0700, Richard Henderson wrote: > On 5/21/21 1:17 PM, Bruno Larsen (billionai) wrote: > > +uint32_t mask = 1u << bit; > > +if (env->fpscr & mask) { > > +ppc_store_fpscr(env, env->fpscr & ~mask); > > Oops, missed this during review but: > > fpsc

Re: [PATCH] target/arm: don't clobber ID_AA64ISAR1 pointer auth

On 5/24/21 8:29 PM, Richard Henderson wrote: On 5/24/21 1:43 AM, Jamie Iles wrote: The pointer auth properties are added to the max CPU type but the finalization happens for all CPUs.  It makes sense to be able to disable pointer authentication for the max CPU type, but for future CPUs that impl

Re: [PATCH v6 11/25] python: add pylint to pipenv

On Wed, May 12, 2021 at 07:12:27PM -0400, John Snow wrote: > We are specifying >= pylint 2.7.x for several reasons: > > 1. For setup.cfg support, added in pylint 2.5.x > 2. To specify a version that has incompatibly dropped >bad-whitespace checks (2.6.x) > 3. 2.7.x fixes "unsubscriptable" warn

Re: [PATCH] target/arm: don't clobber ID_AA64ISAR1 pointer auth

On 5/24/21 1:43 AM, Jamie Iles wrote: The pointer auth properties are added to the max CPU type but the finalization happens for all CPUs. It makes sense to be able to disable pointer authentication for the max CPU type, but for future CPUs that implement pointer authentication and have bits set

Re: [PATCH_V3] Adding ifdefs to call the respective routines only when their configs are enabled

On 5/24/21 7:58 PM, Swetha Joshi wrote: Signed-off-by: Swetha Joshi --- target/arm/kvm64.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) You're still missing the commit message. diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..47a4d9d831 100644

Re: [PATCH] hw/nvme/ctrl: fix functions style

On Fri, May 21, 2021 at 09:13:51AM +0200, Klaus Jensen wrote: On May 21 11:38, Gollu Appalanaidu wrote: Identify command related functions style fix. Signed-off-by: Gollu Appalanaidu --- hw/nvme/ctrl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw

[PATCH 2/2] tests/qtest/nvme-test: add boot partition read test

Add a test case for reading an NVMe Boot Partition without enabling the controller. Signed-off-by: Gollu Appalanaidu --- tests/qtest/nvme-test.c | 118 +++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nv

[PATCH 0/2] add boot partitions support and read test case

This series adds the boot partition feature as well test case for reading boot partition area. Gollu Appalanaidu (2): hw/nvme: add support for boot partiotions tests/qtest/nvme-test: add boot partition read test hw/nvme/ctrl.c | 200 hw/nvme/

[PATCH 1/2] hw/nvme: add support for boot partiotions

NVMe Boot Partitions provides an area that may be read by the host without initializing queues or even enabling the controller. This allows various platform initialization code to be stored on the NVMe device instead of some separete medium. This patch adds the read support for such an area, as we

[PATCH_V3] Adding ifdefs to call the respective routines only when their configs are enabled

Signed-off-by: Swetha Joshi --- target/arm/kvm64.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..47a4d9d831 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1403,7 +1403,10 @@ void kvm_arch_on

Re: [PATCH v6 07/25] python: add MANIFEST.in

On Wed, May 12, 2021 at 07:12:23PM -0400, John Snow wrote: > When creating a source distribution via 'python3 setup.py sdist', the > VERSION and PACKAGE.rst files aren't bundled by default. Create a > MANIFEST.in file that instructs the build tools to include these so that > installation from sourc

Re: [PATCH v7 00/92] target/arm: Implement SVE2

Patchew URL: https://patchew.org/QEMU/20210525010358.152808-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210525010358.152808-1-richard.hender...@linaro.org Subject: [PATCH v7 00/92]

Re: [PATCH v6 06/25] python: add directory structure README.rst files

On Wed, May 12, 2021 at 07:12:22PM -0400, John Snow wrote: > Add short readmes to python/, python/qemu/, python/qemu/machine, > python/qemu/qmp, and python/qemu/utils that explain the directory > hierarchy. These readmes are visible when browsing the source on > e.g. gitlab/github and are designed

[PATCH_V2 1/2] Adding ifdefs to call the respective routines only when their configs are enabled

From: Swetha Signed-off-by: Swetha --- target/arm/kvm64.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..724ce78265 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1403,7 +1403,10 @@ void

[PATCH_V2 2/2] Removed double declaration

--- target/arm/kvm64.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 724ce78265..47a4d9d831 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1405,8 +1405,8 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code,

Re: [PATCH v3 4/9] target/ppc: overhauled and moved logic of storing fpscr

On 5/21/21 1:17 PM, Bruno Larsen (billionai) wrote: +uint32_t mask = 1u << bit; +if (env->fpscr & mask) { +ppc_store_fpscr(env, env->fpscr & ~mask); Oops, missed this during review but: fpscr & ~(target_ulong)mask; Otherwise we clear high bits of fpscr incorrectly. r~

[PATCH v7 91/92] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0e832b2649..1ab97e38e0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -648,8 +64

[PATCH v7 86/92] target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly as M:vm and once correctly as rm. Remove the incorrect name and remove the incorrect decode. Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 4 ++-- target/arm/translate-neon.c | 2 +- 2 files changed, 3 insertions

[PATCH v7 88/92] target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not save much. Also, this will solve an upcoming naming problem. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 9 ++--- target/arm/translate-neon.c | 30 ++

[PATCH v7 85/92] target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 1a8fc7fb39..14a9d0d4d3 100644 --- a/target/

[PATCH v7 82/92] target/arm: Implement SVE2 fp multiply-add long

From: Stephen Long Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200504171240.11220-1-stepl...@quicinc.com> [rth: Rearrange to use float16_to_float32_by_bits.] Signed-off-by: Richard Henderson --- tar

Re: [PATCH] Adding ifdefs to call the respective routines only when their configs are enabled

Hey Richard, I think I submitted the wrong patch, sorry about that. I will go ahead and submit the correct commit id now. What I was trying to do was, when kvm is enabled and if we don't want to include CONFIG_ARM_VIRT or CONFIG_ACPI_APEI, compilation fails as virt_is_acpi_enabled() routine is def

[PATCH v7 71/92] target/arm: Implement SVE2 TBL, TBX

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200428144352.9275-1-stepl...@quicinc.com> [rth: rearrange the macros a little and rebase] Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 5 +++ t

Re: [PATCH v3 9/9] target/ppc: updated meson.build to support disable-tcg

On 5/21/21 1:17 PM, Bruno Larsen (billionai) wrote: updated build file to not compile some sources that are unnecessary if TCG is disabled on the system. Signed-off-by: Bruno Larsen (billionai) --- target/ppc/meson.build | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) Reviewed-

Re: [PATCH] Adding ifdefs to call the respective routines only when their configs are enabled

On 5/24/21 3:56 PM, Swetha Joshi wrote: From: Swetha Signed-off-by: Swetha What are you trying to accomplish? That's what belongs in the commit message that you omitted. +bool acpi_enabled = false; +#ifdef CONFIG_ARM_VIRT bool acpi_enabled = virt_is_acpi_enabled(vms); Of course

[PATCH v7 72/92] target/arm: Implement SVE2 FCVTNT

Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v7: Fix big-endian indexing. --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 4 target/arm/sve_helper.c| 20 +++

Re: [PATCH v3 6/9] target/ppc: moved ppc_cpu_do_interrupt to cpu.c

On 5/21/21 1:17 PM, Bruno Larsen (billionai) wrote: Moved the ppc_cpu_do_interrupt function to cpu.c file, where it makes more sense, and turned powerpc_excp not static, as it now needs to be accessed from outside of excp_helper.c Signed-off-by: Bruno Larsen (billionai) --- target/ppc/cpu.c

[PATCH v7 92/92] target/arm: Enable SVE2 and related extensions

Disable I8MM again for !have_neon during realize. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 2 ++ target/arm/cpu64.c | 13 + target/arm/cpu_tcg.c | 1 + 3 files changed, 16 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4eb0d2f85c..7aeb4b1

[PATCH v7 65/92] target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}

We're about to add more variations on this theme. Accept the inner loop for the _h variants, rather than keep it unrolled. Signed-off-by: Richard Henderson --- target/arm/vec_helper.c | 160 1 file changed, 29 insertions(+), 131 deletions(-) diff --git a

[PATCH v7 89/92] target/arm: Implement aarch32 VSUDOT, VUSDOT

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/neon-shared.decode | 6 ++ target/arm/translate-neon.c | 27 +++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h

[PATCH v7 46/92] target/arm: Implement SVE2 FMMLA

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-stepl...@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helpe

[PATCH v7 75/92] target/arm: Implement SVE2 FLOGB

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200430191405.21641-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fixed esz index and c++ comments v3: Fixed denormal arithmetic and raise invalid. v7: Rewrite; handle denormal exceptions and flush to zero. --- tar

[PATCH v7 90/92] target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE, and V{S,U,US}MMLA.S8 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 target/arm/neon-shared.decode | 7 target/arm/sve.decode | 6 +++ target/arm/tran

[PATCH v7 57/92] target/arm: Implement SVE2 saturating multiply (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 12 target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 14 ++ 4 files changed, 51 insertions(+) diff --git

[PATCH v7 87/92] target/arm: Split out do_neon_ddda

Split out a helper that can handle the 4-register format for helpers shared with SVE. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 90 - 1 file changed, 38 insertions(+), 52 deletions(-) diff --git a/target/arm/translate-neon.c b/target/

[PATCH v7 74/92] target/arm: Implement SVE2 FCVTXNT, FCVTX

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-4-stepl...@quicinc.com> [rth: Use do_frint_mode, which avoids a specific runtime helper.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 2 ++ target/arm/translate-s

[PATCH v7 67/92] target/arm: Implement SVE mixed sign dot product

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 1 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 1 + 4 files changed, 22 insertions(+) diff --git a/target/arm/helper.h b/targ

[PATCH v7 83/92] target/arm: Implement aarch64 SUDOT, USDOT

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/translate-a64.c | 25 + 2 files changed, 30 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c75601b221..b2b684df55 100644 --- a/target/a

[PATCH v7 84/92] target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register format for helpers shared with SVE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 98 - 1 file changed, 43 insertions(+), 55 deletions(-) diff --git a/target/ar

[PATCH v7 81/92] target/arm: Move endian adjustment macros to vec_internal.h

We have two copies of these, one set of which is not complete. Move them to a common header. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 24 target/arm/sve_helper.c | 16 target/arm/vec_helper.c | 12

[PATCH v7 63/92] target/arm: Implement SVE2 complex integer dot product

Signed-off-by: Richard Henderson --- v7: Rebasing dropped from v6. --- target/arm/helper-sve.h| 10 target/arm/sve.decode | 9 target/arm/sve_helper.c| 99 ++ target/arm/translate-sve.c | 17 +++ 4 files changed, 135 insertions(+) d

[PATCH v7 53/92] target/arm: Implement SVE2 integer multiply (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v7: Split arguments to do_sve2_zzz_data. --- target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 30 ++ 2 files changed, 37 insertions(+) diff --git a/target/arm/sve.decode b/target/arm

[PATCH v7 80/92] target/arm: Implement SVE2 bitwise shift immediate

From: Stephen Long Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200430194159.24064-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 33 + target/arm/sve.decod

[PATCH v7 58/92] target/arm: Implement SVE2 signed saturating doubling multiply high

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 + target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 18 target/arm/vec_helper.c| 84 ++ 4 files changed, 116 insertions(+) diff --

[PATCH v7 79/92] target/arm: Implement 128-bit ZIP, UZP, TRN

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 29 +-- target/arm/translate-sve.c | 58 ++ 4 files changed, 90 insertions(

[PATCH v7 78/92] target/arm: Implement SVE2 LD1RO

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v7: Fix replication and tail clearing vs e2e7168a214. --- target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 93 ++ 2 files changed, 97 insertions(+) diff --git a/target/arm/sve.dec

[PATCH v7 70/92] target/arm: Implement SVE2 crypto constructive binary operations

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 3 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 384c92eebb..c75

[PATCH v7 45/92] target/arm: Implement SVE2 gather load insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar

[PATCH v7 77/92] target/arm: Tidy do_ldrq

Use tcg_constant_i32 for passing the simd descriptor, as this hashed value does not need to be freed. Rename dofs to doff to match poff. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/arm/tr

[PATCH v7 68/92] target/arm: Implement SVE2 crypto unary operations

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 11 +++ 2 files changed, 17 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 9f037fe5a7..a9cf3bea3e 100644 --- a/target/arm/

[PATCH v7 50/92] target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 +++ target/arm/translate-a64.c |

[PATCH v7 73/92] target/arm: Implement SVE2 FCVTLT

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v7: Fix big-endian indexing. --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 2 ++ target/arm/sve_h

[PATCH v7 76/92] target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. The lack of MTE handling in do_ldrq was a bug, fixed by this change. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 254 ++--

[PATCH v7 60/92] target/arm: Implement SVE2 multiply-add long (indexed)

Signed-off-by: Richard Henderson --- v7: Rebasing dropped from v6. --- target/arm/helper-sve.h| 17 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 16 target/arm/translate-sve.c | 20 4 files changed, 71

[PATCH v7 52/92] target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more. Split FMLA from FMLS to avoid an extra sub field; similarly for SDOT from UDOT. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 29 +++-- target/arm/translate-sve.c | 38 +++

[PATCH v7 62/92] target/arm: Implement SVE2 complex integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- v7: Rebasing dropped from v6. --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 12 target/arm/sve_helper.c| 28 target/arm/translate-sve.c | 15 +++ 4 files changed, 64 insert

[PATCH v7 69/92] target/arm: Implement SVE2 crypto destructive binary operations

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 38 ++ 3 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cp

[PATCH v7 51/92] target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 04ef38f148..a

[PATCH v7 59/92] target/arm: Implement SVE2 saturating multiply high (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 8 target/arm/vec_helper.c| 88 ++ 4 files changed, 118 insertions(+) diff --g

[PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h}

We're about to add more variations on this theme. Signed-off-by: Richard Henderson --- target/arm/vec_helper.c | 82 ++--- 1 file changed, 20 insertions(+), 62 deletions(-) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 8b7269d8e1..cddf0

[PATCH v7 54/92] target/arm: Implement SVE2 integer multiply-add (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v7: Split arguments to do_sve2__data. --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 31 +++ 2 files changed, 39 insertions(+) diff --git a/target/arm/sve.decode b/target/

[PATCH v7 42/92] target/arm: Implement SVE2 HISTCNT, HISTSEG

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. v4: Fix histseg counting (zhiwei). --- target/arm/helper-sve.h| 7 ++

[PATCH v7 66/92] target/arm: Implement SVE mixed sign dot product (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v7: Macroize the helpers. --- target/arm/cpu.h | 5 + target/arm/helper.h| 4 target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 2 ++ 5

[PATCH v7 47/92] target/arm: Implement SVE2 SPLICE, EXT

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200423180347.9403-1-stepl...@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +-- target/arm/translate-sve.c | 35 +

[PATCH v7 61/92] target/arm: Implement SVE2 integer multiply long (indexed)

Signed-off-by: Richard Henderson --- v7: Rebasing dropped from v6. --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 10 ++ target/arm/sve_helper.c| 6 ++ target/arm/translate-sve.c | 10 ++ 4 files changed, 31 insertions(+) diff --git a/target/arm/

[PATCH v7 49/92] target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix double addition (zhiwei). v7: Split out type changes. --- target/arm/hel

[PATCH v7 35/92] target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON, there is no saturation flag. Create new entry points for SVE2 that do not set QC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/sve.decode | 5 ++ target/a

[PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 19 +++ 4 files changed, 76

[PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed)

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 8 target/arm/sve_helper.c| 36 target/arm/translate-sve.c | 8 4 files changed, 66 insertions

[PATCH v7 40/92] target/arm: Implement SVE2 SUBHNB, SUBHNT

From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-4-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ ta

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