From: Klaus Jensen
Fix same flawed logic in the handling of event masking. Before this
patch the device would erroneously
a) queue up events even though that event type is masked
b) issue AERs for queued events in response to events getting cleared
c) respond to new AERs with queued events
On 2020/10/16 下午1:51, Zhang Chen wrote:
From: Zhang Chen
Hi Jason, this series include latest COLO related patches.
please check and merge it.
Li Zhijian (2):
colo-compare: fix missing compare_seq initialization
colo-compare: check mark in mutual exclusion
Pan Nengyuan (1):
net/fil
On 17/10/2020 19.51, Philippe Mathieu-Daudé wrote:
> Hi Peter, Igor, Thomas,
>
> On 2/28/20 5:38 PM, Peter Maydell wrote:
>> From: Thomas Huth
>>
>> Old kernels from the Meego project can be used to check that Linux
>> is at least starting on these machines.
>>
>> Signed-off-by: Thomas Huth
>> R
+-- On Sun, 18 Oct 2020, BALATON Zoltan wrote --+
| The s->regs.[src|dst]_[xy] values should not be over 0x3fff because we mask
| them on register write in ati.c
Yes, those register values are set to zero(0).
| and here [src|dst]_[x|y] local variables are declared unsigned so negative
| value
There is no "version 2" of the "Lesser" General Public License.
It is either "GPL version 2.0" or "Lesser GPL version 2.1".
This patch replaces all occurrences of "Lesser GPL version 2" with
"Lesser GPL version 2.1" in comment section.
Signed-off-by: Chetan Pant
---
hw/ppc/ppce500_spin.c
On 9/26/2020 3:53 AM, Alex Williamson wrote:
On Wed, 23 Sep 2020 04:54:15 +0530
Kirti Wankhede wrote:
Create mapped iova list when vIOMMU is enabled. For each mapped iova
save translated address. Add node to list on MAP and remove node from
list on UNMAP.
This list is used to track dirty pa
Patchew URL: https://patchew.org/QEMU/20201019051953.90107-...@getutm.app/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201019051953.90107-...@getutm.app
Subject: [PATCH RESEND v2 0/9] iOS and Apple Silicon host sup
From: osy
https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
For < iOS 14, reverse engineered functions from libsystem_pthread.dylib is
implemented to handle APRR supported SoCs.
The following rules apply for JIT write protect:
* JIT write-
From: osy
This allows jailbroken devices with entitlements to switch the option off.
Signed-off-by: Joelle van Dyne
---
include/sysemu/tcg.h | 2 +-
accel/tcg/tcg-all.c | 27 +-
accel/tcg/translate-all.c | 60 +--
bsd-user/main.c
From: osy
iOS does not support ucontext natively for aarch64 and the sigaltstack is
also unsupported (even worse, it fails silently, see:
https://openradar.appspot.com/13002712 )
As a workaround we include a library implementation of ucontext and add it
as a build option.
Signed-off-by: Joelle
From: osy
The iOS toolchain does not use the host prefix naming convention. We add a
new option `--enable-cross-compile` that forces cross-compile even without
a cross_prefix.
Signed-off-by: Joelle van Dyne
---
configure | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff
From: osy
macOS 11/iOS 14 added preadv/pwritev APIs. Due to weak linking, configure
will succeed with CONFIG_PREADV even when targeting a lower OS version. We
therefore need to check at run time if we can actually use these APIs.
Signed-off-by: Joelle van Dyne
---
block/file-posix.c | 12 +
From: osy
Some hosts (iOS) have a sandboxed filesystem and do not provide low-level
APIs for interfacing with host block devices.
Signed-off-by: Joelle van Dyne
---
configure | 4
meson.build| 1 +
block/file-posix.c | 8 +++-
3 files changed, 12 insertions(+), 1 dele
From: osy
We will introduce mirror mapping for JIT segment with separate RX and RW
access. Adding 'const' hints will make it easier to identify read-only
accesses and allow us to easier catch bugs at compile time in the future.
Signed-off-by: Joelle van Dyne
---
include/tcg/tcg.h|
From: osy
On iOS, we cannot allocate RWX pages without special entitlements. As a
workaround, we can allocate a RX region and then mirror map it to a separate
RX region. Then we can write to one region and execute from the other one.
We also define `tcg_mirror_ptr_rw` and `tcg_code_ptr_rw` to re
These set of changes brings QEMU TCG to iOS devices and future Apple Silicon
devices. They were originally developed last year and have been working in the
UTM app. Recently, we ported the changes to master, re-wrote a lot of the build
script changes for meson, and broke up the patches into more di
From: osy
This introduces support for building for iOS hosts. When the correct Xcode
toolchain is used, iOS host will be detected automatically.
block: disable features not supported by iOS sandbox
slirp: disable SMB features for iOS
target: disable system() calls for iOS
tcg: use sys_icache_inv
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to the bug report.
https://bugs.launchpad.net/bugs/1253563
Title:
b
Thank you for your review.OK ,I will adapt them.
On 2020/10/17 17:57, Philippe Mathieu-Daudé wrote:
> On 10/17/20 11:35 AM, Bihong Yu wrote:
>> Signed-off-by: Bihong Yu
>> ---
>> migration/block.c | 36 ++--
>> migration/page_cache.c | 13 +++--
>>
With ZNS support in place, the majority of code in nvme_rw() has
become read- or write-specific. Move these parts to two separate
handlers, nvme_read() and nvme_write() to make the code more
readable and to remove multiple is_write checks that so far existed
in the i/o path.
This is a refactoring
nvme_write() now handles WRITE, WRITE ZEROES and ZONE_APPEND.
Signed-off-by: Dmitry Fomichev
---
hw/block/nvme.c | 95 +--
hw/block/trace-events | 1 -
2 files changed, 28 insertions(+), 68 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.
The emulation code has been changed to advertise NVM Command Set when
"zoned" device property is not set (default) and Zoned Namespace
Command Set otherwise.
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator.
Define t
Add two module properties, "max_active" and "max_open" to control
the maximum number of zones that can be active or open. Once these
variables are set to non-default values, these limits are checked
during I/O and Too Many Active or Too Many Open command status is
returned if they are exceeded.
Si
ZNS specification defines two zone conditions for the zones that no
longer can function properly, possibly because of flash wear or other
internal fault. It is useful to be able to "inject" a small number of
such zones for testing purposes.
This commit defines two optional device properties, "offl
Zone Descriptor Extension is a label that can be assigned to a zone.
It can be set to an Empty zone and it stays assigned until the zone
is reset.
This commit adds a new optional module property, "zone_descr_ext_size".
Its value must be a multiple of 64 bytes. If this value is non-zero,
it becomes
Added brief descriptions of the new device properties that are
now available to users to configure features of Zoned Namespace
Command Set in the emulator.
This patch is for documentation only, no functionality change.
Signed-off-by: Dmitry Fomichev
---
hw/block/nvme.c | 41
From: Niklas Cassel
Define the structures and constants required to implement
Namespace Types support.
Namespace Types introduce a new command set, "I/O Command Sets",
that allows the host to retrieve the command sets associated with
a namespace. Introduce support for the command set and enable
From: Niklas Cassel
Many CNS commands have "allocated" command variants. These include
a namespace as long as it is allocated, that is a namespace is
included regardless if it is active (attached) or not.
While these commands are optional (they are mandatory for controllers
supporting the namesp
This log page becomes necessary to implement to allow checking for
Zone Append command support in Zoned Namespace Command Set.
This commit adds the code to report this log page for NVM Command
Set only. The parts that are specific to zoned operation will be
added later in the series.
All incoming
In NVMe 1.4, a namespace must report an ID descriptor of UUID type
if it doesn't support EUI64 or NGUID. Add a new namespace property,
"uuid", that provides the user the option to either specify the UUID
explicitly or have a UUID generated automatically every time a
namespace is initialized.
Sugge
v6 -> v7:
- Introduce ns->iocs initialization function earlier in the series,
in CSE Log patch.
- Set NVM iocs for zoned namespaces when CC.CSS is set to
NVME_CC_CSS_NVM.
- Clean up code in CSE log handler.
v5 -> v6:
- Remove zoned state persistence code. Replace position-independen
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map),
> but if you check
> https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.
> -Original Message-
> From: Niklas Cassel
> Sent: Wednesday, October 14, 2020 9:01 AM
> To: Dmitry Fomichev
> Cc: Keith Busch ; Klaus Jensen
> ; Kevin Wolf ; Philippe
> Mathieu-Daudé ; Maxim Levitsky
> ; Fam Zheng ; Alistair Francis
> ; Matias Bjorling ;
> Damien Le Moal ; qemu-bl...@non
> -Original Message-
> From: Niklas Cassel
> Sent: Wednesday, October 14, 2020 7:59 AM
> To: Dmitry Fomichev
> Cc: Keith Busch ; Klaus Jensen
> ; Kevin Wolf ; Philippe
> Mathieu-Daudé ; Maxim Levitsky
> ; Fam Zheng ; Alistair Francis
> ; Matias Bjorling ;
> Damien Le Moal ; qemu-bl...@non
> -Original Message-
> From: Keith Busch
> Sent: Tuesday, October 13, 2020 8:51 PM
> To: Dmitry Fomichev
> Cc: Klaus Jensen ; Kevin Wolf
> ; Philippe Mathieu-Daudé ;
> Maxim Levitsky ; Fam Zheng ;
> Alistair Francis ; Matias Bjorling
> ; Niklas Cassel ;
> Damien Le Moal ; qemu-bl...@nongn
Hi Ivan,
On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Iva
The QEMU project has two machines (aarch64 and s390) that can be used
for jobs that do build and run tests. This introduces those jobs,
which are a mapping of custom scripts used for the same purpose.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.d/custom-runners.yml | 192 +
To have the jobs dispatched to custom runners, gitlab-runner must
be installed, active as a service and properly configured. The
variables file and playbook introduced here should help with those
steps.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD, and
As described in the included documentation, the "custom runner" jobs
extend the GitLab CI jobs already in place.
Those jobs are intended to run on hardware and/or Operating Systems
not provided by GitLab's shared runners.
Signed-off-by: Cleber Rosa
Reviewed-by: Daniel P. Berrangé
---
.gitlab-c
On Thu, Oct 15, 2020 at 09:29:40AM +0100, Daniel P. Berrangé wrote:
> On Wed, Oct 14, 2020 at 03:19:47PM -0400, Cleber Rosa wrote:
> > On Wed, Oct 14, 2020 at 02:59:58PM -0400, Cleber Rosa wrote:
> > > On Wed, Oct 14, 2020 at 06:30:09PM +0100, Daniel P. Berrangé wrote:
> > > >
> > > > This needs u
To run basic jobs on custom runners, the environment needs to be
properly set up. The most common requirement is having the right
packages installed.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD, and are intended to provide a reproducible
environment.
TL;DR: this should allow the QEMU maintainer to push to the staging
branch, and have custom jobs running on the project's aarch64 and
s390x machines. Simple usage looks like:
git push remote staging
./scripts/ci/gitlab-pipeline-status --verbose --wait
Long version:
The idea about a public
From: osy
macOS 11/iOS 14 added preadv/pwritev APIs. Due to weak linking, configure
will succeed with CONFIG_PREADV even when targeting a lower OS version. We
therefore need to check at run time if we can actually use these APIs.
Signed-off-by: Joelle van Dyne
---
block/file-posix.c | 12 +
From: osy
On iOS, we cannot allocate RWX pages without special entitlements. As a
workaround, we can allocate a RX region and then mirror map it to a separate
RX region. Then we can write to one region and execute from the other one.
We also define `tcg_mirror_ptr_rw` and `tcg_code_ptr_rw` to re
From: osy
We will introduce mirror mapping for JIT segment with separate RX and RW
access. Adding 'const' hints will make it easier to identify read-only
accesses and allow us to easier catch bugs at compile time in the future.
Signed-off-by: Joelle van Dyne
---
include/tcg/tcg.h|
From: osy
https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
For < iOS 14, reverse engineered functions from libsystem_pthread.dylib is
implemented to handle APRR supported SoCs.
The following rules apply for JIT write protect:
* JIT write-
From: osy
The iOS toolchain does not use the host prefix naming convention. We add a
new option `--enable-cross-compile` that forces cross-compile even without
a cross_prefix.
Signed-off-by: Joelle van Dyne
---
configure | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff
From: osy
This allows jailbroken devices with entitlements to switch the option off.
Signed-off-by: Joelle van Dyne
---
include/sysemu/tcg.h | 2 +-
accel/tcg/tcg-all.c | 27 +-
accel/tcg/translate-all.c | 60 +--
bsd-user/main.c
From: osy
This introduces support for building for iOS hosts. When the correct Xcode
toolchain is used, iOS host will be detected automatically.
block: disable features not supported by iOS sandbox
slirp: disable SMB features for iOS
target: disable system() calls for iOS
tcg: use sys_icache_inv
From: osy
iOS does not support ucontext natively for aarch64 and the sigaltstack is
also unsupported (even worse, it fails silently, see:
https://openradar.appspot.com/13002712 )
As a workaround we include a library implementation of ucontext and add it
as a build option.
Signed-off-by: Joelle
These set of changes brings QEMU TCG to iOS devices and future Apple Silicon
devices. They were originally developed last year and have been working in the
UTM app. Recently, we ported the changes to master, re-wrote a lot of the build
script changes for meson, and broke up the patches into more di
From: osy
Some hosts (iOS) have a sandboxed filesystem and do not provide low-level
APIs for interfacing with host block devices.
Signed-off-by: Joelle van Dyne
---
configure | 4
meson.build| 1 +
block/file-posix.c | 8 +++-
3 files changed, 12 insertions(+), 1 dele
This will allow us to share code between FloatParts and FloatParts128.
Signed-off-by: Richard Henderson
---
Cc: Alex Bennee
What do you think of this instead of inlining pick_nan_muladd
into the two muladd implementations?
r~
---
fpu/softfloat.c | 40
Public bug reported:
Running Fedora32 with virt-manager → libvirt → qemu I noticed that I
got no sound in my spice client. The VM is configured with a SPICE-
server and a QXL display, and in addition a VNC display.
Apparently when I remove the VNC display, then the sound is routed just
fine to t
Kludge when using Linux kernels to reach userland.
No device in DT -> no hardware initialization.
Linux 5.9 uses the RPI_FIRMWARE_GET_CLOCKS so we now need to
implement that feature too. Look like a cat and mouse game...
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 27
Add 2 variants of the raspi4:
- raspi4b1g:Raspberry Pi 4B (revision 1.1, with 1 GiB of RAM)
- raspi4b2g Raspberry Pi 4B (revision 1.2, with 2 GiB)
Example booting the 2GiB machine using content from [*]:
$ qemu-system-aarch64 -M raspi4b2g -serial stdio \
-kernel raspberrypi/firmw
The BCM2838 share the same peripheral base block from the BCM283x
family, but connects 4 Cortex-A72 cores via a GICv2.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/bcm2836.h | 3 +
hw/arm/bcm2836.c | 179 +++
hw/arm/trace-events |
Still not complete as we need to implement more firmware properties.
However state good enough for review, or in case someone want to work
on it and improve it.
Since RFC v1:
- Rebased
- Used recommendations from Luc
https://www.mail-archive.com/qemu-devel@nongnu.org/msg642450.html
Based-on: <2
On 9/25/2020 5:23 PM, Cornelia Huck wrote:
On Wed, 23 Sep 2020 04:54:09 +0530
Kirti Wankhede wrote:
Define flags to be used as delimeter in migration file stream.
Added .save_setup and .save_cleanup functions. Mapped & unmapped migration
region from these functions at source during saving o
On 9/26/2020 3:25 AM, Alex Williamson wrote:
On Wed, 23 Sep 2020 04:54:14 +0530
Kirti Wankhede wrote:
Call VFIO_IOMMU_DIRTY_PAGES ioctl to start and stop dirty pages tracking
for VFIO devices.
Signed-off-by: Kirti Wankhede
Reviewed-by: Dr. David Alan Gilbert
---
hw/vfio/migration.c | 3
On 10/1/2020 3:37 PM, Cornelia Huck wrote:
On Wed, 23 Sep 2020 04:54:11 +0530
Kirti Wankhede wrote:
Sequence during _RESUMING device state:
While data for this device is available, repeat below steps:
a. read data_offset from where user application should write data.
b. write data of data_
Patchew URL:
https://patchew.org/QEMU/20201018203334.1229243-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201018203334.1229243-1-richard.hender...@linaro.org
Subject: [PATCH] softflo
Confirmed, although "65% decrease" is on 0.44% of the total
execution for this test case, so the decrease isn't actually
noticeable.
Nevertheless, it's a simple enough change.
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henders
The Pi A is almost the first machine released.
It uses a BCM2835 SoC which includes a ARMv6Z core.
Example booting the machine using content from [*]
(we use the device tree from the B model):
$ qemu-system-arm -M raspi1ap -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
The Pi 3A+ is a stripped down version of the 3B:
- 512 MiB of RAM instead of 1 GiB
- no on-board ethernet chipset
Add it as it is a closer match to what we model.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/r
Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
Example booting the machine using content from [*]:
$ qemu-system-arm -M raspi0 -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
-dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
-append 'pr
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/bcm2836.h | 1 +
hw/arm/bcm2836.c | 34 ++
hw/arm/raspi.c | 2 ++
3 files changed, 37 insertions(+)
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836
The BCM2835 has only one core. Introduce the core_count field to
be able to use values different than BCM283X_NCPUS (4).
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2836.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/bcm2836.c b/
The realize() function is clearly composed of two parts,
each described by a comment:
void realize()
{
/* common peripherals from bcm2835 */
...
/* bcm2836 interrupt controller (and mailboxes, etc.) */
...
}
Split the two part, so we can reuse the common part with other
Add the raspi0/1/3A+ machines.
Missing review: #7 and #9
Since v2:
- Rebased
- Addressed Igor comment
- Added Luc R-b
- Added model 3A+
Since v1:
- Use more specific machine names
Based-on: <20201010135759.437903-1-...@lmichel.fr>
Supersedes: <20200217114533.17779-1-f4...@amsat.org>
Philippe M
It makes no sense to set enabled-cpus=0 on single core SoCs.
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2836.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index c5d46a8e805..fcb2c9c3e73
Remove usage of TypeInfo::class_data. Instead fill the fields in
the corresponding class_init().
So far all children use the same values for almost all fields,
but we are going to add the BCM2711/BCM2838 SoC for the raspi4
machine which use different fields.
Reviewed-by: Igor Mammedov
Signed-off
No code out of bcm2836.c uses (or requires) the BCM283XInfo
declarations. Move it locally to the C source file.
Reviewed-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/bcm2836.h | 8
hw/arm/bcm2836.c | 14 ++
2 files changed, 14 insertions(
This merges the int_to_float routine and the round_pack_canonical
routine into the same function, allowing the FloatParts structure
to be decomposed by the compiler.
This results in a 60-75% speedup of the flattened function.
Leave the narrower integer inputs to tail-call the int64_t version.
Bu
On 10/18/20 11:34 AM, Philippe Mathieu-Daudé wrote:
>> + g_assert(size != 0);
>
> "The alignment value, which must be an integer power of 2.",
> so maybe:
>
> g_assert(size != 0 && is_power_of_2(alignment));
This is also true of posix_memalign. If we are going to add this, we should
a
On 10/18/20 6:48 PM, Richard Henderson wrote:
We do not need or want to be allocating page sized quanta.
Signed-off-by: Richard Henderson
---
v3: Include ; use g_assert not assert.
---
util/oslib-win32.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/util/osl
Ping.
On 8/14/20 2:39 PM, Richard Henderson wrote:
> The architected pauth algorithm is quite slow without
> hardware support, and boot times for kernels that enable
> use of the feature have been significantly impacted.
>
> Version 1 blurb at
> https://lists.nongnu.org/archive/html/qemu-devel/
On 9/26/2020 2:32 AM, Alex Williamson wrote:
On Wed, 23 Sep 2020 04:54:10 +0530
Kirti Wankhede wrote:
Added .save_live_pending, .save_live_iterate and .save_live_complete_precopy
functions. These functions handles pre-copy and stop-and-copy phase.
In _SAVING|_RUNNING device state or pre-co
+vfio_migration_set_state(char *name, uint32_t state) " (%s) state %d"
+vfio_vmstate_change(char *name, int running, const char *reason, uint32_t dev_state)
" (%s) running %d reason %s device state %d"
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 8275c4c68f4
On 9/26/2020 1:50 AM, Alex Williamson wrote:
On Wed, 23 Sep 2020 04:54:09 +0530
Kirti Wankhede wrote:
Define flags to be used as delimeter in migration file stream.
Added .save_setup and .save_cleanup functions. Mapped & unmapped migration
region from these functions at source during saving
Am 18.10.20 um 18:48 schrieb Richard Henderson:
We do not need or want to be allocating page sized quanta.
Signed-off-by: Richard Henderson
---
v3: Include ; use g_assert not assert.
---
util/oslib-win32.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/util/
We do not need or want to be allocating page sized quanta.
Signed-off-by: Richard Henderson
---
v3: Include ; use g_assert not assert.
---
util/oslib-win32.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
index e99debfb8d..
On Sun, 18 Oct 2020 at 15:38, Lee <380121...@163.com> wrote:
> Ubuntu 14.04.6 LTS, X86_64
> I make source code of version qemu 5.1\5.0\4.2,and foud the error:glib-2.48
> gthread-2.0 is required to compile QEMU
> try apt-get install libglib2.0-dev,and it is sucess :
> Reading state information...
On Sun, Oct 18, 2020 at 8:59 AM Michael S. Tsirkin wrote:
>
> On Sun, Oct 18, 2020 at 08:54:36AM -0700, Andy Lutomirski wrote:
> > On Sun, Oct 18, 2020 at 8:52 AM Michael S. Tsirkin wrote:
> > >
> > > On Sat, Oct 17, 2020 at 03:24:08PM +0200, Jason A. Donenfeld wrote:
> > > > 4c. The guest kernel
From: BALATON Zoltan
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables.
Signed-
On 17/10/2020 21:13, BALATON Zoltan via wrote:
This is inspired by Mark's series:
https://lists.nongnu.org/archive/html/qemu-ppc/2020-10/msg00251.html
and implements what I've suggested in review of that series to
simplify it and avoid code churn if implementing my suggestion later.
Regards,
From: BALATON Zoltan via
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to loading a binary image with -bios if
loading ELF image failed. This allows testing emulation with a ROM
image from real hardware as well as using an ELF OpenBIOS image.
S
From: BALATON Zoltan
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Reviewed-by: P
Now that all of the callers of this function have been switched to use qdev
properties, this legacy init function can now be removed.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20201016182739.22875-6-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Dau
Signed-off-by: Mark Cave-Ayland
Message-Id: <20201016182739.22875-5-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc405_boards.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
From: BALATON Zoltan
The board firmware expect these to be at fixed addresses and programs
them without probing, this patch puts the macio device at the expected
PCI address.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/
On 17/10/2020 16:56, BALATON Zoltan via wrote:
If you can send a v9 with the cast fixed I'll apply this to my qemu-macppc branch
right away.
You could've really just edit the single cast in patch 1 before applying to change
the it back but I've resent the changed patch 1 as v9 also adding you
Signed-off-by: Mark Cave-Ayland
Message-Id: <20201016182739.22875-4-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
hw/sparc64/sun4u.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a
Currently an object link property is used to pass a reference to the Heathrow
PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the Old Wor
This function is no longer used within the codebase.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20201016182739.22875-2-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
hw/r
Currently an object link property is used to pass a reference to the OpenPIC
into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the New World m
Signed-off-by: Mark Cave-Ayland
Message-Id: <20201016182739.22875-3-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
hw/sparc/sun4m.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
From: BALATON Zoltan
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
Signed-off-by: BALATON
On Sun, Oct 18, 2020 at 08:54:36AM -0700, Andy Lutomirski wrote:
> On Sun, Oct 18, 2020 at 8:52 AM Michael S. Tsirkin wrote:
> >
> > On Sat, Oct 17, 2020 at 03:24:08PM +0200, Jason A. Donenfeld wrote:
> > > 4c. The guest kernel maintains an array of physical addresses that are
> > > MADV_WIPEONFOR
Instead use qdev_prop_set_chr() to configure the ESCC serial chardevs at the
Mac Old World and New World machine level.
Also remove the now obsolete comment referring to the use of serial_hd() and
the setting of user_creatable to false accordingly.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20
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