Hi Ivan, On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.grif...@emdalo.com> wrote: > > I don't know why it isn't documented in that PDF (or in the register map), > but if you check > https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h > you'll see the following > > ``` > typedef struct > { > volatile uint32_t SOFT_RESET; > volatile uint32_t VDETECTOR; > volatile uint32_t TVS_CONTROL; > volatile uint32_t TVS_TEMP_A; > volatile uint32_t TVS_TEMP_B; > volatile uint32_t TVS_TEMP_C; > volatile uint32_t TVS_VOLT_A; > volatile uint32_t TVS_VOLT_B; > volatile uint32_t TVS_VOLT_C; > volatile uint32_t TVS_OUTPUT0; > volatile uint32_t TVS_OUTPUT1; > volatile uint32_t TVS_TRIGGER; > volatile uint32_t TRIM_VDET1P05; > volatile uint32_t TRIM_VDET1P8; > volatile uint32_t TRIM_VDET2P5; > volatile uint32_t TRIM_TVS; > volatile uint32_t TRIM_GDET1P05; > volatile uint32_t RESERVED0; > volatile uint32_t RESERVED1; > volatile uint32_t RESERVED2; > volatile uint32_t SERVICES_CR; > volatile uint32_t SERVICES_SR; > volatile uint32_t USER_DETECTOR_SR; > volatile uint32_t USER_DETECTOR_CR; > volatile uint32_t MSS_SPI_CR; > > } SCBCTRL_TypeDef; > > #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL)) > > /*2kB bytes long mailbox.*/ > #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL)) > ``` > > And in > https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c > you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with > the FPGA system controller to perform various services.
It's actually documented, but not in the PDF file. I also spent some time locating the doc when I do the DDR controller modeling work. See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map Regards, Bin
