Re: [PATCH v4 3/3] hw/misc/mos6522: move timer_new from init() into realize() to avoid memleaks

On Fri, Mar 06, 2020 at 09:56:52AM +1100, David Gibson wrote: > On Thu, Mar 05, 2020 at 02:54:22PM +0800, Pan Nengyuan wrote: > > There are some memleaks when we call 'device_list_properties'. This patch > > move timer_new from init into realize to fix it. > > > > Reported-by: Euler Robot > > Si

Re: [PATCH v4 00/10] Further bitmaps improvements

12.03.2020 23:41, John Snow wrote: On 3/12/20 1:59 AM, Vladimir Sementsov-Ogievskiy wrote: 11.03.2020 20:03, John Snow wrote: On 3/11/20 9:58 AM, Vladimir Sementsov-Ogievskiy wrote: 11.03.2020 12:55, Max Reitz wrote: On 11.03.20 07:17, Vladimir Sementsov-Ogievskiy wrote: 10.03.2020 20:17

Re: [PATCH] block/io: fix bdrv_co_do_copy_on_readv

13.03.2020 2:09, John Snow wrote: On 3/12/20 4:19 AM, Vladimir Sementsov-Ogievskiy wrote: Prior to 1143ec5ebf4 it was OK to qemu_iovec_from_buf() from aligned-up buffer to original qiov, as qemu_iovec_from_buf() will stop at qiov end anyway. But after 1143ec5ebf4 we assume that bdrv_co_do_cop

Re: [PATCH v9 00/10] error: auto propagated local_err part I

12.03.2020 17:24, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: v9 01: A lot of rewordings [thanks to Eric] Still, keep all r-b marks, assuming that they are mostly about macro definition 02: significant changes are: 1. Do not match double propagation pattern in ERRP

Re: [PATCH v9 02/10] scripts: Coccinelle script to use ERRP_AUTO_PROPAGATE()

12.03.2020 19:36, Markus Armbruster wrote: I may have a second look tomorrow with fresher eyes, but let's get this out now as is. Vladimir Sementsov-Ogievskiy writes: Script adds ERRP_AUTO_PROPAGATE macro invocation where appropriate and does corresponding changes in code (look for details in

Re: [PATCH RFC 0/9] Add riscv64 kvm accel support

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang wrote: > > Hi, > > This series adds riscv64 kvm support, It is based on riscv_kvm_master > branch at https://github.com/kvm-riscv/linux. > > This series depends on above pending changes which haven't yet been > accepted, so this QEMU patch series is bloc

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

On 3/12/20 3:10 PM, Alistair Francis wrote: >> I still think this must be a guest (or nested guest) bug related to clearing >> PTE bits and failing to flush the TLB properly. > > It think so as well now. I have changed the Linux guest and Hypervisor > to be very aggressive with flushing but still

[PATCH 1/4] spapr: Move creation of ibm, dynamic-reconfiguration-memory dt node

Currently this node with information about hotpluggable memory is created from spapr_dt_cas_updates(). But that's just a hangover from when we created it only as a diff to the device tree at CAS time. Now that we fully rebuild the DT as CAS time, it makes more sense to create this along with the

[PATCH 3/4] spapr: Rename DT functions to newer naming convention

In the spapr code we've been gradually moving towards a convention that functions which create pieces of the device tree are called spapr_dt_*(). This patch speeds that along by renaming most of the things that don't yet match that so that they do. For now we leave the *_dt_populate() functions wh

[PATCH 4/4] spapr: Fold spapr_node0_size() into its only caller

The Real Mode Area (RMA) needs to fit within the NUMA node owning memory at address 0. That's usually node 0, but can be a later one if there are some nodes which have no memory (only CPUs). This is currently handled by the spapr_node0_size() helper. It has only one caller, so there's not a lot

[PATCH 2/4] spapr: Move creation of ibm,architecture-vec-5 property

This is currently called from spapr_dt_cas_updates() which is a hang over from when we created this only as a diff to the DT at CAS time. Now that we fully rebuild the DT at CAS time, just create it alon with the rest of the properties in /chosen. Signed-off-by: David Gibson --- hw/ppc/spapr.c

[PATCH 0/4] spapr: Assorted minor cleanups

Here's a handful of cleanups that came out of larger bits of work but which aren't intimately tied to those. For one reason or another they got forgotten for a while, but I've now dug them out, polished them a bit and hope to get them in just in time for the qemu-5.0 soft freeze. David Gibson (4)

[PATCH RFC 9/9] target/riscv: add host riscv64 cpu type

Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3c3264869f..11557719cf 100644 --- a/target/riscv

[PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset.In addition,add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 15 +-- target/riscv/cpu.c | 4 target/riscv

[PATCH RFC 0/9] Add riscv64 kvm accel support

Hi, This series adds riscv64 kvm support, It is based on riscv_kvm_master branch at https://github.com/kvm-riscv/linux. This series depends on above pending changes which haven't yet been accepted, so this QEMU patch series is blocked until that dependency has been dealt with, but is worth review

[PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add riscv64 kvm support to configure. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- configure | 1 + target/riscv/Makefile.objs | 1 + target/riscv/kvm.c | 128 +++

[PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++- target/riscv/kvm.c | 19 +++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9

[PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 54 +- 1 file changed, 53 insertions(+), 1 deletion

[PATCH RFC 1/9] linux-header: Update linux/kvm.h

Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linux. Only use this header file, so do not update all linux headers. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8 1 file changed, 8 insertions(+) diff --git a/linux-heade

[PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 144 - 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..3e8f8e7185 100644 --- a/targ

[PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers by kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 136 - 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c in

Re: [PATCH] migration/throttle: Add throttle-trig-thres migration parameter

Hi Dr. David, On 2020/3/13 2:07, Dr. David Alan Gilbert wrote: > * Keqian Zhu (zhukeqi...@huawei.com) wrote: >> Currently, if the bytes_dirty_period is more than the 50% of >> bytes_xfer_period, we start or increase throttling. >> >> If we make this percentage higher, then we can tolerate higher >

[PATCH v3] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()

The current code causes clang static code analyzer generate warning: hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read value = value & 0x000f; ^ ~~ hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read value = v

RE: [PATCH v2] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()

>-Original Message- >From: Peter Maydell [mailto:peter.mayd...@linaro.org] >Sent: Friday, March 13, 2020 1:01 AM >To: Chenqun (kuhn) >Cc: QEMU Developers ; QEMU Trivial triv...@nongnu.org>; Zhanghailiang ; >Jason Wang ; Peter Chubb >; qemu-arm ; Euler >Robot >Subject: Re: [PATCH v2] hw/ne

Re: [kvm-unit-tests PATCH v6 10/13] arm/arm64: ITS: INT functional tests

On 2020/3/11 21:51, Eric Auger wrote: +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_prerequisites(4)) + return; + + dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */); +

Re: [kvm-unit-tests PATCH v5 10/13] arm/arm64: ITS: INT functional tests

Hi Eric, On 2020/3/12 17:59, Auger Eric wrote: Hi Zenghui, On 3/12/20 10:19 AM, Zenghui Yu wrote: On 2020/3/11 22:00, Marc Zyngier wrote: That is still a problem with the ITS. There is no architectural way to report an error, even if the error numbers are architected... One thing we could do

[PATCH v3 5/5] hw/arm/fsl-imx6: Wire up USB controllers

With this patch, the USB controllers on 'sabrelite' are detected and can be used to boot the system. Signed-off-by: Guenter Roeck --- v3: Wire up USB and USB PHY controllers separately. The number of USB controllers does not match the number of USB PHYs, and they are logically different.

[PATCH v3 4/5] hw/arm/fsl-imx6ul: Wire up USB controllers

IMX6UL USB controllers are quite similar to IMX7 USB controllers. Wire them up the same way. The only real difference is that wiring up phy devices is necessary to avoid phy reset timeouts in the Linux kernel. Signed-off-by: Guenter Roeck --- v3: Wire up USB and USB PHY controllers in separate l

[PATCH v3 3/5] hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices

Recent Linux kernels (post v4.20) crash due to accesses to flexcan and pwm controllers. Instantiate as unimplemented devices to work around the problem. Signed-off-by: Guenter Roeck --- v3: New patch hw/arm/fsl-imx6ul.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/hw/arm/

Re: [PATCH v7 0/4] linux-user: generate syscall_nr.sh for RISC-V

Patchew URL: https://patchew.org/QEMU/cover.1584051142.git.alistair.fran...@wdc.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v7 0/4] linux-user: generate syscall_nr.sh for RISC-V Message-id: cover.1584051142.git.alistai

[PATCH v3 1/5] hw/usb: Add basic i.MX USB Phy support

Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6, and i.MX7 SoCs. The only support really needed - at least to boot Linux - is support for soft reset, which needs to reset various registers to their initial value. Otherwise, just record register values. Reviewed-by: Peter Maydell

[PATCH v3 2/5] hw/arm/fsl-imx6ul: Fix USB interrupt numbers

USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number is 45. That didn't really matter up to now since the interrupts were not used, but it needs to be fixed to be able to wire up the USB controllers. Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC") Signed-off-by: Guenter Roeck -

[PATCH v3 0/5] Wire up USB controllers in i.MX6 emulations

This patch series wires up the USB controllers on fsl-imx6 and fsl-imx6ul emulations. The first patch provides a basic implementation of the USB PHY controller used in i.MX28 and later chips. Only reset bit handling in the control register is actually implemented. Basic USB PHY support is needed t

Re: [RFC] cpus: avoid get stuck in pause_all_vcpus

On 2020/3/12 23:28, Paolo Bonzini wrote: > On 10/03/20 10:14, Longpeng(Mike) wrote: >> From: Longpeng >> >> We find an issue when repeat reboot in guest during migration, it cause the >> migration thread never be waken up again. >> >> | >>

[PATCH 2/3] MAINTAINERS: Adjust maintainer's email

From: Aleksandar Markovic For some longish time I've been using multiple email addresses for mailing list communication, and would like to consolidate it into a single email address that is the most convenient to me. My other emails, from rt-rk.com and wavecomp.com domains remain active and I wil

[PATCH 3/3] MAINTAINERS: Add a file to the main MIPS section

From: Aleksandar Markovic A recently added acceptance test is important not only for Malta machine, but for overall MIPS target, since it tests smp feature. CC: Philippe Mathieu-Daudé Signed-off-by: Aleksandar Markovic --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTA

[PATCH 1/3] MAINTAINERS: Adjust maintainer's status for some MIPS items

From: Aleksandar Markovic Aurelien has been and will forever remain an idol in QEMU for MIPS world. However, since he decided to move on to other projects, acknowledge the reality, and formally releive him from maintainer's duties for QEMU for MIPS items. Aurelien is though welcome to come back a

[PATCH 0/3] MAINTAINERS: Adjust MIPS items

From: Aleksandar Markovic Some MIPS maintainership houskeeping changes, and some items for better reflecting the reality. Aleksandar Markovic (3): MAINTAINERS: Adjust maintainer's status for some MIPS items MAINTAINERS: Adjust maintainer's email MAINTAINERS: Add a file to the main MIPS sec

[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type

The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton --- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.

[PATCH 1/2] riscv: sifive_e: Support changing CPU type

Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv/

[PATCH 0/2] Support different CPU types for the sifive_e machine

The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension

[PATCH 1/2] riscv: sifive_e: Support changing CPU type

Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv/

[PATCH 0/2] Support different CPU types for the sifive_e machine

The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension

[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type

The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton --- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.

Re: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1

Patchew URL: https://patchew.org/QEMU/20200312145900.2054-1-zhiwei_...@c-sky.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1 Message-id: 20200312145900.2054-1-zhiwei_.

[PATCH] linux-user: Update TASK_UNMAPPED_BASE for aarch64

This change updates TASK_UNMAPPED_BASE (the base address for guest programs) for aarch64. It is needed to allow qemu to work with Thread Sanitizer (TSan), which has specific boundary definitions for memory mappings on different platforms: https://github.com/llvm/llvm-project/blob/master/compiler

Re: [PATCH v10 02/10] qemu-binfmt-conf.sh: enforce safe tests

Laurent, as Eric explained, this commit (as well as the homogeneisation of spacing) are fixes to pre-existing issues in the script, in order to better match other bash sources in the codebase. It would be possible to pick 1/10 and 2/10 as a separate patchset. El mar., 10 mar. 2020 a las 12:47, Eri

Re: [PATCH v3 12/16] hw/i386/vmport: Add support for CMD_GET_VCPU_INFO

On 13/03/2020 2:09, Michael S. Tsirkin wrote: On Thu, Mar 12, 2020 at 06:54:27PM +0200, Liran Alon wrote: Command currently returns that it is unimplemented by setting the reserved-bit in it's return value. Following patches will return various useful vCPU information to guest. Reviewed-by:

Re: [PATCH v10 04/10] qemu-binfmt-conf.sh: add QEMU_CREDENTIAL and QEMU_PERSISTENT

2020/03/10 9:20, Laurent Vivier: > If variable are set to 'yes', how do you force the value to no with the > command line? > I believe you cannot. Do you mean the explanation should be reworded? Or that the feature should be implemented? > Please, refresh my memory, why do we need these variabl

Re: [PATCH v3 12/16] hw/i386/vmport: Add support for CMD_GET_VCPU_INFO

On Thu, Mar 12, 2020 at 06:54:27PM +0200, Liran Alon wrote: > Command currently returns that it is unimplemented by setting > the reserved-bit in it's return value. > > Following patches will return various useful vCPU information > to guest. > > Reviewed-by: Nikita Leshenko > Signed-off-by: Lir

Re: [PATCH v3 11/16] hw/i386/vmport: Add support for CMD_GETTIMEFULL

On Thu, Mar 12, 2020 at 06:54:26PM +0200, Liran Alon wrote: > Similar to CMD_GETTIME but lacks the 136-year overflow issue, > by returning full 64-bit of host uSeconds. > > Reviewed-by: Nikita Leshenko > Signed-off-by: Liran Alon > --- > hw/i386/vmport.c | 17 + > includ

Re: [PATCH v3 10/16] hw/i386/vmport: Add support for CMD_GETTIME

On Thu, Mar 12, 2020 at 06:54:25PM +0200, Liran Alon wrote: > This command is used by guest to gettimeofday() from host. > See usage example in open-vm-tools TimeSyncReadHost() function. > > Reviewed-by: Nikita Leshenko > Signed-off-by: Liran Alon > --- > hw/i386/vmport.c | 21 +

Re: [PATCH] block/io: fix bdrv_co_do_copy_on_readv

On 3/12/20 4:19 AM, Vladimir Sementsov-Ogievskiy wrote: > Prior to 1143ec5ebf4 it was OK to qemu_iovec_from_buf() from aligned-up > buffer to original qiov, as qemu_iovec_from_buf() will stop at qiov end > anyway. > > But after 1143ec5ebf4 we assume that bdrv_co_do_copy_on_readv works on > part

Re: Questions about pollute the mail list archives

On 2020/3/11 11:46, Richard Henderson wrote: On 3/10/20 7:19 PM, LIU Zhiwei wrote: Is it serious? It isn't ideal. I would eventually try to review via your branch, and find a copy of the patch to reply, or send a reply to the cover letter if no copy of the patch arrived. Is there any way

Re: [PATCH v2 1/2] iotests: Refactor blockdev-reopen test for iothreads

On 3/6/20 9:14 AM, Kevin Wolf wrote: > We'll want to test more than one successful case in the future, so > prepare the test for that by a refactoring that runs each scenario in a > separate VM. > > test_iothreads_switch_{backing,overlay} currently produce errors, but > these are cases that sho

Re: [PATCH] linux-user: Add an argument QEMU_MMAP_BASE to set custom mmap base address in qemu user mode

On Thu, Mar 12, 2020 at 1:42 AM Laurent Vivier wrote: > Le 09/03/2020 à 19:07, Lirong Yuan a écrit : > > > > On Mon, Mar 2, 2020 at 11:51 AM Lirong Yuan > > wrote: > > > > On Mon, Mar 2, 2020 at 10:39 AM Laurent Vivier > > wrote: > >

[PATCH v7 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64

Add support for the clock_gettime64/clock_settime64 syscalls. If your host is 64-bit or is 32-bit with the *_time64 syscall then the timespec will correctly be a 64-bit time_t. Otherwise the host will return a 32-bit time_t which will be rounded to 64-bits. This will be incorrect after y2038. Sig

[PATCH v7 1/4] linux-user: Protect more syscalls

New y2038 safe 32-bit architectures (like RISC-V) don't support old syscalls with a 32-bit time_t. The kernel defines new *_time64 versions of these syscalls. Add some more #ifdefs to syscall.c in linux-user to allow us to compile without these old syscalls. Signed-off-by: Alistair Francis Review

[PATCH v7 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel

Signed-off-by: Alistair Francis Reviewed-by: Laurent Vivier --- linux-user/riscv/syscall32_nr.h | 295 +++ linux-user/riscv/syscall64_nr.h | 301 linux-user/riscv/syscall_nr.h | 294 +-- 3 files changed, 5

[PATCH v7 3/4] linux-user: Support futex_time64

Add support for host and target futex_time64. If futex_time64 exists on the host we try that first before falling back to the standard futux syscall. Signed-off-by: Alistair Francis --- linux-user/syscall.c | 144 +++ 1 file changed, 131 insertions(+), 13

[PATCH v7 0/4] linux-user: generate syscall_nr.sh for RISC-V

This series updates the RISC-V syscall_nr.sh based on the 5.5 kernel. There are two parts to this. One is just adding the new syscalls, the other part is updating the RV32 syscalls to match the fact that RV32 is a 64-bit time_t architectures (y2038) safe. We need to make some changes to syscall.c

Re: [PATCH] iotests/026: Move v3-exclusive test to new file

On 3/11/20 10:07 AM, Max Reitz wrote: > data_file does not work with v2, and we probably want 026 to keep > working for v2 images. Thus, open a new file for v3-exclusive error > path test cases. > > Fixes: 81311255f217859413c94f2cd9cebf2684bbda94 >(“iotests/026: Test EIO on allocation

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

On Wed, Mar 4, 2020 at 9:34 AM Richard Henderson wrote: > > On 3/3/20 5:16 PM, Alistair Francis wrote: > > The RISC-V spec specifies that when a write happens and the D bit is > > clear the implementation will set the bit in the PTE. It does not > > describe that the PTE being dirty means that we

Re: [PATCH 0/5] QEMU Gating CI

On Thu, Mar 12, 2020 at 10:00:42PM +, Peter Maydell wrote: > On Thu, 12 Mar 2020 at 19:36, Cleber Rosa wrote: > > > > The idea about a public facing Gating CI for QEMU was lastly > > summarized in an RFC[1]. Since then, it was decided that a > > simpler version should be attempted first. > >

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

On Thu, Mar 12, 2020 at 3:00 PM LIU Zhiwei wrote: > > > > On 2020/3/13 5:23, Alistair Francis wrote: > > On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: > >> vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags > >> should update after configure instructions. The (ill, lmul

Re: [PATCH 0/5] QEMU Gating CI

On Thu, 12 Mar 2020 at 19:36, Cleber Rosa wrote: > > The idea about a public facing Gating CI for QEMU was lastly > summarized in an RFC[1]. Since then, it was decided that a > simpler version should be attempted first. OK, so my question here is: * what are the instructions that I have to foll

Re: [PATCH v4 0/7] Tighten qemu-img rules on missing backing format

On 3/12/20 4:39 PM, no-re...@patchew.org wrote: Patchew URL: https://patchew.org/QEMU/20200312192822.3739399-1-ebl...@redhat.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it l

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

On 2020/3/13 5:23, Alistair Francis wrote: On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will b

Re: [PATCH v4 0/7] Tighten qemu-img rules on missing backing format

Patchew URL: https://patchew.org/QEMU/20200312192822.3739399-1-ebl...@redhat.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH v4 0/7] Tighten qemu-img rules on missing backing format

Patchew URL: https://patchew.org/QEMU/20200312192822.3739399-1-ebl...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ==

Re: [PATCH v4 0/7] Tighten qemu-img rules on missing backing format

Patchew URL: https://patchew.org/QEMU/20200312192822.3739399-1-ebl...@redhat.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash exp

[PATCH] hw/isa/superio: Correct the license text

The license is the 'GNU General Public License v2.0 or later', not 'and': This program is free software; you can redistribute it and/ori modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your op

[PATCH] hw/arm/bcm283x: Correct the license text

The license is the 'GNU General Public License v2.0 or later', not 'and': This program is free software; you can redistribute it and/ori modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your op

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: > > vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags > should update after configure instructions. The (ill, lmul, sew ) of vtype > and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. > > Signed-off-

Re: QMP netdev_add multiple dnssearch values

On 11/27/19 9:49 AM, Eric Blake wrote: On 11/27/19 7:30 AM, Markus Armbruster wrote: "Good enough" was true back then.  It wasn't true when we reused it for netdev_add: hostfwd and guestfwd are list-valued. We did define a QAPI schema a few months later (14aa0c2de0 "qapi schema: add Netdev typ

Re: [PATCH] acpi: Add Windows ACPI Emulated Device Table (WAET)

On 12/03/2020 21:47, Michael S. Tsirkin wrote: On Thu, Mar 12, 2020 at 07:28:31PM +0200, Liran Alon wrote: On 12/03/2020 18:27, Igor Mammedov wrote: On Wed, 11 Mar 2020 19:08:26 +0200 Liran Alon wrote: we typically do not version ACPI table changes (there might be exceptions but it should b

[PATCH] net: Complete qapi-fication of netdev_add

We've had all the required pieces for doing a type-safe representation of netdev_add as a flat union for quite some time now (since 0e55c381f6 in v2.7.0, released in 2016), but did not make the final switch to using it because of concern about whether a command-line regression in accepting "1" in p

Re: [PATCH v5 03/60] target/riscv: support vector extension csr

On Thu, Mar 12, 2020 at 8:05 AM LIU Zhiwei wrote: > > The v0.7.1 specification does not define vector status within mstatus. > A future revision will define the privileged portion of the vector status. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/

Re: [PATCH v4 00/10] Further bitmaps improvements

On 3/12/20 1:59 AM, Vladimir Sementsov-Ogievskiy wrote: > 11.03.2020 20:03, John Snow wrote: >> >> >> On 3/11/20 9:58 AM, Vladimir Sementsov-Ogievskiy wrote: >>> 11.03.2020 12:55, Max Reitz wrote: On 11.03.20 07:17, Vladimir Sementsov-Ogievskiy wrote: > 10.03.2020 20:17, Max Reitz wrote

Re: [PULL 00/36] target-arm queue

lowing changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565: > > Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' > into staging (2020-03-12 15:20:52 +) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm

Re: [PATCH v2] linux-user: fix socket() strace

On 3/12/20 5:55 PM, Laurent Vivier wrote: print_socket_type() doesn't manage flags and the correct type cannot be displayed Signed-off-by: Laurent Vivier --- Notes: v2: replace gemu_log() by qemu_log() as it has been removed from qemu linux-user/strace.c | 8 +++- 1 file changed,

[PATCH] hw/net/i82596.c: Avoid reading off end of buffer in i82596_receive()

The i82596_receive() function attempts to pass the guest a buffer which is effectively the concatenation of the data it is passed and a 4 byte CRC value. However, rather than implementing this as "write the data; then write the CRC" it instead bumps the length value of the data by 4, and writes 4

[PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled

Signed-off-by: Richard Henderson --- v5: Assign cs->num_ases to the final value first. Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available. v6: Add secure tag memory for EL3. --- target/arm/cpu.h | 6 ++ hw/arm/virt.c| 52 +++ tar

[PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads

Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 98 target/arm/sve_helper.c| 98 ++-- target/arm/translate-s

[PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores

Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 47 +++ target/arm/sve_helper.c| 95 -- target/arm/translate-

Re: [PATCH v8 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine

On Thu, Mar 12, 2020 at 5:22 PM Peter Maydell wrote: > On Wed, 11 Mar 2020 at 22:19, Niek Linnenbank > wrote: > > > > Dear QEMU developers, > > > > Hereby I would like to contribute the following set of patches to QEMU > > which add support for the Allwinner H3 System on Chip and the > > Orange

[PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 1 + target/arm/sve_helper.c| 63 ++- target/arm/translate-sve.c | 88 ++ 3 files changed, 94 insertions(+), 58 deletions(-) diff --git a/target/arm/helper-sve.h b/t

[PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 + target/arm/sve_helper.c| 74 -- target/arm/translate-sve.c | 93 -- 3 files changed, 110 insertions(+), 59 deletions(-) diff --git a/target/arm/helper-sve.h

Re: [PATCH] acpi: Add Windows ACPI Emulated Device Table (WAET)

On Thu, Mar 12, 2020 at 07:28:31PM +0200, Liran Alon wrote: > > On 12/03/2020 18:27, Igor Mammedov wrote: > > On Wed, 11 Mar 2020 19:08:26 +0200 > > Liran Alon wrote: > > > + > > > +static void > > > +build_waet(GArray *table_data, BIOSLinker *linker) > > see build_hmat_lb() for example how to do

Re: [PATCH V2 7/8] COLO: Migrate dirty pages during the gap of checkpointing

* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote: > We can migrate some dirty pages during the gap of checkpointing, > by this way, we can reduce the amount of ram migrated during checkpointing. > > Signed-off-by: zhanghailiang > --- > migration/colo.c | 73 ++

[PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE

There are a number of paths by which the TBI is still intact for user-only in the SVE helpers. Because we currently always set TBI for user-only, we do not need to pass down the actual TBI setting from above, and we can remove the top byte in the inner-most primitives, so that none are forgotten.

[PATCH v6 25/42] target/arm: Implement helper_mte_check1

Fill out the stub that was added earlier. Signed-off-by: Richard Henderson --- target/arm/internals.h | 47 +++ target/arm/mte_helper.c | 126 +++- 2 files changed, 172 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/ar

[PATCH v6 42/42] target/arm: Add allocation tag storage for system mode

Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 128 1 file changed, 128 insertions(+) d

[PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 49d2e68564..e5d12edd55 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/tra

[PATCH v6 22/42] target/arm: Move regime_tcr to internals.h

We will shortly need this in mte_helper.c as well. Signed-off-by: Richard Henderson --- target/arm/internals.h | 9 + target/arm/helper.c| 9 - 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f091891312..56f

[PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry

D1.10 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c

Re: [PATCH V2 8/8] migration/colo: Only flush ram cache while do checkpoint

* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote: > After add migrating ram backgroud, we will call ram_load > for this process, but we should not flush ram cache during > this process. Move the flush action to the right place. > > Signed-off-by: zhanghailiang Reviewed-by: Dr. David Alan G

[PATCH v6 27/42] target/arm: Add helper_mte_check_zva

Use a special helper for DC_ZVA, rather than the more general mte_checkN. Leave the helper blank for now. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h| 1 + target/arm/mte_helper.c| 106 + target/arm/translate-a64.c | 16 +- 3 f

[PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads

Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 58 ++ target/arm/internals.h | 6 + target/arm/sve_helper.c| 218 ++

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