Currently, host cpu is inherited simply.
Signed-off-by: Yifei Jiang <jiangyi...@huawei.com>
Signed-off-by: Yipeng Yin <yinyipe...@huawei.com>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3c3264869f..11557719cf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
set_feature(env, RISCV_FEATURE_PMP);
}
+static void riscv_host_cpu_init(Object *obj)
+{
+}
+
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -622,6 +626,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
/* Deprecated */
DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2724eca714..10b053a467 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,6 +39,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
/* Deprecated */
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
--
2.19.1
