Re: [Qemu-devel] Fwd: [j...@sing.id.au: atomic failures on qemu-system-riscv64]

On Thu, 06 Jun 2019 19:50:57 PDT (-0700), richard.hender...@linaro.org wrote: Also, unless I'm misunderstanding something our implementation of LR/SC is pretty broken. We're just using a CAS to check if the value changed, which suffers from the ABA problem that LR/SC is there to fix in the f

Re: [Qemu-devel] [PATCH] target/mips: Add implementation of DSPRAM

On Jun 6, 2019 3:49 PM, "Mateja Marjanovic" wrote: > > From: Mateja Marjanovic > > Add support for DSPRAM (Data Scratch Pad RAM). It still needs > some minor fixing, but the structure is right. > > Signed-off-by: Mateja Marjanovic > --- Please consider splitting the patch into several logical u

[Qemu-devel] [Qemu-trivial] [PATCH v2] test: Use g_strndup instead of plain strndup

Due to memory management rules. See HACKING. Signed-off-by: Tony Nguyen diff --git a/tests/check-qjson.c b/tests/check-qjson.c index fa2afcc..07a773e 100644 --- a/tests/check-qjson.c +++ b/tests/check-qjson.c @@ -767,7 +767,7 @@ static void utf8_string(void) if (*end ==

Re: [Qemu-devel] [PATCH v18 00/29] Add RX archtecture support

Patchew URL: https://patchew.org/QEMU/20190607153725.18055-1-phi...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v18 00/29] Add RX archtecture support Message-id: 20190607153725.18055-1-ph

Re: [Qemu-devel] RISC-V: Include ROM in QEMU

On Thu, 06 Jun 2019 16:22:47 PDT (-0700), alistai...@gmail.com wrote: Hello, As a test of the waters, how would the QEMU community feel about including the RISC-V OpenSBI project as a ROM submodule? The idea would be to have OpenSBI (similar to ATF for ARM and a BIOS for x86) included by defaul

Re: [Qemu-devel] [PATCH 3/4] qapi: implement block-dirty-bitmap-remove transaction action

On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote: > It is used to do transactional movement of the bitmap (which is > possible in conjunction with merge command). Transactional bitmap > movement is needed in scenarios with external snapshot, when we don't > want to leave copy of the bitmap

Re: [Qemu-devel] [PATCH] RFC: qio: Improve corking of TLS sessions

On 6/7/19 5:14 PM, Eric Blake wrote: > Our current implementation of qio_channel_set_cork() is pointless for > TLS sessions: we block the underlying channel, but still hand things > piecemeal to gnutls which then produces multiple encryption packets. > Better is to directly use gnutls corking, whic

Re: [Qemu-devel] [PATCH 2/4] block/dirty-bitmap: add hide/unhide API

On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote: > Add functionality to make bitmap temporary anonymous. It will be used > to implement bitmap remove transaction action. We need hide bitmap > persistence too, as there are should not be unnamed persistent bitmaps. > Ah, so this effectivel

[Qemu-devel] [PATCH] RFC: qio: Improve corking of TLS sessions

Our current implementation of qio_channel_set_cork() is pointless for TLS sessions: we block the underlying channel, but still hand things piecemeal to gnutls which then produces multiple encryption packets. Better is to directly use gnutls corking, which collects multiple inputs into a single encr

Re: [Qemu-devel] [PATCH 2/5] block/dirty-bitmap: Refactor bdrv_can_store_new_bitmap

On 6/7/19 2:17 PM, Vladimir Sementsov-Ogievskiy wrote: > 07.06.2019 21:10, John Snow wrote: >> >> >> On 6/7/19 10:29 AM, Vladimir Sementsov-Ogievskiy wrote: >>> 06.06.2019 21:41, John Snow wrote: Instead of bdrv_can_store_new_bitmap, rework this as bdrv_add_persistent_dirty_bitmap. Thi

Re: [Qemu-devel] [PATCH 1/4] blockdev: reduce aio_context locked sections in bitmap add/remove

On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote: > Commit 0a6c86d024c52 returned these locks back to add/remove > functionality, to protect from intersection of persistent bitmap > related IO with other IO. But other bitmap-related functions called > here are unrelated to the problem, and

[Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 87 +++ 1 file changed, 78 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6ff4272da2..ece3eadf66 100644 --- a/target/riscv/cpu_helper.c +++

[Qemu-devel] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode

The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive checkpatch errors which are being ignored. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 118 -- 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_h

Re: [Qemu-devel] [PATCH 0/4] qapi: block-dirty-bitmap-remove transaction action

On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote: > Hi all! > > Here is block-dirty-bitmap-remove transaction action. > > It is used to do transactional movement of the bitmap (which is > possible in conjunction with merge command). Transactional bitmap > movement is needed in scenarios w

[Qemu-devel] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status

When the Hypervisor extension is in use we only enable floating point support when both status and bsstatus have enabled floating point support. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target

[Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty

Mark both sstatus and bsstatus as dirty (3). Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 313c27b700..1c3cd1c94b 100644 --- a/target/riscv/translate.c +++ b

[Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops

Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing floating point operations when V=0. Signed-off-by: Alistair Francis --- target/riscv/translate.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/tran

[Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1

Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb35f..e08bb8dd5a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -130,9 +13

[Qemu-devel] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension

Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6111f0f0bc..38583e7a6e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -436,6 +436,9 @@ static void r

[Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions

Signed-off-by: Alistair Francis --- target/riscv/insn32.decode| 23 ++- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes

To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 + 1 file changed, 5 inser

[Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6cef78a2c7..6ff4272da2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -28

[Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS

When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/si

[Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu_bits.h | 5 target/riscv/cpu_helper.c | 52 +++ 3 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eed561d56e..5b3b32dbbc 1

[Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 4 +-- target/riscv/cpu_helper.c | 71 +-- target/riscv/csr.c| 4 +-- 3 files changed, 65 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h in

[Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 target/riscv/csr.c | 119 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c898bb1102..9c27727e6f 100644 --- a/target/riscv

[Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled

Let's creaate a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistai

[Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions

Signed-off-by: Alistair Francis --- target/riscv/csr.c | 68 ++ 1 file changed, 68 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b1308d47c..911f83ef51 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -82,6 +82,20

[Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions

Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 include/hw/riscv/sifive_plic.h | 3 --- 2 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 07a032d93d..1e7e4c8d51 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/r

[Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f51139b543..0116d2499c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_h

[Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_helper.c | 23 +++ 3 files changed, 31 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4843b879..eeb3756c91 100644 --- a/t

[Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support

Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 66 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e08bb8dd5a..60dcd73fc7 100644 --- a/target/riscv/op_helper.c +++ b/

[Qemu-devel] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 35 +++ 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b009049cc4..6cef78a2c7 100644 --- a/target/riscv/cpu_helper.c +++ b/ta

[Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eeb3756c91..b99d2b7af2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,12 +169,29 @@ struct CPURISCVState {

[Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W

The privledge check based on the CSR address mask 0x300 doesn't work when using Hypervisor extensions so remove the check Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9e

[Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled

Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d1378bb7f..6111f0f0bc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -220,14 +220,41 @@ static void r

[Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 4 target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_helper.c | 23 +++ 3 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3337d1aef3..de4843b879 100644 --- a

[Qemu-devel] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs

Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be becuase it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis --- target/riscv/cpu_

[Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension

This patch series adds the RISC-V Hypervisor extension 0.3. This is the latest draft spec of the Hypervisor extension. The Hypervisor extension is disabled by default, so this series should result in no changes to anyone using QEMU unless they enable the extension. The extention can be enabled wit

[Qemu-devel] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8937bda918..3337d1aef3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVC RV('C') #define RVS RV('S') #de

Re: [Qemu-devel] [Qemu-devel PATCH v2 2/2] util/main-loop: Fix incorrect assertion

Hi Philippe, On 6/6/2019 4:18 PM, Philippe Mathieu-Daudé wrote: On 6/5/19 9:15 PM, Lidong Chen wrote: The check for poll_fds in g_assert() was incorrect. The correct assertion should check "n_poll_fds + w->num <= ARRAY_SIZE(poll_fds)" because the subsequent for-loop is doing access to poll_fds[

Re: [Qemu-devel] [PATCH v3 00/10] Refactor cpu topo into machine properties

On Sun, May 19, 2019 at 04:54:18AM +0800, Like Xu wrote: > This patch series make existing cores/threads/sockets into machine > properties and get rid of global smp_* variables they use currently. > > The purpose of getting rid of globals is disentangle layer violations and > let's do it one step

[Qemu-devel] [PULL 6/8] BootLinuxConsoleTest: Test nanoMIPS kernels on the I7200 CPU

From: Philippe Mathieu-Daudé Similar to the x86_64/pc test, it boots a Linux kernel on a Malta machine and verify the serial is working. Use the documentation added in commit f7d257cb4a17 to test nanoMIPS kernels and the I7200 CPU. This test can be run using: $ avocado --show=console run -t

[Qemu-devel] [PULL 8/8] travis: Make check-acceptance job more verbose

It will help us debug issues when tests fail. Signed-off-by: Eduardo Habkost --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 75e017a5cf..82c74673e1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -225,7 +225,7 @@ matrix: # Ac

[Qemu-devel] [PULL 7/8] BootLinuxConsoleTest: Run kerneltests BusyBox on Malta

From: Philippe Mathieu-Daudé This tests boots a Linux kernel on a Malta machine up to a busybox shell on the serial console. Few commands are executed before halting the machine (via reboot). We use the initrd cpio image from the kerneltests project: https://kerneltests.org/ If MIPS is a target

[Qemu-devel] [PULL 5/8] BootLinuxConsoleTest: Test the SmartFusion2 board

From: Philippe Mathieu-Daudé Similar to the x86_64/pc test, it boots a Linux kernel on an Emcraft board and verify the serial is working. If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can

[Qemu-devel] [PULL 4/8] BootLinuxConsoleTest: Do not log empty lines

From: Philippe Mathieu-Daudé Avoid to log empty lines in console debug logs. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20190520220635.10961-2-f4...@amsat.org> Reviewed-by: Alistair Francis Reviewed-by: Cleber Rosa Tested-by: Cleber Rosa Acked-by: Aleksandar Markovic Signed-off-by:

[Qemu-devel] [PULL 2/8] Deprecate Python 2 support

Python 2 will reach end of life in January 1 2020. Declare it as deprecated. Signed-off-by: Eduardo Habkost Message-Id: <20190503193721.18459-1-ehabk...@redhat.com> Reviewed-by: Thomas Huth Reviewed-by: Markus Armbruster Reviewed-by: Daniel P. Berrangé [ehabkost: print "warning:" in lowercase

[Qemu-devel] [PULL 1/8] tests/boot_linux_console: Let extract_from_deb handle various compressions

From: Philippe Mathieu-Daudé Debian binary package format supports various compressions. Per man deb(5): NAME deb - Debian binary package format FORMAT ... The third, last required member is named data.tar. It contains the filesystem as a tar archive, either not compressed

[Qemu-devel] [PULL 3/8] configure: Require python3 >= 3.5

The oldest python3 version in distros that will be supported by QEMU 4.1 is 3.5.3 (the one in Debian Stretch). Error out if running python3 < 3.5. We have a .travis.yml job configured to use Python 3.4. Change it to use Python 3.5. Signed-off-by: Eduardo Habkost Message-Id: <20190508182339.224

[Qemu-devel] [PULL 0/8] Python queue, 2019-06-07

The following changes since commit 185b7ccc11354cbd69b6d53bf8d831dd964f6c88: Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190607-2' into staging (2019-06-07 15:24:13 +0100) are available in the Git repository at: git://github.com/ehabkost/qemu.git tags/python-next-pu

Re: [Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit register macros

On Fri, Jun 7, 2019 at 9:57 AM Philippe Mathieu-Daudé wrote: > > Some RX peripheral using 8bit and 16bit registers. > Added 8bit and 16bit APIs. > > Signed-off-by: Yoshinori Sato > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > Message-Id: <20190607091116.49044-11-ys...@

[Qemu-devel] Fix cacheline size retrieval on FreeBSD/PowerPC(64)

The attached very trivial patch fixes a startup bug that prevents at least Qemu 3.1 and later from working on FreeBSD/powerpc64. - Justin >From 74a70fdcfa5347e7637aa36276c55781f19de72a Mon Sep 17 00:00:00 2001 From: Justin Hibbits Date: Fri, 7 Jun 2019 13:44:51 -0500 Subject: [PATCH] Fix cachelin

Re: [Qemu-devel] [RFC PATCH 00/10] monitor: Split monitor.c in core/HMP/QMP/misc

Patchew URL: https://patchew.org/QEMU/20190607135430.22149-1-kw...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [RFC PATCH 00/10] monitor: Split monitor.c in core/HMP/QMP/misc Message-id: 201906

Re: [Qemu-devel] [Qemu-block] [PATCH v2 1/5] block/nvme: don't flip CQ phase bits

On 6/7/19 7:08 AM, Paolo Bonzini wrote: > On 06/06/19 23:23, John Snow wrote: >> So: This looks right; does this fix a bug that can be observed? Do we >> have any regression tests for block/NVMe? > > I don't think it fixes a bug; by the time the CQ entry is picked up by > QEMU, the device is no

Re: [Qemu-devel] [PATCH 5/5] block/qcow2-bitmap: Count queued bitmaps towards directory_size

On 6/6/19 10:30 PM, Eric Blake wrote: > On 6/6/19 1:41 PM, John Snow wrote: >> Similarly to the previous commit, we need to also keep a ledger of the >> additional directory size burden that we've not yet committed so we can >> reject new additions sooner instead of later. >> >> Signed-off-by: J

Re: [Qemu-devel] [PATCH 15/18] Boot Linux Console Test: add a test for aarch64 + virt

CCing Daniel, who wrote commit 6ab3fc32ea64. On Fri, Jun 07, 2019 at 11:44:32AM -0400, Cleber Rosa wrote: > On Fri, Jun 07, 2019 at 12:42:14AM -0300, Eduardo Habkost wrote: > > On Fri, Jun 07, 2019 at 12:26:48AM -0300, Eduardo Habkost wrote: > > > On Fri, Feb 01, 2019 at 11:10:31AM -0500, Cleber R

Re: [Qemu-devel] [PATCH 1/2] migration/xbzrle: update cache and current_data in one place

* Wei Yang (richardw.y...@linux.intel.com) wrote: > When we are not in the last_stage, we need to update the cache if page > is not the same. > > Currently this procedure is scattered in two places and mixed with > encoding status check. > > This patch extract this general step out to make the co

[Qemu-devel] [PATCH] tests/vm: favour the locally built QEMU for bootstrapping

It turns out that relying on the system installed QEMU can result in problems especially if it has been patched. Seeing as this is a developer tool and we should be dogfooding we favour the locally built binary if it exists. The developer always has the option of overriding their locally broken bui

Re: [Qemu-devel] [PATCH] qcow2-bitmaps: fix qcow2_can_store_new_dirty_bitmap

07.06.2019 21:48, Vladimir Sementsov-Ogievskiy wrote: > qcow2_can_store_new_dirty_bitmap works wrong, as it considers only > bitmaps already stored in the qcow2 image and ignores persistent > BdrvDirtyBitmap objects. > > So, let's instead count persistent BdrvDirtyBitmaps. We load all qcow2 > bitm

[Qemu-devel] [PATCH] qcow2-bitmaps: fix qcow2_can_store_new_dirty_bitmap

qcow2_can_store_new_dirty_bitmap works wrong, as it considers only bitmaps already stored in the qcow2 image and ignores persistent BdrvDirtyBitmap objects. So, let's instead count persistent BdrvDirtyBitmaps. We load all qcow2 bitmaps on open, so there should not be any bitmap in the image for wh

[Qemu-devel] [PULL 2/2] accel: Remove unused AccelClass::opt_name attribute

From: Wainer dos Santos Moschetta The AccelType type was converted to AccelClass QOM object on b14a0b7469f, and the original data type had a field to store the option name which in turn was used to search an accelerator. The lookup method (accel_find) changed too, making the option field unnecess

[Qemu-devel] [PULL 0/2] Machine Core queue, 2019-06-07

The following changes since commit 185b7ccc11354cbd69b6d53bf8d831dd964f6c88: Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190607-2' into staging (2019-06-07 15:24:13 +0100) are available in the Git repository at: git://github.com/ehabkost/qemu.git tags/machine

Re: [Qemu-devel] [PATCH 2/5] block/dirty-bitmap: Refactor bdrv_can_store_new_bitmap

07.06.2019 21:10, John Snow wrote: > > > On 6/7/19 10:29 AM, Vladimir Sementsov-Ogievskiy wrote: >> 06.06.2019 21:41, John Snow wrote: >>> Instead of bdrv_can_store_new_bitmap, rework this as >>> bdrv_add_persistent_dirty_bitmap. This makes a more obvious symmetry >>> with bdrv_remove_persistent_

Re: [Qemu-devel] [PATCH 3/5] block/dirty-bitmap: rework bdrv_remove_persistent_dirty_bitmap

On 6/7/19 10:41 AM, Vladimir Sementsov-Ogievskiy wrote: > 06.06.2019 21:41, John Snow wrote: >> Allow propagating error code information from >> bdrv_remove_persistent_dirty_bitmap as well. >> >> Give it an interface that matches the newly revised >> bdrv_add_persistent_dirty_bitmap, including r

Re: [Qemu-devel] [PATCH 2/5] block/dirty-bitmap: Refactor bdrv_can_store_new_bitmap

On 6/7/19 1:10 PM, John Snow wrote: > > > On 6/7/19 10:29 AM, Vladimir Sementsov-Ogievskiy wrote: >> 06.06.2019 21:41, John Snow wrote: >>> Instead of bdrv_can_store_new_bitmap, rework this as >>> bdrv_add_persistent_dirty_bitmap. This makes a more obvious symmetry >>> with bdrv_remove_persistent

Re: [Qemu-devel] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree

On 6/6/19 12:45 PM, Peter Maydell wrote: > Convert the "single-precision" register moves to decodetree: > * VMSR > * VMRS > * VMOV between general purpose register and single precision > > Note that the VMSR/VMRS conversions make our handling of > the "should this UNDEF?" checks consistent betw

Re: [Qemu-devel] [PATCH 4/5] block/qcow2-bitmap: Count queued bitmaps towards nb_bitmaps

On 6/6/19 10:27 PM, Eric Blake wrote: > On 6/6/19 1:41 PM, John Snow wrote: >> When we check to see if we can store a bitmap, we don't check how many >> we've queued up. This can cause a problem saving bitmaps on close >> instead of when we request them to be added. With the stricter add >> inte

Re: [Qemu-devel] [PATCH v18 15/29] target/rx: Add RX to SysEmuTarget

On 6/7/19 10:37 AM, Philippe Mathieu-Daudé wrote: > From: Richard Henderson > > Fixes check-qtest-rx: tests/qmp-cmd-test Is that in master? If so, what commit id; if not, why not just squash this into that patch before merging it? -- Eric Blake, Principal Software Engineer Red Hat, Inc.

Re: [Qemu-devel] [PATCH v6 0/7] Add "boot_linux" acceptance test

Patchew URL: https://patchew.org/QEMU/20190606211414.8681-1-cr...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v6 0/7] Add "boot_linux" acceptance test Type: series Message-id: 20190606211414.8681-1-cr

[Qemu-devel] [PATCH] BootLinuxSshTest: Only use 'test' for unittest.TestCase method names

In commit f6e501a28ef9, Eduardo started to use "check_" as a prefix for methods of similar purpose. Follow this prior art, since it might become the conventions when writting Avocado tests. Suggested-by: Cleber Rosa Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/linux_ssh_mips_malta

[Qemu-devel] [PULL 1/2] numa: improve cpu hotplug error message with a wrong node-id

From: Laurent Vivier On pseries, core-ids are strongly binded to a node-id by the command line option. If an user tries to add a CPU to the wrong node, he has an error but it is not really helpful: qemu-system-ppc64 ... -smp 1,maxcpus=64,cores=1,threads=1,sockets=1 \ -n

Re: [Qemu-devel] [PATCH v4 1/3] machine: show if CLI option '-numa node, mem' is supported in QAPI schema

Igor Mammedov writes: > Legacy '-numa node,mem' option has a number of issues and mgmt often > defaults to it. Unfortunately it's no possible to replace it with > an alternative '-numa memdev' without breaking migration compatibility. > What's possible though is to deprecate it, keeping option wo

Re: [Qemu-devel] [PATCH 2/5] block/dirty-bitmap: Refactor bdrv_can_store_new_bitmap

07.06.2019 21:17, Vladimir Sementsov-Ogievskiy wrote: > 07.06.2019 21:10, John Snow wrote: >> >> >> On 6/7/19 10:29 AM, Vladimir Sementsov-Ogievskiy wrote: >>> 06.06.2019 21:41, John Snow wrote: Instead of bdrv_can_store_new_bitmap, rework this as bdrv_add_persistent_dirty_bitmap. This ma

[Qemu-devel] [PATCH] tcg: Fix typos in helper_gvec_sar{8,32,64}v

The loop is written with scalars, not vectors. Use the correct type when incrementing. Fixes: 5ee5c14cacd Reported-by: Laurent Vivier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime-gvec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/tcg-runtime

Re: [Qemu-devel] [PATCH 2/2] qemu-tech.texi: Remove "QEMU compared to other emulators" section

On Fri, Jun 07, 2019 at 04:28:27PM +0100, Peter Maydell wrote: > The "QEMU compared to other emulators" section of our documentation > hasn't been updated since 2015 (and parts of the text are even older). > We're clearly not very well placed to track the evolution of a > dozen other emulation proj

Re: [Qemu-devel] [PATCH 4/5] block/qcow2-bitmap: Count queued bitmaps towards nb_bitmaps

On 6/7/19 10:58 AM, Vladimir Sementsov-Ogievskiy wrote: > 06.06.2019 21:41, John Snow wrote: >> When we check to see if we can store a bitmap, we don't check how many >> we've queued up. This can cause a problem saving bitmaps on close >> instead of when we request them to be added. With the str

Re: [Qemu-devel] [PATCH 2/5] block/dirty-bitmap: Refactor bdrv_can_store_new_bitmap

On 6/7/19 10:29 AM, Vladimir Sementsov-Ogievskiy wrote: > 06.06.2019 21:41, John Snow wrote: >> Instead of bdrv_can_store_new_bitmap, rework this as >> bdrv_add_persistent_dirty_bitmap. This makes a more obvious symmetry >> with bdrv_remove_persistent_dirty_bitmap. Most importantly, we are free

Re: [Qemu-devel] [RFC PATCH 10/10] monitor: Split out monitor/core.c

Oh, can you also fix up the paths in writing-qmp-commands.txt? Thanks for this split! Dave -- Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK

Re: [Qemu-devel] [PATCH v18 15/29] target/rx: Add RX to SysEmuTarget

On 6/7/19 8:04 PM, Eric Blake wrote: > On 6/7/19 10:37 AM, Philippe Mathieu-Daudé wrote: >> From: Richard Henderson >> >> Fixes check-qtest-rx: tests/qmp-cmd-test > > Is that in master? If so, what commit id; if not, why not just squash > this into that patch before merging it? Right, we should

Re: [Qemu-devel] [PATCH 12/42] target/arm: Convert "double-precision" register moves to decodetree

On 6/6/19 12:45 PM, Peter Maydell wrote: > Convert the "double-precision" register moves to decodetree: > this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. > > Note that the conversion process has tightened up a few of the > UNDEF encoding checks: we now correctly forbid: > * VMOV-

Re: [Qemu-devel] [PATCH 0/2] qemu-tech: move part to docs/devel, delete part

On 6/7/19 10:28 AM, Peter Maydell wrote: > Peter Maydell (2): > Convert "translator internals" docs to RST, move to devel manual > qemu-tech.texi: Remove "QEMU compared to other emulators" section Acked-by: Richard Henderson r~

Re: [Qemu-devel] [PATCH v18 04/29] !fixup target/rx: CPU definition

On 6/7/19 10:37 AM, Philippe Mathieu-Daudé wrote: > Rename macros. Why is this marked '!fixup' in the subject instead of just merging the patches directly? > > Signed-off-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > target/rx/cpu.c | 22 ++ > targe

Re: [Qemu-devel] [PATCH 11/42] target/arm: Add helpers for VFP register loads and stores

On 6/6/19 12:45 PM, Peter Maydell wrote: > The current VFP code has two different idioms for > loading and storing from the VFP register file: > 1 using the gen_mov_F0_vreg() and similar functions, >which load and store to a fixed set of TCG globals >cpu_F0s, CPU_F0d, etc > 2 by direct ca

Re: [Qemu-devel] [PATCH 7/8] VNC Acceptance test: check protocol version

On Fri, Jun 07, 2019 at 06:29:15PM +0100, Daniel P. Berrangé wrote: > On Fri, Jun 07, 2019 at 11:22:22AM -0400, Cleber Rosa wrote: > > This goes a bit further than the other tests, and does a basic (read > > only) interaction with the VNC protocol. > > > > This is not a enough to perform a handsha

Re: [Qemu-devel] [PATCH v4 1/3] machine: show if CLI option '-numa node, mem' is supported in QAPI schema

On Fri, Jun 07, 2019 at 07:39:17PM +0200, Markus Armbruster wrote: > This is correct when the TYPE_VIRT_MACHINE, TYPE_PC_MACHINE and > TYPE_SPAPR_MACHINE are exactly the machines supporting NUMA. How could > I check that? parse_numa_node() rejects the -numa option if the machine doesn't implement

Re: [Qemu-devel] [Qemu-block] [RFC PATCH 00/10] monitor: Split monitor.c in core/HMP/QMP/misc

On 6/7/19 10:35 AM, Dr. David Alan Gilbert wrote: >>> But if people prefer, I can move the existing files in the root >>> directory to monitor/{qmp,hmp}-cmds.c temporarily in this series and >>> then work from there with follow-ups until they are empty (or maybe I >>> don't even have to make them

[Qemu-devel] [PULL 0/1] Usb 20190607 patches

The following changes since commit 442bac16a6cd708a9f87adb0a263f9d833f03ed5: usb-tablet: fix serial compat property (2019-05-29 07:10:02 +0200) are available in the Git repository at: git://git.kraxel.org/qemu tags/usb-20190607-pull-request for you to fetch changes up to

Re: [Qemu-devel] [PATCH 3/4] net/virtio: add failover support

* Jens Freimann (jfreim...@redhat.com) wrote: > On Tue, Jun 04, 2019 at 08:00:19PM +0100, Dr. David Alan Gilbert wrote: > > * Michael S. Tsirkin (m...@redhat.com) wrote: > > > On Tue, Jun 04, 2019 at 03:43:21PM +0200, Jens Freimann wrote: > > > > On Mon, Jun 03, 2019 at 04:36:48PM -0300, Eduardo Ha

Re: [Qemu-devel] [PATCH 2/2] migration/xbzrle: cleanup the handling cache miss condition

* Wei Yang (richardw.y...@linux.intel.com) wrote: > For cache miss condition not in last_stage, we need to insert data into > cache. When this step succeed, current_data should be updated. While no > matter these checks pass or not, -1 is returned. > > Based on this, the logic in cache miss handli

Re: [Qemu-devel] [PATCH v18 04/29] !fixup target/rx: CPU definition

On 6/7/19 8:02 PM, Eric Blake wrote: > On 6/7/19 10:37 AM, Philippe Mathieu-Daudé wrote: >> Rename macros. > > Why is this marked '!fixup' in the subject instead of just merging the > patches directly? Since all the series is reviewed/tested and Igor asked to amend a fixup but we are having hard

Re: [Qemu-devel] [RFC PATCH 06/10] Move monitor.c to monitor/misc.c

* Kevin Wolf (kw...@redhat.com) wrote: > Create a new monitor/ subdirectory and move monitor.c there. As the plan > is to move the monitor core into separate files, use the chance to > rename it to misc.c. > > Signed-off-by: Kevin Wolf > --- > monitor.c => monitor/misc.c | 0 > Makefile.target

Re: [Qemu-devel] [RFC PATCH 10/10] monitor: Split out monitor/core.c

* Kevin Wolf (kw...@redhat.com) wrote: > Move the monitor core infrastructure from monitor/misc.c to > monitor/core.c. This is code that can be shared for all targets, so > compile it only once. > > What remains in monitor/misc.c after this patch is mostly monitor > command implementations and cod

Re: [Qemu-devel] Sketch of a transition of QEMU docs to Sphinx

On Tue, 21 May 2019 at 19:56, Peter Maydell wrote: > > Currently we have a vague plan that we should migrate our > documentation away from Texinfo to using Sphinx, plus some isolated > bits of documentation already in .rst format. This email is an attempt > to sketch out a transition plan for gett

Re: [Qemu-devel] [RFC PATCH 05/10] monitor: Move cmd_table to MonitorHMP

* Kevin Wolf (kw...@redhat.com) wrote: > Monitor.cmd_table contains the handlers for HMP commands, so there is no > reason to keep it in the state shared with QMP. Move it to MonitorHMP. > > Signed-off-by: Kevin Wolf Reviewed-by: Dr. David Alan Gilbert > --- > monitor.c | 23 +++--

Re: [Qemu-devel] [PATCH 7/8] VNC Acceptance test: check protocol version

On Fri, Jun 07, 2019 at 11:22:22AM -0400, Cleber Rosa wrote: > This goes a bit further than the other tests, and does a basic (read > only) interaction with the VNC protocol. > > This is not a enough to perform a handshake, but enough to make sure > that the socket is somewhat operational and that

Re: [Qemu-devel] [PATCH v4 0/3] numa: deprecate '-numa node, mem' and default memory distribution

Igor Mammedov writes: > Changes since v3: > - simplify series by dropping idea of showing property values in > "qom-list-properties" > and use MachineInfo in QAPI schema instead Where did "[PATCH v3 1/6] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size

Re: [Qemu-devel] Headers without multiple inclusion guards

On Wed, Jun 05, 2019 at 07:52:50PM +0200, Markus Armbruster wrote: > Daniel P. Berrangé writes: > > > On Tue, May 28, 2019 at 08:12:24PM +0200, Markus Armbruster wrote: > >> We have a bunch of headers without multiple inclusion guards. Some are > >> clearly intentional, some look accidental. To

Re: [Qemu-devel] [PATCH] qapi: InitSocketAddress: add keepalive option

Vladimir Sementsov-Ogievskiy writes: > 06.06.2019 14:17, Daniel P. Berrangé wrote: >> On Thu, Jun 06, 2019 at 01:15:33PM +0300, Vladimir Sementsov-Ogievskiy wrote: >>> Signed-off-by: Vladimir Sementsov-Ogievskiy >>> --- >>> >>> Hi all! >>> >>> This is a continuation of "[PATCH v2 0/2] nbd: enabl

Re: [Qemu-devel] [PATCH v6 5/7] qemu-coroutine-sleep: introduce qemu_co_sleep_wake

07.06.2019 18:52, Vladimir Sementsov-Ogievskiy wrote: > 07.06.2019 16:02, Kevin Wolf wrote: >> Am 07.06.2019 um 13:18 hat Vladimir Sementsov-Ogievskiy geschrieben: >>> 07.06.2019 10:57, Kevin Wolf wrote: Am 11.04.2019 um 19:27 hat Vladimir Sementsov-Ogievskiy geschrieben: > Introduce a fun

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