On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the "single-precision" register moves to decodetree:
> * VMSR
> * VMRS
> * VMOV between general purpose register and single precision
>
> Note that the VMSR/VMRS conversions make our handling of
> the "should this UNDEF?" checks consistent between the two
> instructions:
> * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0
> (previously was a nop)
> * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better
> (previously was a nop)
> * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better
> (previously would write to the register, which had no
> guest-visible effect because we always UNDEF reads)
>
> We also tighten up the decode: we were previously underdecoding
> some SBZ or SBO bits.
>
> The conversion of VMOV_single includes the expansion out of the
> gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr()
> sequences into the simpler direct load/store of the TCG temp via
> neon_{load,store}_reg32(): we know in the new function that we're
> always single-precision, we don't need to use the old-and-deprecated
> cpu_F0* TCG globals, and we don't happen to have the declaration of
> gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the
> new function is.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> target/arm/translate-vfp.inc.c | 161 +++++++++++++++++++++++++++++++++
> target/arm/translate.c | 148 +-----------------------------
> target/arm/vfp.decode | 4 +
> 3 files changed, 168 insertions(+), 145 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
