On 6/6/19 12:45 PM, Peter Maydell wrote: > The current VFP code has two different idioms for > loading and storing from the VFP register file: > 1 using the gen_mov_F0_vreg() and similar functions, > which load and store to a fixed set of TCG globals > cpu_F0s, CPU_F0d, etc > 2 by direct calls to tcg_gen_ld_f64() and friends > > We want to phase out idiom 1 (because the use of the > fixed globals is a relic of a much older version of TCG), > but idiom 2 is quite longwinded: > tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) > requires us to specify the 64-bitness twice, once in > the function name and once by passing 'true' to > vfp_reg_offset(). There's no guard against accidentally > passing the wrong flag. > > Instead, let's move to a convention of accessing 64-bit > registers via the existing neon_load_reg64() and > neon_store_reg64(), and provide new neon_load_reg32() > and neon_store_reg32() for the 32-bit equivalents. > > Implement the new functions and use them in the code in > translate-vfp.inc.c. We will convert the rest of the VFP > code as we do the decodetree conversion in subsequent > commits. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- > target/arm/translate.c | 10 +++++++++ > 2 files changed, 30 insertions(+), 20 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
