On 19-02-11 18:12:13, Peter Xu wrote:
> On Wed, Jan 30, 2019 at 01:09:11PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> > replace extended context mode. This patch extends current emulator to
> > support Scalable Mode
Hi Igor,
Thanks for your reply!
On 2/5/2019 11:47 PM, Igor Mammedov wrote:
On Wed, 30 Jan 2019 21:02:10 +0800
"Liu, Jing2" wrote:
Hi everyone,
I have two questions.
1. PCI hotplug on pci.0 must manually rescan in guest. The ACPI hotplug
handler sends the GPE event to guest but it seems gues
Public bug reported:
Hello all,
There is a bug in Qemu related to the enabling of external interrupts
for multicores (Virt machine).
After correcting Qemu as described in #1815078
(https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
interrupts for core 1 at address 0x0C00_2080 w
Paolo Bonzini writes:
> On 12/02/19 10:08, Markus Armbruster wrote:
>> Please wrap your lines at column 70 or so. Humans tend to have trouble
>> following long lines with their eyes (I sure do). Typographic manuals
>> suggest to limit columns to roughly 60 characters for exactly that
>> reason[
On Thu, Feb 07, 2019 at 01:24:28PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> Here is a new simple helper for a very often patter
> around qemu_iovec_init_external, when we need simple qiov with only
> one iov, initialized from external buffer.
>
> v3:
> 01-02: tiny improvements,
Guests started with NVDIMMs larger than the underlying host file produce
confusing errors inside the guest. This happens because the guest
accesses pages beyond the end of the file.
Check the pmem file size on startup and print a clear error message if
the size is invalid.
Fixes: https://bugzill
To make code more readable move handling of locked list to a generic
functions.
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c | 20 +--
hw/rdma/rdma_backend_defs.h | 8 ++--
hw/rdma/rdma_utils.c| 39 +
hw/rdma/rdma_uti
To make code more readable move handling of protected list to a
rdma_utils
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c | 20 +--
hw/rdma/rdma_backend_defs.h | 8 ++--
hw/rdma/rdma_utils.c| 39 +
hw/rdma/rdma_utils.h
The function rdma_poll_cq is called from two contexts - completion
handler thread which sense new completion on backend channel and
explicitly as result of guest issuing poll_cq command.
Add lock to protect against concurrent executions.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
-
The sun4uv_init() function expects vga_interface_type to be either
VGA_STD or VGA_NONE and sets up a stdvga device or no vga card
accordingly.
However, the code in vl.c prefers the Cirrus VGA card to stdvga if
it is available and the user and the machine did not specify anything
else.
So far this h
This hook is not called and was implemented by mistake.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/vmw/pvrdma_main.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
index 90dc9b191b..8b379c6435 100644
--- a
Utilize error_report for all pr_err calls and some pr_dbg that are
considered as errors.
For the remaining pr_dbg calls, the important ones were replaced by
trace points while other deleted.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c| 336 +++
When device is going down free all saved MAD buffers.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c| 34 +-
hw/rdma/vmw/pvrdma_main.c | 2 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/rdma/rdma_bac
Allow interrogating device internals through HMP interface.
The exposed indicators can be used for troubleshooting by developers or
sysadmin.
There is no need to expose these attributes to a management system (e.x.
libvirt) because (1) most of them are not "device-management' related
info and (2) t
Hi,
Please review the following patch-set which consist of cosmetics fixes to
device's user interface (traces, error_report and monitor) and some bug
fixes.
Thanks Markus, Eric, Marcel and David for reviewing v0.
Appreciate your review to this v2.
Still missing r-b for patches 2, 4 and 6.
v0 ->
On 13/02/2019 00:21, David Gibson wrote:
> On Tue, Feb 12, 2019 at 08:01:22PM +, Mark Cave-Ayland wrote:
>> On 12/02/2019 18:21, Philippe Mathieu-Daudé wrote:
>>
>>> On 2/12/19 6:50 PM, Mark Cave-Ayland wrote:
On 12/02/2019 17:21, Philippe Mathieu-Daudé wrote:
>>> If this delay i
This hook was installed to close the device when VM is going down.
After the device is closed there is no need to be informed on VM
shutdown.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/vmw/pvrdma_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/rdma/vmw/
On Wed, Feb 13, 2019 at 07:32:23AM +0100, Philippe Mathieu-Daudé wrote:
>Hi Wei,
>
>On 2/13/19 7:26 AM, Wei Yang wrote:
>> On Tue, Feb 12, 2019 at 12:34:31AM -0500, Michael S. Tsirkin wrote:
>>> On Tue, Feb 12, 2019 at 01:22:24PM +0800, Wei Yang wrote:
On Wed, Jan 30, 2019 at 08:06:50AM +0800,
The function argument rdma_dev_res is not needed as it is stored in the
backend_dev object at init.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c | 13 ++---
hw/rdma/rdma_backend.h | 1 -
hw/rdma/vmw/pvrdma_qp_ops.c | 3 +--
3 files chang
On Tue, Feb 12, 2019 at 12:58:40PM +0100, Kevin Wolf wrote:
> Am 12.02.2019 um 04:22 hat Stefan Hajnoczi geschrieben:
> > On Mon, Feb 11, 2019 at 09:38:37AM +, Vladimir Sementsov-Ogievskiy
> > wrote:
> > > 11.02.2019 6:42, Stefan Hajnoczi wrote:
> > > > On Fri, Feb 08, 2019 at 05:11:22PM +0300
When QP is destroyed the backend QP is destroyed as well. This ensures
we clean all received buffer we posted to it.
However, a contexts of these buffers are still remain in the device.
Fix it by maintaining a list of buffer's context and free them when QP
is destroyed.
Signed-off-by: Yuval Shaia
On 12/02/2019 23:59, BALATON Zoltan wrote:
> Hello,
>
> On Tue, 12 Feb 2019, Philippe Mathieu-Daudé wrote:
>> Hi Zoltan,
>
> Thanks for the quick review and testing. I'll use your suggestions for the
> other
> (mips) patches in a v2. For this one I'm not convinced.
>
>> On 2/11/19 4:19 AM, BAL
On Tue, Feb 12, 2019 at 03:44:46PM +0100, Igor Mammedov wrote:
> > diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
> > index ba601ce940..325ab4aad9 100644
> > --- a/backends/hostmem-file.c
> > +++ b/backends/hostmem-file.c
> > @@ -46,6 +46,22 @@ file_backend_memory_alloc(HostMemoryBa
Hi Wei,
On 2/13/19 7:26 AM, Wei Yang wrote:
> On Tue, Feb 12, 2019 at 12:34:31AM -0500, Michael S. Tsirkin wrote:
>> On Tue, Feb 12, 2019 at 01:22:24PM +0800, Wei Yang wrote:
>>> On Wed, Jan 30, 2019 at 08:06:50AM +0800, Wei Yang wrote:
There are several functions/variable which are not used
On Tue, Feb 12, 2019 at 12:34:31AM -0500, Michael S. Tsirkin wrote:
>On Tue, Feb 12, 2019 at 01:22:24PM +0800, Wei Yang wrote:
>> On Wed, Jan 30, 2019 at 08:06:50AM +0800, Wei Yang wrote:
>> >There are several functions/variable which are not used anymore.
>> >
>> >This serials just remove those wi
Cc'ing the QCOW2 folks.
Drew DeVault writes:
> I recently ran into an issue where I found I couldn't combine the
> -loadvm and -snapshot flags, nor any conceivable combination of
> alternate approaches like loadvm via the monitor. Independently, both
> options work as expected, but together I ge
Daniel P. Berrangé writes:
> Yes, this is another regression accidentally introduced by the keyboard
> state tracker.
>
> When GTK does key repeat it omits the Up event for repeated keys.
>
> IOW, you get
>
> Press (a)
> Press (a)
> Press (a)
> Release (a)
This is how keyboards c
On 01/02/2019 11:40, Alexey Kardashevskiy wrote:
> At the moment the rtas's Makefile uses generic QEMU rules which means
> that when QEMU is compiled on a little endian system, the spapr-rtas.bin
> is compiled as little endian too which is incorrect as it is always
> executed in big endian mode.
> From: Kevin Wolf [mailto:kw...@redhat.com]
> Am 14.01.2019 um 12:10 hat Pavel Dovgalyuk geschrieben:
> > > From: Kevin Wolf [mailto:kw...@redhat.com]
> > > Am 09.01.2019 um 13:13 hat Pavel Dovgalyuk geschrieben:
> > > > Replay is capable of recording normal BH events, but sometimes
> > > > there
On 19-02-11 18:37:41, Peter Xu wrote:
> On Wed, Jan 30, 2019 at 01:09:10PM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested and pass-through modes. The
> >
On Mon, Jan 28, 2019 at 10:46:20AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> And use it to get the correct HILE bit in HID0
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> target/ppc/cpu-qom.h
On Mon, Jan 28, 2019 at 10:46:17AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> This moves the code to handle waking up from the 0x100 vector
> from powerpc_excp() to a separate function, as the former is
> already way too big as it is.
>
> No functional change.
>
> Signed-
On Mon, Jan 28, 2019 at 10:46:21AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> It's very easy for the CPU specific has_work() implementation
> and the logic in ppc_hw_interrupt() to be subtly out of sync.
>
> This can occasionally allow a CPU to wakeup from a PM state
> and
On Mon, Jan 28, 2019 at 10:46:18AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The ISA 2.06/2.07 Power Management instructions (doze, nap & rvwinkle)
> don't exist on POWER9, don't enable them.
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
T
On Mon, Jan 28, 2019 at 10:46:19AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> To better reflect what this does, as it's specific to some of the
> P7/P8/P9 PM states, not generic.
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
Reviewed-by: Da
On Mon, Jan 28, 2019 at 10:46:24AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> It should be generic Hypervisor Virtualization interrupts for HV
> directed rings and traditional External Interrupts for the OS directed
> ring.
>
> Don't generate anything for the user ring as
On Mon, Jan 28, 2019 at 10:46:25AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> This controls whether the External Interrupt (0x500) can be
> delivered to the hypervisor or not.
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
Reviewed-by: David
On Mon, Jan 28, 2019 at 10:46:22AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> This adds support for delivering that exception
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> target/ppc/cpu.h
On Mon, Jan 28, 2019 at 10:46:16AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> STOP must act differently based on PSSCR:EC on POWER9. When set, it
> acts like the P7/P8 power management instructions and wake up at 0x100
> based on the wakeup conditions in LPCR.
>
> When PSS
On Mon, Jan 28, 2019 at 10:46:23AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Adds support for the Hypervisor directed interrupts in addition to the
> OS ones.
>
> Signed-off-by: Benjamin Herrenschmidt
> Signed-off-by: Cédric Le Goater
> ---
> include/hw/ppc/ppc.h
On Wed, Feb 13, 2019 at 11:03:12AM +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2019-02-12 at 16:59 +1100, David Gibson wrote:
> > On Mon, Jan 28, 2019 at 10:46:13AM +0100, Cédric Le Goater wrote:
> > > From: Benjamin Herrenschmidt
> > >
> > > There's no point in going out of translation on an
On Tue, Feb 12, 2019 at 07:24:59PM +0100, Greg Kurz wrote:
> From: Michael Roth
>
> Certain devices types, like memory/CPU, are now being handled using a
> hotplug interface provided by a top-level MachineClass. Hotpluggable
> host bridges are another such device where it makes sense to use a
> m
On Tue, Feb 12, 2019 at 07:24:13PM +0100, Greg Kurz wrote:
> The pseries machine only uses LSIs to support legacy PCI devices. Every
> PHB claims 4 LSIs at realize time. When using in-kernel XICS (or upcoming
> in-kernel XIVE), QEMU synchronizes the state of all irqs, including these
> LSIs, later
On Tue, Feb 12, 2019 at 07:24:33PM +0100, Greg Kurz wrote:
> To support PHB hotplug we need to clean up lingering references,
> memory, child properties, etc. prior to the PHB object being
> finalized. Generally this will be called as a result of calling
> object_unparent() on the PHB object, which
On Tue, Feb 12, 2019 at 08:18:19AM +0100, Cédric Le Goater wrote:
> On 2/12/19 2:11 AM, David Gibson wrote:
> > On Mon, Jan 07, 2019 at 07:39:46PM +0100, Cédric Le Goater wrote:
> >> The interrupt mode is chosen by the CAS negotiation process and
> >> activated after a reset to take into account th
On Tue, Feb 12, 2019 at 07:25:25PM +0100, Greg Kurz wrote:
> Hotplugging PHBs is a machine-level operation, but PHBs reside on the
> main system bus, so we register spapr machine as the handler for the
> main system bus.
>
> Provide the usual pre-plug, plug and unplug-request handlers.
>
> Move t
On Tue, Feb 12, 2019 at 05:09:29PM +0530, P J P wrote:
> From: Prasad J Pandit
>
> On ppc hosts, hypervisor shares following system attributes
>
> - /proc/device-tree/system-id
> - /proc/device-tree/model
>
> with a guest. This could lead to information leakage and misuse.[*]
> Add machine
On Tue, Feb 12, 2019 at 07:24:06PM +0100, Greg Kurz wrote:
> MSI is the default and LSI specific code is guarded by the
> xive_source_irq_is_lsi() helper. The xive_source_irq_set()
> helper is a nop for MSIs.
>
> Simplify the code by turning xive_source_irq_set() into
> xive_source_irq_set_lsi() a
On Tue, Feb 12, 2019 at 07:25:32PM +0100, Greg Kurz wrote:
> From: Michael Roth
>
> The 'dr_phb_enabled' field of that class can be set as part of
> machine-specific init code. It will be used to conditionally
> enable creation of DRC objects and device-tree description to
> facilitate hotplug of
On Tue, Feb 12, 2019 at 07:24:26PM +0100, Greg Kurz wrote:
> This will be used by PHB hotplug in order to create the "interrupt-map"
> property of the PHB node.
>
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Greg Kurz
> ---
> v4: - return phandle via a pointer
You don't really need to do th
On Tue, Feb 12, 2019 at 10:48:27PM +0100, Laurent Vivier wrote:
> A core cannot be split between two nodes.
> To check if a thread of the same core has already been assigned to a node,
> this patch reverses the numa topology checking order and exits if the
> topology is not valid.
I'm not entirely
On Tue, Feb 12, 2019 at 07:25:19PM +0100, Greg Kurz wrote:
> The current logic is to provide the FDT fragment when attaching a device
> to a DRC. This works perfectly fine for our current hotplug support, but
> soon we will add support for PHB hotplug which has some constraints, that
> CPU, PCI and
On Tue, Feb 12, 2019 at 07:24:00PM +0100, Greg Kurz wrote:
> Only pseries machines, either recent ones started with ic-mode=xics
> or older ones using the legacy irq allocation scheme, need to set the
> @offset of the ICS to XICS_IRQ_BASE. Recent pseries started with
> ic-mode=dual set it to 0 and
On Tue, Feb 12, 2019 at 08:12:28AM +0100, Cédric Le Goater wrote:
> On 2/12/19 2:01 AM, David Gibson wrote:
> > On Mon, Jan 07, 2019 at 07:39:44PM +0100, Cédric Le Goater wrote:
> >> The activation of the KVM IRQ device depends on the interrupt mode
> >> chosen at CAS time by the machine and some m
On Tue, Feb 12, 2019 at 01:12:55PM +0100, Roman Kapl wrote:
> The PPC BRANCH exception could bubble up, but this is an QEMU internal
> exception
> and QEMU then crased. Instead it should trigger TRACE exception, according to
> PPC 2.07 book. It could happen only when using branch stepping, which i
On Tue, Feb 12, 2019 at 07:24:19PM +0100, Greg Kurz wrote:
> This will be needed by PHB hotplug in order to access the "phandle"
> property of the interrupt controller node.
>
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Greg Kurz
Reviewed-by: David Gibson
> ---
> v4: - folded some change
On Tue, Feb 12, 2019 at 08:05:53AM +0100, Cédric Le Goater wrote:
> On 2/12/19 2:06 AM, David Gibson wrote:
> > On Mon, Jan 07, 2019 at 07:39:45PM +0100, Cédric Le Goater wrote:
> >> The IRQ number space of the XIVE and XICS interrupt mode are aligned
> >> when using the dual interrupt mode for the
On Tue, Feb 12, 2019 at 10:48:24PM +0100, Laurent Vivier wrote:
> spapr_possible_cpu_arch_ids() counts only cores, and so
> the number of available CPUs is the number of vCPU divided
> by smp_threads.
>
> ... -smp 4,maxcpus=8,cores=2,threads=2,sockets=2 -numa node,cpus=0,cpus=1 \
>
On Tue, Feb 12, 2019 at 08:01:22PM +, Mark Cave-Ayland wrote:
> On 12/02/2019 18:21, Philippe Mathieu-Daudé wrote:
>
> > On 2/12/19 6:50 PM, Mark Cave-Ayland wrote:
> >> On 12/02/2019 17:21, Philippe Mathieu-Daudé wrote:
> >>
> > If this delay is to prevent a bug which only happens in MacO
This patch adds support for a generic MMU-less Nios II board that can
be used e.g. for bare-metal compiler testing. Nios II booting is also
tweaked so that bare-metal binaries start executing in RAM starting at
0x, rather than an alias at 0xc000, which allows features
such as unwinding
This is the fifth version of the patch series last posted here:
http://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg01987.html
Since the previous version, I've updated the copyrights on the new
files, refreshed the patches against current trunk, and fixed bugs in
the implementations of lse
This patch adds support for libgloss semihosting to Nios II bare-metal
emulation.
Signed-off-by: Sandra Loosemore
Signed-off-by: Julian Brown
---
qemu-options.hx| 8 +-
target/nios2/Makefile.objs | 2 +-
target/nios2/cpu.h | 4 +-
target/nios2/helper.c | 11 ++
t
On Tue, Feb 12, 2019 at 03:06:18PM +0100, Philippe Mathieu-Daudé wrote:
> Commit a56de056c91f8 squashed two unrelated commits at once.
> Revert it and reapply the two commits to avoid confusion.
>
> See: https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg02966.html
This does look slightly b
On Tue, Feb 12, 2019 at 10:57:49AM +0100, Paolo Bonzini wrote:
[...]
> +Writing and modifying default configurations
> +
> +
> +In addition to the Kconfig files under hw/, each target also includes
> +a file called ``default-configs/TARGETNAME-softmmu.m
On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote:
> On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
> > Hi,
> >
> > this patchset converts the RISC-V decoder to decodetree in four major
> steps:
> >
> > 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> > Man
On Wed, Feb 13, 2019 at 09:48:57AM +0800, Changpeng Liu wrote:
> Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features
> support" added fields to struct virtio_blk_config. This changes
> the size of the config space and breaks migration from QEMU 3.1
> and older:
>
> qemu-system-ppc64
I recently ran into an issue where I found I couldn't combine the
-loadvm and -snapshot flags, nor any conceivable combination of
alternate approaches like loadvm via the monitor. Independently, both
options work as expected, but together I get this error:
qemu-system-x86_64: Device 'virtio0' does
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Tuesday, February 12, 2019 11:11 PM
> To: Liu, Changpeng
> Cc: qemu-devel@nongnu.org; stefa...@redhat.com; sgarz...@redhat.com;
> dgilb...@redhat.com; ldok...@redhat.com
> Subject: Re: [PATCH v3] virtio-blk
Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features
support" added fields to struct virtio_blk_config. This changes
the size of the config space and breaks migration from QEMU 3.1
and older:
qemu-system-ppc64: get_pci_config_device: Bad config data: i=0x10 read: 41
device: 1 cmask:
On Tue, Feb 12, 2019 at 9:39 AM Fabien Chouteau wrote:
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as bot
Hello,
On Tue, 12 Feb 2019, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
Thanks for the quick review and testing. I'll use your suggestions for the
other (mips) patches in a v2. For this one I'm not convinced.
On 2/11/19 4:19 AM, BALATON Zoltan wrote:
[...]
+
+static void ati_reg_write_offs(
On Tue, 12 Feb 2019, Philippe Mathieu-Daudé wrote:
On 2/11/19 5:01 AM, BALATON Zoltan wrote:
Add (partial) emulation of the on-board GPU of the machine. This
allows the PMON2000 firmware to run and should also work with Linux
console but probably not with X yet.
Signed-off-by: BALATON Zoltan
-
On Tue, 2019-02-12 at 16:59 +1100, David Gibson wrote:
> On Mon, Jan 28, 2019 at 10:46:13AM +0100, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt
> >
> > There's no point in going out of translation on an SMT OR with
> > mttcg since the backend won't do anything useful such as pausing,
On Tue, 2019-02-12 at 17:02 +1100, David Gibson wrote:
> On Mon, Jan 28, 2019 at 10:46:14AM +0100, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt
> >
> > Those instructions currently raise an exception from within
> > the helper. This tends to result in a bogus nip value in
> > the env
On Mon, Jan 28, 2019 at 10:46:14AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Those instructions currently raise an exception from within
> the helper. This tends to result in a bogus nip value in
> the env context (typically the beginning of the TB). Such
> a helper needs
On Mon, Jan 28, 2019 at 10:46:15AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> When issuing a power management instruction, we set MSR:EE
> to force ppc_hw_interrupt() into calling powerpc_excp()
> to deal with the fact that on P7 and P8, the system reset
> caused by the wak
On Mon, Jan 28, 2019 at 10:46:13AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> There's no point in going out of translation on an SMT OR with
> mttcg since the backend won't do anything useful such as pausing,
> it's only useful on traditional TCG to give time to other
> pro
On Tue, Feb 12, 2019 at 3:10 PM Jim Wilson wrote:
>
> The gdb CSR xml file has registers in documentation order, not numerical
> order, so we need a table to map the register numbers. This also adds
> fairly standard gdb hooks to access xml specified registers.
>
> Signed-off-by: Jim Wilson
Rev
On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 3
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/csr.c | 34 ++
2 files changed
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv-64bit-fpu.xml | 52 +
4 files changed, 346 insertion
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 2
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target/ris
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 46
4 files changed, 340 insertions
This is the 4th version of the patch set. Updated as per the review
from Alistair, it has the riscv_csrrw_debug function added, and
Reviewed-By lines added. Otherwise it is the same as the 3rd version.
Jim
On 2/12/19 3:37 PM, John Snow wrote:
>
>
> On 2/12/19 3:16 PM, Eric Blake wrote:
>> On 2/12/19 2:07 PM, John Snow wrote:
>>> When bitmaps are persistent, they may incur a disk read or write when
>>> bitmaps
>>> are added or removed. For configurations like virtio-dataplane, failing to
>>> acquir
A core cannot be split between two nodes.
To check if a thread of the same core has already been assigned to a node,
this patch reverses the numa topology checking order and exits if the
topology is not valid.
Update test/numa-test accordingly.
Fixes: 722387e78daf ("spapr: get numa node mapping f
This will allow to use it in more functions in the future.
As we change the prototype to take directly CpuInstanceProperties
instead of CPUArchId, rename the function to cpu_props_to_string().
Signed-off-by: Laurent Vivier
---
hw/core/machine.c | 44 ++--
There are inconsistencies between the command line using
"-numa node,cpus=XX" and what is checked internally:
the XX is supposed to be a CPU number, but for SPAPR
it's taken as a core number, ignoring the threads.
(See the description message of PATCH 1 for more details)
This series fixes this pro
Change the existing message to an error and exit.
This message was a warning and comes with the information
it will be removed in the future since May 10 2017
(ec78f8114bc4 "numa: use possible_cpus for not mapped CPUs check").
Update tests/numa-test to remove the incomplete CPU mapping test.
Sig
spapr_possible_cpu_arch_ids() counts only cores, and so
the number of available CPUs is the number of vCPU divided
by smp_threads.
... -smp 4,maxcpus=8,cores=2,threads=2,sockets=2 -numa node,cpus=0,cpus=1 \
-numa node,cpus=3,cpus=4 \
Per the GDB remote protocol documentation
https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet
the debug stub is expected to send a reply to the 'vKill' packet. At
least some versions of GDB crash if the gdb stub simply exits without
sending a reply. This patch fixe
On 2/12/19 12:31 AM, Laurent Vivier wrote:
> I know nothing about ARM, but in kernel we have also a "v5t"
> (cpu_elf_name) and in QEMU we have a ARM_FEATURE_V4T which is set with
> ARM_FEATURE_V5. Is it related?
>From the ARM ARM (DDI 0406C, page A1-30):
The valid variants of ARMv4, ARMv5, and AR
Commit 7be41675f7c set -std=gnu99 for C code via QEMU_CFLAGS. Currently
we generate a "custom" QEMU_CXXFLAGS for VSS DLL C++ build by
filtering out some options from QEMU_CFLAGS and adding some others.
Since we don't filter out -std=gnu99 currently this breaks builds when
VSS support is enabled.
W
ommit 0b5e750bea635b167eb03d86c3d9a09bbd43bc06:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2019-02-12 10:53:37 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-hppa-20190212
for you to fetc
On 2/12/19 3:16 PM, Eric Blake wrote:
> On 2/12/19 2:07 PM, John Snow wrote:
>> When bitmaps are persistent, they may incur a disk read or write when bitmaps
>> are added or removed. For configurations like virtio-dataplane, failing to
>> acquire this lock will abort QEMU when disk IO occurs.
>>
Tested-by: Helge Deller
Tested-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 131 +--
target/hppa/insns.decode | 34 +-
2 files changed, 63 insertions(+), 102 deletions(-)
diff --git a/target/hppa/translate.c b/ta
These fix a couple build regressions that have slipped in over that past
couple months and hopefully will help avoid future breakages.
qga/vss-win32/Makefile.objs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Commit 3ebee3b191e defined assert() as g_assert(), but when we build
the VSS DLL component of QGA (to handle fsfreeze) we do not include
glib, which results in breakage when building with VSS support enabled.
Fix this by including glib. Since the VSS DLL is built statically,
this introduces an add
Patches posted:
https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg02863.html
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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