On 2018-10-23 11:04, Laurent Vivier wrote:
> Hi,
>
> I'm going to collect patches for the next pull request for the
> qemu-trivial I'd like to do before the softfreeze.
>
> As we didn't have any pull request for more than 3 months and some of
> the patches have been pushed through another maintai
Hello Cedric,
+-- On Wed, 24 Oct 2018, Cédric Le Goater wrote --+
| I think using a data[8] would be more appropriate. It would make the
| pnv_lpc_do_eccb() routine a little more complex. I tried to rewrite it to
| have a common one with the P9 LPC model but could not find a common pattern.
|
Return value of 0 means ok, we want to free the memory only in case of
error.
Signed-off-by: Yuval Shaia
---
hw/rdma/vmw/pvrdma_cmd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/rdma/vmw/pvrdma_cmd.c b/hw/rdma/vmw/pvrdma_cmd.c
index 4faeb21631..57d6f41ae6 100644
--- a/
>On 18/10/2018 15:04, Philippe Mathieu-Daudé wrote:
>> Hi, this series takes Peng Hao's previous work but rather than adding yet
>> another device, simply add the MMIO interface to the current device (which
>> only implements the I/O port access).
>>
>> The first patches are simple cleanups:
>> - p
On Wed, 2018-10-24 at 07:06 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert Hoo
>
> I am now wondering what els
On Wed, 2018-10-24 at 07:16 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:24PM +0800, Robert Hoo wrote:
> > Add FeatureWordType indicator in struct FeatureWordInfo.
> > Change feature_word_info[] accordingly.
> > Change existing functions that refer to feature_word_info[]
> > accord
Hello Laszlo and Philippe ,
Thanks for your review,
Philippe Mathieu-Daudé 于2018年10月25日周四 上午6:56写道：
> Hi,
>
> On 24/10/18 13:35, Laszlo Ersek wrote:
> > On 10/24/18 09:11, Li Qiang wrote:
> >> This can avoid setting a negative value to
> >> etc/boot-fail-wait.
>
> Li Qiang, can you add a qt
From: Li Qiang
It seems that the intel link is unavailable, change it to point to the
qemu site.
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Marcel Apfelbaum
Acked-by: Michael S. Tsirkin
Reviewed-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 2 +-
1 file chan
From: Li Qiang
Make them more QOMConventional.
Cc:qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
d
From: "Singh, Brijesh"
Emulate the interrupt remapping support when guest virtual APIC is
enabled.
For more information refer: IOMMU spec rev 3.0 (section 2.2.5.2)
When VAPIC is enabled, it uses interrupt remapping as defined in
Table 22 and Figure 17 from IOMMU spec.
Signed-off-by: Brijesh Si
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-bridge/ioh3420.h | 6 --
hw/pci-bridge/ioh3420.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
delete mode 100644 hw/pci-bridge/ioh342
From: "Singh, Brijesh"
Emulate the interrupt remapping support when guest virtual APIC is
not enabled.
For more info Refer: AMD IOMMU spec Rev 3.0 - section 2.2.5.1
When VAPIC is not enabled, it uses interrupt remapping as defined in
Table 20 and Figure 15 from IOMMU spec.
Signed-off-by: Brije
From: Philippe Mathieu-Daudé
Introduced in 48ebf2f90f8 and faf1e708d5b, these functions
were never used. Remove them.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-bridge/xio3130_downstream.h | 11 ---
hw/pci-bridge
From: "Singh, Brijesh"
Currently, the amdvi_validate_dte() assumes that a valid DTE will
always have V=1. This is not true. The V=1 means that bit[127:1] are
valid. A valid DTE can have IV=1 and V=0 (i.e address translation
disabled and interrupt remapping enabled)
Remove the V=1 check from amdv
From: Laszlo Ersek
The "tests/acpi-test-data" files are currently not covered by any section
in MAINTAINERS, and "scripts/checkpatch.pl" complains when new data files
are added.
Cc: "Michael S. Tsirkin"
Cc: Alex Williamson
Cc: Gerd Hoffmann
Cc: Igor Mammedov
Cc: Marcel Apfelbaum
Signed-off-
From: Li Qiang
Cc: qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci
From: "Singh, Brijesh"
The vtd_generate_msi_message() in intel-iommu is used to construct a MSI
Message from IRQ. A similar function will be needed when we add interrupt
remapping support in amd-iommu. Moving the function in common file to
avoid the code duplication. Rename it to x86_iommu_irq_to
From: yuchenlin
There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device,
but seabios will only set the physical address for the 3rd one (cmd).
Then in vhost_virtqueue_start(), virtio_queue_get_desc_addr()
will be 0 for ctrl and event vq.
In this case, ctrl and event vq are not initia
From: "Singh, Brijesh"
Now that amd-iommu support interrupt remapping, enable the GASup in IVRS
table and GASup in extended feature register to indicate that IOMMU
support guest virtual APIC mode. GASup provides option to guest OS to
make use of 128-bit IRTE.
Note that the GAMSup is set to zero
From: Philippe Mathieu-Daudé
Noted while refactoring:
CC mips-softmmu/hw/mips/gt64xxx_pci.o
In file included from include/hw/pci-host/gt64xxx.h:2,
from hw/mips/gt64xxx_pci.c:30:
include/hw/pci/pci_bus.h:23:5: error: unknown type name ‘PCIIOMMUFunc’
From: "Singh, Brijesh"
Interrupt remapping needs kernel-irqchip={off|split} on both Intel and AMD
platforms. Move the check in common place.
Signed-off-by: Brijesh Singh
Reviewed-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
From: Mao Zhongyi
Signed-off-by: Mao Zhongyi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci/pci_bridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 08b7e
From: Laszlo Ersek
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer
From: Laszlo Ersek
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer
From: Yaowei Bai
Here should be submit_requests, there is no submit_merged_requests
function.
Signed-off-by: Yaowei Bai
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/block/virtio-blk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block
From: "Singh, Brijesh"
Register the interrupt remapping callback and read/write ops for the
amd-iommu-ir memory region.
amd-iommu-ir is set to higher priority to ensure that this region won't
be masked out by other memory regions.
Signed-off-by: Brijesh Singh
Cc: Peter Xu
Cc: "Michael S. Tsir
From: Laszlo Ersek
Expose the calculated "hole64 start" GPAs as plain uint64_t values,
extracting the internals of the current property getters.
This patch doesn't change behavior.
Cc: "Michael S. Tsirkin"
Cc: Alex Williamson
Cc: Gerd Hoffmann
Cc: Igor Mammedov
Cc: Marcel Apfelbaum
Signed-
From: Yongji Xie
Some old guests (before commit 7a11370e5: "virtio_blk: enable VQs early")
kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK. This violates
the virtio spec. But virtio 1.0 transitional devices support this behaviour.
So we should start vhost when guest kicks in this case.
S
From: Peter Xu
Provide the function and use it in vtd_init(). Used to reset both
context entry cache and iotlb cache for the whole IOMMU unit.
Signed-off-by: Peter Xu
Reviewed-by: Eric Auger
Reviewed-by: Jason Wang
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i
From: "Singh, Brijesh"
To be consistent with intel-iommu:
- rename the address space to use '_' instead of '-'
- update the memory region relationships
Signed-off-by: Brijesh Singh
Reviewed-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Edua
From: Gerd Hoffmann
Add memory bar to pci-testdev. Size is configurable using the membar
property. Setting the size to zero (default) turns it off. Can be used
to check whether guests handle large pci bars correctly.
Reviewed-by: Marc-André Lureau
Reviewed-by: Laszlo Ersek
Tested-by: Laszlo
From: Peter Xu
There are two callers for vtd_sync_shadow_page_table_range(): one
provided a valid context entry and one not. Move that fetching
operation into the caller vtd_sync_shadow_page_table() where we need to
fetch the context entry.
Meanwhile, remove the error_report_once() directly sin
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova
---
hw/arm/microbit.c | 2 ++
hw/arm/nrf51_soc.c | 20
include/hw/arm/nrf51_soc.h | 3 +++
3 files changed, 25 insertions(+)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
inde
From: Peter Xu
We should handle VTD_FR_CONTEXT_ENTRY_P properly when synchronizing
shadow page tables. Having invalid context entry there is perfectly
valid when we move a device out of an existing domain. When that
happens, instead of posting an error we invalidate the whole region.
Without t
From: "Singh, Brijesh"
When interrupt remapping is enabled, add a special IVHD device
(type IOAPIC).
Signed-off-by: Brijesh Singh
Acked-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Cc: Tom Lendacky
Cc
From: Peter Xu
QEMU is not handling the global DMAR switch well, especially when from
"on" to "off".
Let's first take the example of system reset.
Assuming that a guest has IOMMU enabled. When it reboots, we will drop
all the existing DMAR mappings to handle the system reset, however we'll
sti
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova
---
hw/char/Makefile.objs| 1 +
hw/char/nrf51_uart.c | 330 +++
hw/char/trace-events | 4 +
include/hw/char/nrf51_uart.h | 78 +
4 files changed, 413 insertions(+)
The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into
staging (2018-10-23 17:20:23 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
Acked-by: Thomas Huth
Reviewed-by: Stefan Hajnoczi
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f865822e32..
This series adds support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
v3:
* serial_hd() moved to the board code
* sysbus_init_child_obj() used for initialization
* qemu_chr_fe_accept_input() called after byte popping
v2:
* Suspend/Enable functionalit
Hi Mao,
On 24/10/18 11:40, Mao Zhongyi wrote:
run
git grep '\$here' tests/qemu-iotests
This command doesn't look correct, I believe you have to use either
- git grep '$here'
or
- git grep \$here
has 0 hits, which means we are setting a variable that
no use, so execute the following cmd to
On 24/10/18 12:18, Thomas Huth wrote:
We don't use CONFIG_PARALLEL_ISA in any of our Makefiles, so this
is just a dead config option which can be removed.
Fixes: a4cb773928e047b137c6998209cf2eec857fac6b
Oops, this slipped while refactoring the series, this is part of a
further cleanup that I
On 24/10/18 7:12, Li Qiang wrote:
Also remove unnecessary 'res' variable.
Signed-off-by: Li Qiang
---
hw/nvram/fw_cfg.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 946f765..f4a52d8 100644
--- a/hw/nvram/fw_cfg.c
+++ b
Hi,
On 24/10/18 13:35, Laszlo Ersek wrote:
On 10/24/18 09:11, Li Qiang wrote:
This can avoid setting a negative value to
etc/boot-fail-wait.
Li Qiang, can you add a qtest for this?
Signed-off-by: Li Qiang
---
hw/nvram/fw_cfg.c | 15 ++-
1 file changed, 10 insertions(+), 5 d
On 24/10/18 21:14, Stefan Berger wrote:
Zero-init the ptm_loc structure so that we don't have fields that
are not initialised.
Signed-off-by: Stefan Berger
Reviewed-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_emulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/h
On 24/10/2018 15:06, George Kennedy wrote:
>>
>>
>> Why didn't lsi_do_command invoke lsi_queue_command? That would set
>> s->current to NULL (on the SCSI level, that means the bus is freed; on
>> the QEMU level, the idea is that lsi_transfer_data would then start a
>> reselection).
>
> Through th
On Sat, 20 Oct 2018 00:14:22 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in three major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* functions are called by the decode functions for 16-
Dear KVM and QEMU community,
FOSDEM'19 will feature a Virtualization & IaaS Devroom again. Here is
the call for proposals. Please check it out if you would like to submit
a talk.
Thanks,
Stefan
---
We are excited to announce that the call for proposals is now open for
the Virtualization & IaaS
On Wed, Oct 24, 2018 at 10:06:41PM +0100, Peter Maydell wrote:
> On 24 October 2018 at 21:54, Michael S. Tsirkin wrote:
> > On Wed, Oct 24, 2018 at 07:21:17AM +0100, Peter Maydell wrote:
> >> Hi. This pull request seems to include an accidental update
> >> to the dtc submodule. It's in the "intel_
On Mon, Oct 22, 2018 at 07:08:52PM +0800, Fei Li wrote:
> Hi,
> these two patches are to fix live migration issues. The first is
> about multifd, and the second is to fix some error handling.
>
> But I have a question about using multifd migration.
> In our current code, when multifd is used durin
On 24 October 2018 at 21:54, Michael S. Tsirkin wrote:
> On Wed, Oct 24, 2018 at 07:21:17AM +0100, Peter Maydell wrote:
>> Hi. This pull request seems to include an accidental update
>> to the dtc submodule. It's in the "intel_iommu: move ce fetching out
>> when sync shadow" commit, and it's not m
On 24/10/2018 21:13, Kan Li wrote:
> Summary:
> This is to fix bug https://bugs.launchpad.net/qemu/+bug/1796754.
> It is valid for ifc_buf to be NULL according to
> http://man7.org/linux/man-pages/man7/netdevice.7.html.
>
> Signed-off-by: Kan Li
> ---
> linux-user/syscall.c | 55
> +
On Wed, Oct 24, 2018 at 12:28:52PM +0100, Peter Xu wrote:
> On Wed, Oct 24, 2018 at 07:21:17AM +0100, Peter Maydell wrote:
> > > dtc | 2 +-
> >
> > Hi. This pull request seems to include an accidental update
> > to the dtc submodule. It's in the "intel_iommu: mo
On Wed, Oct 24, 2018 at 07:21:17AM +0100, Peter Maydell wrote:
> On 24 October 2018 at 00:41, Michael S. Tsirkin wrote:
> > The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
> >
> > Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22'
> > into stag
On Wed, Oct 24, 2018 at 12:09:18AM +0200, Paolo Bonzini wrote:
> On 22/10/2018 20:36, Samuel Ortiz wrote:
> > We build a minimal set of ACPI hardware-reduced tables: XSDT,
> > FADT, MADT and a DSDT pointed by a RSDP.
> > The DSDT only contains one PCI host bridge for now.
> >
> > This API will be
On 24/10/2018 19:35, Max Filippov wrote:
> Stack pointer alignment code incorrectly adds stack_size to sp instead
> of subtracting it. It also does not take flat_argvp_envp_on_stack() into
> account when calculating stack_size. This results in initial stack
> pointer misalignment with certain set o
Public bug reported:
Tested on QEMU 3.0.0 on Arch Linux.
I'm using a hidpi screen, and therefore use those environment variables
in order to have GTK+ apps properly scaled:
GDK_SCALE=2
GDK_DPI_SCALE=0.5
However, QEMU, when launched with "-display gtk,gl=on" option, doesn't
scale the window cont
Public bug reported:
-nodefaults has an unclear documentation, I believe it should states it
does not applies to devices created by a machine model.
See https://stackoverflow.com/questions/52908614/qemu-s-nodefaults-not-
working-as-expected-to-me to read how I came to this.
** Affects: qemu
Summary:
This is to fix bug https://bugs.launchpad.net/qemu/+bug/1796754.
It is valid for ifc_buf to be NULL according to
http://man7.org/linux/man-pages/man7/netdevice.7.html.
Signed-off-by: Kan Li
---
linux-user/syscall.c | 55
1 file chan
Public bug reported:
Copy/paste of https://stackoverflow.com/questions/52929723/qemu-eject-
complains-device-is-not-found-while-it-is-there , since I found this bug
trying to find an answer to an own question on Stack Overflow.
Below, what was my question the answer I wrote, all exposes the bug.
Zero-init the ptm_loc structure so that we don't have fields that
are not initialised.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_emulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/tpm/tpm_emulator.c b/hw/tpm/tpm_emulator.c
index 10bc20dbec..968f06ae3b 100644
---
Stack pointer alignment code incorrectly adds stack_size to sp instead
of subtracting it. It also does not take flat_argvp_envp_on_stack() into
account when calculating stack_size. This results in initial stack
pointer misalignment with certain set of command line arguments and
environment variable
On Wed, Oct 24, 2018 at 10:19 AM Max Filippov wrote:
>
> On Wed, Oct 24, 2018 at 4:35 AM Laurent Vivier wrote:
> > > diff --git a/linux-user/flatload.c b/linux-user/flatload.c
> > > index 2eefe55e5000..1893966b5b30 100644
> > > --- a/linux-user/flatload.c
> > > +++ b/linux-user/flatload.c
>
> > >
On 24 October 2018 at 14:40, Aleksandar Markovic
wrote:
> From: Aleksandar Markovic
>
> The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22'
> into staging (2018-10-23 17:20:23 +0100)
>
> are a
Using 64-bit arithmetic increases the performance for xts-aes-128
when built with gcrypt:
Encrypt: 355 MB/s -> 545 MB/s
Decrypt: 362 MB/s -> 568 MB/s
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
crypto/xts.c | 40
1 file changed
Hi Philippe,
> The three-operand MADD and MADDU are specific to the
> Toshiba TX19/TX39/TX79 cores.
>
> The "32-Bit TX System RISC TX39 Family Architecture manual"
> is available at https://wiki.qemu.org/File:DSAE0022432.pdf
>
> Signed-off-by: Philippe Mathieu-Daudé
I'm queueing your MADD and M
Add testing coverage for AES with XTS, ECB and CTR modes
Reviewed-by: Marc-André Lureau
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
tests/benchmark-crypto-cipher.c | 149 +++-
1 file changed, 126 insertions(+), 23 deletions(-)
diff --git a/tes
The tweak encrypt/decrypt functions are identical except for the
comments, so can be merged. Profiling data shows that the compiler is
in fact already merging the two merges in the object files.
Reviewed-by: Marc-André Lureau
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
cr
The new type is designed to allow use of 64-bit arithmetic instead
of operating 1-byte at a time. The following patches will use this to
improve performance.
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
crypto/xts.c | 46 ++
1 fil
Encouraging the compiler to inline xts_tweak_encdec increases the
performance for xts-aes-128 when built with gcrypt:
Encrypt: 545 MB/s -> 580 MB/s
Decrypt: 568 MB/s -> 602 MB/s
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
crypto/xts.c | 10 +-
1 file changed,
Using 64-bit arithmetic increases the performance for xts-aes-128
when built with gcrypt:
Encrypt: 272 MB/s -> 355 MB/s
Decrypt: 275 MB/s -> 362 MB/s
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
crypto/xts.c | 84
1
The following changes since commit c96292036a17857d62b8b5d3c8752bac3d6b7193:
Merge remote-tracking branch
'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging (2018-10-24
16:31:40 +0100)
are available in the Git repository at:
https://github.com/berrange/qemu tags/qcrypto-ne
Validate that the XTS cipher mode will correctly operate with plain
text, cipher text and IV buffers that are not 64-bit aligned.
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
tests/test-crypto-xts.c | 86 +
1 file changed, 86 insertio
The current XTS test overloads two different tests in a single function
making the code a little hard to follow. Split it into distinct test
cases.
Reviewed-by: Alberto Garcia
Signed-off-by: Daniel P. Berrangé
---
tests/test-crypto-xts.c | 140 +++-
1 file ch
Hi Philippe,
On Wed, Oct 24, 2018 at 12:57:32PM +0200, Philippe Mathieu-Daudé wrote:
> Increase the size of 'membership' holder size to 64 bits. This is
> needed for future extensions since existing bits are almost all used.
> (This change is related to f9c9cd63e3),
I'm queueing your patch to ame
Hi all,
I am trying to use QEMU vIOMMU for virtio DMA remapping. When I run the
VM, I get the following messages in stderr:
qemu-system-x86_64: vtd_iommu_translate: detected translation failure
(dev=01:00:00, iova=0x0)
qemu-system-x86_64: New fault is not recorded due to compression of faults
qe
From: Dimitrije Nikolic
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.
Signed-off-by: Dimitrije Nikolic
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 128 ++
From: Aleksandar Markovic
Add nanoMIPS CRC32 instruction pool.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c44a751..4338b9a 100644
--- a/target/mips/transl
From: Aleksandar Markovic
Add some nanoMIPS bits and pieces that for various reasons
didn't manage to be integrated.
Aleksandar Markovic (2):
target/mips: Add nanoMIPS CRC32 instruction pool
target/mips: Add disassembler support for nanoMIPS
Dimitrije Nikolic (1):
target/mips: Implement e
On Wed, Oct 24, 2018 at 4:35 AM Laurent Vivier wrote:
> > diff --git a/linux-user/flatload.c b/linux-user/flatload.c
> > index 2eefe55e5000..1893966b5b30 100644
> > --- a/linux-user/flatload.c
> > +++ b/linux-user/flatload.c
> > -sp -= 16 - ((sp + stack_len) & 15);
> > +if ((sp - stac
On 10/23/18 5:37 PM, David Gibson wrote:
> On Mon, Oct 22, 2018 at 05:49:07PM +0530, P J P wrote:
>> From: Prasad J Pandit
>>
>> While performing PowerNV memory r/w operations, the access length
>> 'sz' could exceed the data[4] buffer size. Add check to avoid OOB
>> access.
>>
>> Reported-by: Mogu
This compilation issue will occur when user use --disable-replication
to config Qemu.
Reported-by: Thomas Huth
Signed-off-by: Zhang Chen
---
migration/colo.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/migration/colo.c b/migration/colo.c
index 956ac236
On 21/10/2018 17:55, Max Filippov wrote:
> bFLT format header doesn't have enough information to register a handler
> for a specific architecture. Add switch -f / --flat that registers one
> of the qemu binaries as a handler for bFLT executable images.
>
> Signed-off-by: Max Filippov
> ---
> Chan
Without that, window effects in KWin get suspended as soon as any
qemu-sdl window becomes visible. While the SDL default makes sense
for games, it's not really suitable for QEMU.
Signed-off-by: Sebastian Krzyszkowiak
---
ui/sdl2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ui/sdl2.c
On 24 October 2018 at 10:52, Thomas Huth wrote:
> Hi Peter,
>
> the following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22'
> into staging (2018-10-23 17:20:23 +0100)
>
> are available in the git repo
On 24 October 2018 at 12:16, wj193102 wrote:
> Hi，everybody。
> Now I have installed QEMU3.0.0. I want to launch wine by QEMU. But I can't
> find qemu-runtime-i386-XXX.tar.gz and qemu-XXX-i386-wine.tar.gz on the QEMU
> web page.
> Please tell me how I can get them and use the wine by QEMU? Thank
From: Fredrik Noring
Add a placeholder for LQ instruction.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c
From: Aleksandar Markovic
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.
Reviewed-by: Stefan Markovic
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 40 ---
From: Fredrik Noring
Add a placeholder for MMI3 subclass.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/m
From: Aleksandar Markovic
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.
Reviewed-by: Stefan Markovic
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translat
From: Fredrik Noring
Add support for DIV1 and DIVU1 instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/transla
From: Fredrik Noring
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 48
1 file changed, 48 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/transl
** Tags added: linux-user sh4
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1796520
Title:
autogen crashes on qemu-sh4-user after 61dedf2af7
Status in QEMU:
New
Bug description:
Running "auto
From: Fredrik Noring
Add a test for MULTU.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/multu.c | 39 +++
2 files changed, 40 inser
From: Fredrik Noring
Add a test for MTLO1 and MTHI1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/mtlohi1.c | 40 ++
2 files change
From: Fredrik Noring
Add a test for DIV1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/Makefile | 3 +-
tests/tcg/mips/mipsr5900/div1.c | 73 +++
2 files changed, 75 inser
From: Fredrik Noring
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksand
From: Fredrik Noring
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
targe
From: Fredrik Noring
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.
This change adds the function check_insn_opc_user_only to sign
From: Fredrik Noring
Add a test for MULTU1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/multu.c | 43 +---
1 file changed, 36 insertions(+), 7 deletions(-)
diff --git a/tes
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