On Fri, Feb 17, 2017 at 10:18:35AM -0700, Alex Williamson wrote:
> On Tue, 7 Feb 2017 16:28:02 +0800
> Peter Xu wrote:
>
> > This is v7 of vt-d vfio enablement series.
> [snip]
> > =
> > Test Done
> > =
> >
> > Build test passed for x86_64/arm/ppc64.
> >
> > Simply tested with
+-- On Fri, 17 Feb 2017, Peter Maydell wrote --+
| Alistair's point is that when you resend a patchset where some patches have
| got reviews/acks and those patches haven't changed significantly, you should
| include the Reviewed-by: or Acked-by: tags in the commit messages on the
| resent patche
On Fri, Feb 17, 2017 at 11:29 PM, Nish Aravamudan <
nish.aravamu...@canonical.com> wrote:
> I believe Christian has it on his todo for the next SRU, though;
> Christian, could you confirm?
>
Yes, that is correct.
Sorry for the inconvenient delay due to the chain SRUs.
But at least the bigger ones
On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> The logical partitioning control register controls a threads operation
> based on the partition it is currently executing. Add new definitions and
> update the mask used when writing to the LPCR based on the POWER9 spec.
>
> S
Hi Peter,
On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell wrote:
> On 17 February 2017 at 06:31, wrote:
>> From: Vijaya Kumar K
>>
>> To Save and Restore ICC_SRE_EL1 register introduce vmstate
>> subsection and load only if non-zero.
>> Also initialize icc_sre_el1 with to 0x7 in pre_load
>> fun
On 19.02.2017 04:55, Philippe Mathieu-Daudé wrote:
> On 02/17/2017 05:27 AM, Ziyue Yang wrote:
>> From: Ziyue Yang
>>
>> Currently mon_get_cpu always dereferences first_cpu without checking
>> whether it's a valid pointer. This commit adds check before
>> dereferencing,
>> and reports "No CPU" inf
On 17.02.2017 09:27, Ziyue Yang wrote:
> From: Ziyue Yang
>
> Many QEMU monitor commands, like "info lapic", "info tlb" and so on
> use mon_get_cpu or related wrappers to access CPU info without checking
> whether the CPU exists.
> This patch series fix the "info lapic" case, and is the base of t
On Mon, Feb 20, 2017 at 03:04:30PM +1100, Suraj Jitindar Singh wrote:
> The DPFD field in the LPCR is 3 bits wide. This has always been defined
> as 0x3 << shift which indicates a 2 bit field, which is incorrect.
> Correct this.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
Acked-by: Balbir Sing
Destination host unreachable.
Ping again.
Pavel Dovgalyuk
> -Original Message-
> From: Pavel Dovgalyuk [mailto:dovga...@ispras.ru]
> Sent: Monday, February 13, 2017 8:05 AM
> To: 'Pavel Dovgalyuk'; qemu-devel@nongnu.org
> Cc: kw...@redhat.com; pbonz...@redhat.com; qemu-bl...@nongnu.org;
On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote:
> POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
>
> Add a definition for this mmu model and set the POWER9 cpu model to use
> this mmu model.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
> target
Hi, Gaohuai
I tried to debug the problem, and I found the indirect cause may be that
the rmap value is not cleared when KVM mmu page is freed. I have read
code without the root cause. Can you stable reproduce the the issue?
Many guesses need to be verified.
On Mon, 2017-02-20 at 10:17 +0800, han
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/696530
Title:
qemu-0.13.0-
POWER9 doesn't have a storage description register 1 (SDR1) which is used
to store the base and size of the hash table. Thus we don't need to
generate this register on the POWER9 cpu model and thus shouldn't read or
write to it either. While we're here, init_proc_book3s_64 is a convoluted
mess whic
The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.
Signed-off-by: S
Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.
Signed-off-by: Suraj Jitindar Singh
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 18 ++
1 file changed, 18 insertio
ISA v3.00 adds the idea of a partition table which is used to store the
address translation details for all partitions on the system. The partition
table consists of double word entries indexed by partition id where the second
double word contains the location of the process table in guest memory.
Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).
This now allows a POWER9 cpu to boot to userspace in tcg emulation for a
pseries machine with a legacy kernel.
Signed-off-by: Suraj Jitindar Singh
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h| 18 ++
Add a new mmu fault handler for the POWER9 cpu and add it as the handler
for the POWER9 cpu definition.
This handler checks if the guest is radix or hash based on the value in the
partition table entry and calls the correct fault handler accordingly.
The hash fault handling code has also been upd
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jiti
This is V3 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.
To use a POWER9 cpu provide the command line option
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu-qom.h| 5 -
target/ppc/mmu_helper.c | 2 ++
target/ppc/transl
From: XiongZhang
If IGD isn't assigned at 00:02.0 in UPT and host bios enable stolen
memory, seabios won't reseave stolen memory in E820 for guest. Then
both Intel graphic driver and others in guest could use stolen
memory, this will generate system hang. So we should disable stolen
memory in thi
On 2017年02月17日 10:53, zhanghailiang wrote:
This series includes two parts: codes optimization and bug fix.
patch 1 tries to move timer process into colo compare thread as
a new coroutine.
patch 2 ~ 4 fixe some bugs of colo compare.
v2->v3:
- change the definition of remove_fd_in_watch() inst
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH] vfio/pci-quirks.c: Disable stolen memory for igd
VFIO
Message-id: 20170220111716.10471-1-xiong.y.zh...@intel.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BAS
From: XiongZhang
If IGD isn't assigned at 00:02.0 in UPT and host bios enable stolen
memory, seabios won't reseave stolen memory in E820 for guest. Then
both Intel graphic driver and others in guest could use stolen
memory, this will generate system hang. So we should disable stolen
memory in thi
Hi, Kai Huang and Xiao Guangrong.
For the problem mentioned above, there may be a bug related to PML and probably
on Broadwell CPUs.
I've been reading the code for PML for days, but I haven't found any clews. Do
you have any idea about this BUG ?
Hope you can help!
On 2017/2/10 23:28, Chris F
This patch is to deal with fault event reported from IOMMU driver.
Signed-off-by: Lan Tianyu
---
hw/i386/intel_iommu.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9b1ba1b..79507d2 100644
--- a/hw/i386/intel_io
Resend patchset due to wrong Qemu devel mail address. Sorry for noise.
This patchset proposes a solution for vIOMMU to get hardware IOMMU
fault event and info. Motivation is to make vIOMMU inject associated
fault event when pIOMMU reports fault event. vIOMMU is in charge of
transforming fault info
This patch is to implement fault event handler with new vfio cmd to
get fault info and notify vIOMMU device model.
Signed-off-by: Lan Tianyu
---
hw/vfio/common.c | 51 ++
linux-headers/linux/vfio.h | 22
2 files changed,
This patch is to assign an event fd to VFIO IOMMU type1 driver
in order to get notification when IOMMU driver reports fault event.
Signed-off-by: Lan Tianyu
---
hw/vfio/common.c | 37 +
include/hw/vfio/vfio-common.h | 3 +++
linux-headers/linux/
Hervé Poussineau writes:
> Hi,
>
> Le 09/01/2017 à 14:48, Paolo Bonzini a écrit :
>>
>>
>> On 09/01/2017 13:49, Markus Armbruster wrote:
>>> Hervé Poussineau writes:
>>>
'ide-hd', 'ide-cd' and 'scsi-cd' devices already disable default cdrom.
Make it the same for 'scsi-hd'.
Th
Eric Blake writes:
> On 02/14/2017 12:25 AM, Denis V. Lunev wrote:
>> From: Anton Nefedov
>>
>> Windows reports BSOD parameters through Hyper-V crash MSRs. This
>> information is very useful for initial crash analysis and thus
>> it would be nice to have a way to fetch it.
>>
>> Signed-off-by:
These changes use a vxhs test server that is a part of the following
repository:
https://github.com/VeritasHyperScale/libqnio.git
Signed-off-by: Ashish Mittal
---
v9 changelog:
(1) Dropped second argument to set_prog_path(). We will pick up the test
server location from the user's PATH env se
Source code for the qnio library that this code loads can be downloaded from:
https://github.com/VeritasHyperScale/libqnio.git
Sample command line using JSON syntax:
./x86_64-softmmu/qemu-system-x86_64 -name instance-0008 -S -vnc 0.0.0.0:0
-k en-us -vga cirrus -device virtio-balloon-pci,id=bal
f_fpregs is a 2d array, not 1d:
typedef struct fpregset
{
int f_pcr;
int f_psr;
int f_fpiaddr;
#ifdef __mcoldfire__
int f_fpregs[8][2];
#else
int f_fpregs[8][3];
#endif
} fpregset_t;
For the moment, we don't manage ColdFire case, only 680x0.
Signed-off-by: Laurent Vivier
--
Hello!
Problem: function imx_gpt_reset is used for soft (requested by guest)
and hard resets. But soft and hard resets should have different
behaviour (hard reset should clear all registers, while soft reset
should preserve some bits).
Patch changelog:
v1 -> v2: use different approach, patch
On Thu, 2017-02-16 at 21:14 +0200, Marcel Apfelbaum wrote:
> > Wait, actually.. we have two possible directions to go, both of which
> > have been mentioned in the thread, but I don't think we've settled on
> > one:
> >
> > 1) Have pseries create a PCIe bus (as my first cut draft does).
> >
>
On 02/18/2017 01:38 PM, Peter Maydell wrote:
> On 18 February 2017 at 17:45, Michael Davidsaver
> wrote:
>> On 02/16/2017 09:11 AM, Peter Maydell wrote:
>>> I haven't actually checked real hardware behaviour, but I think
>>> we can fairly safely implement this as not checking the IPSR
>>> excepti
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 6 +++---
hw/display/sm501_template.h | 31 ++-
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 9091bb5..3d32a3c 100644
--- a/hw/display/sm50
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index e966896..9091bb5 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -474,6 +474,7 @@ typedef struct SM501State {
uint32_t gpi
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 1132 ++-
hw/display/sm501_template.h | 52 +-
2 files changed, 594 insertions(+), 590 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 040a0b9..4f40dee 100644
--- a/h
This series improves the sm501 display controller emulation fixing
endianness problems that caused mixed up colors in LE hosts, fix hardware
cursor and adding panel layer support and some missing registers. The
first few patches update the code style and QOMify the device before
changes are made to
Only the display controller part is created automatically on PCI
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 58 +
hw/display/sm501_template.h | 8 +++
2 files changed, 58 insertions(+), 8 deletions(-)
diff --git a/hw/display/
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 73 +++---
1 file changed, 37 insertions(+), 36 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 1bd0303..2e1c4b7 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 133 +++
hw/sh4/r2d.c | 11 -
include/hw/devices.h | 5 --
3 files changed, 101 insertions(+), 48 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 4eb085
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 169 +---
hw/display/sm501_template.h | 25 +++
2 files changed, 107 insertions(+), 87 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 3d32a3c..1bd0303 100644
---
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 8
hw/display/sm501_template.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 4f40dee..4eb085c 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@
This is not used by default on any emulated machine yet but it is
still useful to have it compiled so it can be added from the command
line for clients that can use it (e.g. MorphOS has no driver for any
other emulated video cards but can output via SM501)
Signed-off-by: BALATON Zoltan
---
defau
Write only to allow clients to initialise these without failing
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 2e1c4b7..16a00cc 100644
--- a/hw/disp
On 19 February 2017 at 07:22, Chad Joan wrote:
> I suspect I'm going to encounter this problem again as I try to make small
> fixes for more projects, so it might be worth it for me to spend a small
> amount of time at some point setting up a mail client that I can send git
> patches with. Or per
Le 18/02/2017 à 23:37, Peter Maydell a écrit :
> On 7 February 2017 at 18:33, Laurent Vivier wrote:
>> This also adds the basic test file and the configuration update.
>>
>> This implementation can only test instructions with values in register and
>> no memory access.
>>
>> Signed-off-by: Laurent
Le 18/02/2017 à 23:31, Helge Deller a écrit :
> Add the neccessary sockopts for ping and traceroute on IPv6.
>
> This fixes the following qemu warnings with IPv6:
> Unsupported ancillary data: 0/2
> Unsupported ancillary data: 0/11
> Unsupported ancillary data: 41/25
> Unsupported setsockopt level
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