On Wed, Jul 27, 2016 at 12:01:33PM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
>
> > [ Unknown signature status ]
> > On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> >> From: Vivek Andrew Sha
> >>
> >> Adds Vector Shift Right Variable instruction.
> >>
> >> Sign
David Gibson writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 11:47:15AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > [ Unknown signature status ]
>> > On Tue, Jul 26, 2016 at 05:28:30PM +0530, Nikunj A Dadhania wrote:
>> >> While implementing modulo instructi
On Wed, Jul 27, 2016 at 11:47:15AM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
>
> > [ Unknown signature status ]
> > On Tue, Jul 26, 2016 at 05:28:30PM +0530, Nikunj A Dadhania wrote:
> >> While implementing modulo instructions figured out that the
> >> implementation uses many branch
On Tue, Jul 26, 2016 at 05:28:23PM +0530, Nikunj A Dadhania wrote:
> This set starts adding new instructions for POWER9 described in ISA3.0.
>
> Patches:
> 01-02: First two patches adds the required POWER9 cpu model and ISA defines.
> 03-14: Adds following instructions:
> addpcis
Hi Edger,
>
> A few first pass comments inline
>
Thanks for review.
>> +typedef struct SMMUTransCfg {
>> +union {
>> +hwaddr va; /* Input to S1 */
>> +hwaddr ipa; /* Input to S2 */
>> +};
>
> I think we could just use va here.
>
Agreed
>> +u
David Gibson writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
>> From: Vivek Andrew Sha
>>
>> Adds Vector Shift Right Variable instruction.
>>
>> Signed-off-by: Vivek Andrew Sha
>> Signed-off-by: Nikunj A Dadhania
>> ---
>> target-p
On Tue, Jul 26, 2016 at 05:28:24PM +0530, Nikunj A Dadhania wrote:
> From: "Aneesh Kumar K.V"
>
> The patch adds CPU PVR definition for POWER9 and enables QEMU to launch
> guests/linux-user in TCG mode.
>
> Signed-off-by: Aneesh Kumar K.V
> [ Added POWER9 alias, POWER9 SPAPR core and dropped MM
C code can test ABI version with this macro.
Signed-off-by: Fam Zheng
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index 879324b..e04e59f 100755
--- a/configure
+++ b/configure
@@ -5069,6 +5069,10 @@ if test "$sdl" = "yes" ; then
echo "CONFIG_SDL
Signed-off-by: Fam Zheng
---
Makefile.objs | 1 +
configure | 4 +--
include/qemu/module.h | 2 ++
include/ui/console.h | 5 ++--
ui/Makefile.objs | 2 ++
ui/sdl-init.c | 75 +++
ui/sdl.c | 19
The new module is named ui-sdl.so, following the name scheme of existing
block-iscsi.so, etc..
Fam Zheng (3):
rules.mak: Don't extract libs from .mo-libs in link command
configure: Add CONFIG_SDL2
sdl: Modularize
Makefile.objs | 1 +
configure | 8 --
include/qemu
For module build, .mo objects are passed to LINK and consumed in
process-archive-undefs. The reason behind that is documented in the
comment above process-archive-undefs.
Similarly, extract-libs should be called with .mo filtered out too.
Otherwise, the .mo-libs are added to the link command incor
David Gibson writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:55AM +0530, Nikunj A Dadhania wrote:
>> From: Swapnil Bokade
>>
>> Adds following instructions:
>>
>> vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
>> vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
David Gibson writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:54AM +0530, Nikunj A Dadhania wrote:
>> From: Sandipan Das
>>
>> Adds following instructions:
>>
>> vabsdub: Vector Absolute Difference Unsigned Byte
>> vabsduh: Vector Absolute Difference Unsigned Halfword
>>
On Wed, Jul 27, 2016 at 10:44:42AM +0530, Bharata B Rao wrote:
> Boot CPU is assumed to be always present in QEMU code. So
> until that assumptions are gone, deny removal request.
> In another words, QEMU won't support boot CPU core hot-unplug.
>
> Signed-off-by: Bharata B Rao
Applied to ppc-for
David Gibson writes:
> [ Unknown signature status ]
> On Tue, Jul 26, 2016 at 05:28:30PM +0530, Nikunj A Dadhania wrote:
>> While implementing modulo instructions figured out that the
>> implementation uses many branches. Change the logic to achieve the
>> branch-less code. Undefined value is set
On Tue, Jul 26, 2016 at 05:28:38PM +0530, Nikunj A Dadhania wrote:
> ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level
> indirect opcode table and corresponding parsing routines.
>
> EO (11:12) Expanded opcode field
> Formats: XX1
>
> EO (11:15) Expanded opcode field
> Formats: V
On Wed, Jul 27, 2016 at 12:56:54AM +0530, Nikunj A Dadhania wrote:
> From: Sandipan Das
>
> Adds following instructions:
>
> vabsdub: Vector Absolute Difference Unsigned Byte
> vabsduh: Vector Absolute Difference Unsigned Halfword
> vabsduw: Vector Absolute Difference Unsigned Word
>
> Signed-o
On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> From: Vivek Andrew Sha
>
> Adds Vector Shift Right Variable instruction.
>
> Signed-off-by: Vivek Andrew Sha
> Signed-off-by: Nikunj A Dadhania
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 17 +
On Wed, Jul 27, 2016 at 12:56:58AM +0530, Nikunj A Dadhania wrote:
> extswsli : Extend Sign Word & Shift Left Immediate
>
> Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
> ---
> target-ppc/translate.c | 30 ++
> 1 file changed, 30 insertions(+)
>
> di
On Wed, Jul 27, 2016 at 12:56:53AM +0530, Nikunj A Dadhania wrote:
> From: Sandipan Das
>
> DFP Test Significance Immediate [Quad]
>
> Signed-off-by: Sandipan Das
> Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
> ---
> target-ppc/dfp_helper.c | 35 +
On Wed, Jul 27, 2016 at 12:56:55AM +0530, Nikunj A Dadhania wrote:
> From: Swapnil Bokade
>
> Adds following instructions:
>
> vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
> vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
> vcmpnezw[.]: Vector Compare Not Equal or Zero Word
>
> Sig
On Tue, Jul 26, 2016 at 05:28:30PM +0530, Nikunj A Dadhania wrote:
> While implementing modulo instructions figured out that the
> implementation uses many branches. Change the logic to achieve the
> branch-less code. Undefined value is set to dividend in case of invalid
> input.
>
> Signed-off-by
On Wed, Jul 27, 2016 at 12:56:56AM +0530, Nikunj A Dadhania wrote:
> From: Vivek Andrew Sha
>
> vslv: Vector Shift Left Variable
>
> Signed-off-by: Vivek Andrew Sha
> Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.
On 07/27/2016 10:50 AM, Jason Wang wrote:
On 2016年07月27日 10:32, Zhang Chen wrote:
Hi~ all~~
Anyone have some comments for this series?
Will have a look at this.
Btw. I wonder how this is tested, do we need a unit test for this?
COLO-compare and filter-rewriter works normal depend on co
Boot CPU is assumed to be always present in QEMU code. So
until that assumptions are gone, deny removal request.
In another words, QEMU won't support boot CPU core hot-unplug.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr_cpu_core.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/ppc
On Wed, Jul 27, 2016 at 10:01:41AM +0530, Bharata B Rao wrote:
> On Wed, Jul 27, 2016 at 08:22:51AM +0530, Bharata B Rao wrote:
> > Hi,
> >
> > Coalesced mmio buffer is part of vCPU 0's kvm_run mmap'ed area
> > and with the introduction of CPU hotplug, vCPU 0 can be removed on
> > PowerPC leading
On Wed, Jul 27, 2016 at 07:27:11AM +0300, Marcel Apfelbaum wrote:
> On 07/26/2016 09:30 PM, Michael S. Tsirkin wrote:
> > On Sun, Jul 17, 2016 at 07:53:07PM +0300, Marcel Apfelbaum wrote:
> > >
> > > v4 -> v5:
> > > Addressed the pull request issues: (Peter Maydell)
> > > See: https://lists.gn
On Wed, 2016-07-27 at 12:19 +1000, David Gibson wrote:
> twi etc will generally resume from the next instruction if they trap,
> yes? In which case I'm a bit confused by the nip - 4. But possibly I
> just haven't correctly followed all the nip update logic changed by
> this patch.
>From the ISA
On Wed, Jul 27, 2016 at 08:22:51AM +0530, Bharata B Rao wrote:
> Hi,
>
> Coalesced mmio buffer is part of vCPU 0's kvm_run mmap'ed area
> and with the introduction of CPU hotplug, vCPU 0 can be removed on
> PowerPC leading to the below seen segfault in QEMU.
>
>
> This happens because during CPU
On 07/26/2016 09:30 PM, Michael S. Tsirkin wrote:
On Sun, Jul 17, 2016 at 07:53:07PM +0300, Marcel Apfelbaum wrote:
v4 -> v5:
Addressed the pull request issues: (Peter Maydell)
See: https://lists.gnu.org/archive/html/qemu-devel/2016-07/msg00882.html
- cland warning -> "hw/pci/pci.c:196:23
On Mon, Jul 25, 2016 at 02:27:18PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Mon, Jul 25, 2016 at 10:41 AM, Prerna wrote:
> >
> >
> > On Thu, Jul 7, 2016 at 12:04 PM, Prerna Saxena
> > wrote:
> >>
> >> From: Prerna Saxena
> >>
> >> The current vhost-user protocol requires the client to send r
On Mon, Jul 25, 2016 at 02:43:35PM +0300, Shmulik Ladkani wrote:
> From: Shmulik Ladkani
>
> In cases where iov_copy() is passed with zero 'bytes' argument and a
> non-zero 'offset' argument, nothing gets copied - as expected.
>
> However since no copy iterations are performed, 'offset' is left
On Wed, 2016-07-27 at 12:47 +1000, David Gibson wrote:
> > +#if defined(HOST_WORDS_BIGENDIAN)
> > + memcpy(&env->gpr[reg], src, adjlen);
> > + reg += (adjlen >> 2);
> > + addr = addr_add(env, addr, adjlen);
> > +#else
> > + while(adjlen) {
> > + env->gpr[reg++
On Wed, 2016-07-27 at 12:36 +1000, David Gibson wrote:
> > - do_dcbz(env, addr, dcbz_size, GETPC());
> > + /* Try fast path translate */
> > + haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx);
>
> It worries me slightly that this doesn't take any length to verify. I
>
On Wed, 2016-07-27 at 12:33 +1000, David Gibson wrote:
>
> Should you be returning true here?
>
> Without it, IIUC, the functions below will generate the unconditional
> trap, then generate more code to actually test the condition and trap
> again.
You are right, we generate dead code, will fix.
On Wed, 2016-07-27 at 12:30 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:18AM +1000, Benjamin Herrenschmidt
> wrote:
> >
> > The current alignment exception generation tries to load the opcode
> > to put in DSISR from a context where a cpu_ldl_code() is really not
> > a good idea. It
On Wed, 2016-07-27 at 12:26 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:15AM +1000, Benjamin Herrenschmidt
> wrote:
> >
> > This is no longer necessary as the helpers will properly retrieve
> > the return address when needed.
>
> Is this right? Don't the tw etc. instructions conti
On Wed, 2016-07-27 at 12:21 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:12AM +1000, Benjamin Herrenschmidt
> wrote:
> >
> > This is no longer necessary as the helpers will properly retrieve
> > the return address when needed
>
> Well, the helpers are only fixed in this patch IIUC.
On Wed, 2016-07-27 at 12:19 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:10AM +1000, Benjamin Herrenschmidt
> wrote:
> >
> > We make env->nip almost always point to the faulting instruction,
> > thus avoiding a mess of "store_current" vs "store_next" in the
> > exception handling. Th
On Wed, 2016-07-27 at 12:04 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:07AM +1000, Benjamin Herrenschmidt
> wrote:
> > Instead, pass GETPC() result to the corresponding helpers. This
> > requires a bit of fiddling to get the PC (hopefully) right in
> > the case where we generate a p
On Wed, 2016-07-27 at 12:00 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:06AM +1000, Benjamin Herrenschmidt
> wrote:
> >
> > We don't implement imprecise FP exceptions and using store_current
> > which sets SRR1 to the *previous* instruction never makes sense
> > for these. So let's
On Wed, 2016-07-27 at 11:57 +1000, David Gibson wrote:
> > -void helper_float_check_status(CPUPPCState *env)
> > +static __attribute__((noinline)) void
> do_float_check_status(CPUPPCState *env,
> > +
> uintptr_t raddr)
>
> Why do you need
On Wed, 2016-07-27 at 11:50 +1000, David Gibson wrote:
>
> > +void raise_exception_err(CPUPPCState *env, uint32_t exception,
> > + uint32_t error_code)
> > +{
> > +raise_exception_err_ra(env, exception, error_code, 0);
> > +}
> > +
> > +void raise_exception(CPUPPCState
So this is fixed upstream, in Fedora and ARCH. Can we expect a fix for
xenial? This is quite a show stopper.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1581936
Title:
Frozen Windows 7 VMs with V
Hello all,
I am running an i386 binary in user mode using qemu.
In the code, I am looking for the next location that the simulated
program counter jumps to when a TranslationBlock completes execution. This
address should be the guest address, not the address on the host.
I found a variable
Hi,
Coalesced mmio buffer is part of vCPU 0's kvm_run mmap'ed area
and with the introduction of CPU hotplug, vCPU 0 can be removed on
PowerPC leading to the below seen segfault in QEMU.
0x100a1d34 in kvm_flush_coalesced_mmio_buffer ()
at qemu/kvm-all.c:1828
1828while (ring
On 2016年07月27日 10:32, Zhang Chen wrote:
Hi~ all~~
Anyone have some comments for this series?
Will have a look at this.
Btw. I wonder how this is tested, do we need a unit test for this?
We need more comments to improve COLO codes.
Thanks
Zhang Chen
On 07/05/2016 06:29 PM, Zhang Chen
On Wed, Jul 27, 2016 at 08:21:20AM +1000, Benjamin Herrenschmidt wrote:
> Use tlb_vaddr_to_host to do a fast path single translate for
> the whole cache line. Also make the reservation check match
> the entire range.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> target-ppc/mem_helper.c | 46
On Wed, Jul 27, 2016 at 08:21:07AM +1000, Benjamin Herrenschmidt wrote:
> Instead, pass GETPC() result to the corresponding helpers. This
> requires a bit of fiddling to get the PC (hopefully) right in
> the case where we generate a program check, though the hacks there
> are temporary, a subsequen
On Wed, Jul 27, 2016 at 08:21:19AM +1000, Benjamin Herrenschmidt wrote:
> We don't need to call a helper for trap always and trap never
> which are used by Linux under some circumstances.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> target-ppc/translate.c | 48 ++
On Wed, Jul 27, 2016 at 08:21:04AM +1000, Benjamin Herrenschmidt wrote:
> Instead of relying on NIP having been updated already.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> target-ppc/fpu_helper.c | 63
> +
> 1 file changed, 38 insertions(+)
On Wed, Jul 27, 2016 at 08:21:26AM +1000, Benjamin Herrenschmidt wrote:
> Use a single translate when not crossing a page boundary and avoid
> going through layers of helpers. MacOS uses those instructions
> a lot, so does OpenBIOS.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> target-ppc/me
On Wed, Jul 27, 2016 at 08:21:10AM +1000, Benjamin Herrenschmidt wrote:
> We make env->nip almost always point to the faulting instruction,
> thus avoiding a mess of "store_current" vs "store_next" in the
> exception handling. The syscall exception knows to move the PC by
> 4 and that's really abou
On Wed, Jul 27, 2016 at 08:20:56AM +1000, Benjamin Herrenschmidt wrote:
> Instead of using the same helpers called from translate.c, let's have
> a bunch of functions that take the various argument combinations,
> especially the retaddr which will be needed in subsequent patches,
> and leave the he
On Wed, Jul 27, 2016 at 08:21:18AM +1000, Benjamin Herrenschmidt wrote:
> The current alignment exception generation tries to load the opcode
> to put in DSISR from a context where a cpu_ldl_code() is really not
> a good idea. It might fault and longjmp out and that's not something
> we want happen
On Wed, Jul 27, 2016 at 08:21:15AM +1000, Benjamin Herrenschmidt wrote:
> This is no longer necessary as the helpers will properly retrieve
> the return address when needed.
Is this right? Don't the tw etc. instructions continue on rather than
retrying if an exception occurs?
>
> Signed-off-by:
On Wed, Jul 27, 2016 at 08:21:06AM +1000, Benjamin Herrenschmidt wrote:
> We don't implement imprecise FP exceptions and using store_current
> which sets SRR1 to the *previous* instruction never makes sense
> for these. So let's be truthful and make them precise, which is
> allowed by the architect
On Wed, Jul 27, 2016 at 08:21:12AM +1000, Benjamin Herrenschmidt wrote:
> This is no longer necessary as the helpers will properly retrieve
> the return address when needed
Well, the helpers are only fixed in this patch IIUC.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> target-ppc/timebas
On Wed, Jul 27, 2016 at 08:20:55AM +1000, Benjamin Herrenschmidt wrote:
> We forgot to do gen_update_nip() for these like we do with other
> helpers. Fix this, but in a more efficient way by passing the RA
> to the accessors instead so the overhead is only taken on faults.
>
> Signed-off-by: Benja
Hi~ all~~
Anyone have some comments for this series?
We need more comments to improve COLO codes.
Thanks
Zhang Chen
On 07/05/2016 06:29 PM, Zhang Chen wrote:
Filter-rewriter is a part of COLO project.
So this patch set depend on colo-compare.
It will rewrite some of secondary packet to mak
Hi Peter,
Thanks for your guidance!
> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Tuesday, July 26, 2016 5:23 PM
> To: 이광우(LEE KWANGWOO) MS SW
> Cc: Xiao Guangrong; Michael S. Tsirkin; Igor Mammedov; Paolo Bonzini; Richard
> Henderson; Eduardo
> Hab
On 07/27/2016 12:25 AM, Max Reitz wrote:
+replication
While some acronyms are written fully in lower case in this file, this
is not an acronym, so I'd capitalize it as "Replication", or maybe call
it "Block replication" instead.
I just know the rule and "Repliation" is good for me.
>+M: Wen
On 07/27/2016 12:22 AM, Max Reitz wrote:
On 26.07.2016 10:15, Changlong Xie wrote:
From: Wen Congyang
Signed-off-by: Wen Congyang
Signed-off-by: Changlong Xie
Signed-off-by: Wang WeiWei
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Reviewed-by: Eric Blake
---
qapi/block-core.json
On 07/27/2016 12:17 AM, Max Reitz wrote:
On 26.07.2016 10:15, Changlong Xie wrote:
From: Wen Congyang
Signed-off-by: Wen Congyang
Signed-off-by: Changlong Xie
Signed-off-by: Wang WeiWei
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/Makefile.objs | 1 +
block/replicati
Save the free page info into a page bitmap, will be used in virtio
balloon device driver.
Signed-off-by: Liang Li
Cc: Andrew Morton
Cc: Vlastimil Babka
Cc: Mel Gorman
Cc: Michael S. Tsirkin
Cc: Paolo Bonzini
Cc: Cornelia Huck
Cc: Amit Shah
---
mm/page_alloc.c | 46
> So I'm fine with this patchset, but I noticed it was not yet reviewed by MM
> people. And that is not surprising since you did not copy memory
> management mailing list on it.
>
> I added linux...@kvack.org Cc on this mail but this might not be enough.
>
> Please repost (e.g. [PATCH v2 repost])
Define a new feature bit which supports a new virtual queue. This
new virtual qeuque is for information exchange between hypervisor
and guest. The VMM hypervisor can make use of this virtual queue
to request the guest do some operations, e.g. drop page cache,
synchronize file system, etc. And the V
will allow faster notifications using a bitmap down the road.
balloon_pfn_to_page() can be removed because it's useless.
Signed-off-by: Liang Li
Signed-off-by: Michael S. Tsirkin
Cc: Paolo Bonzini
Cc: Cornelia Huck
Cc: Amit Shah
---
drivers/virtio/virtio_balloon.c | 22 --
Support the request for vm's free page information, response with
a page bitmap. QEMU can make use of this free page bitmap to speed
up live migration process by skipping process the free pages.
Signed-off-by: Liang Li
Cc: Michael S. Tsirkin
Cc: Andrew Morton
Cc: Vlastimil Babka
Cc: Mel Gorman
Expose the function to get the max pfn, so it can be used in the
virtio-balloon device driver.
Signed-off-by: Liang Li
Cc: Andrew Morton
Cc: Vlastimil Babka
Cc: Mel Gorman
Cc: Michael S. Tsirkin
Cc: Paolo Bonzini
Cc: Cornelia Huck
Cc: Amit Shah
---
mm/page_alloc.c | 6 ++
1 file chang
This patchset is for kernel and contains two parts of change to the
virtio-balloon.
One is the change for speeding up the inflating & deflating process,
the main idea of this optimization is to use bitmap to send the page
information to host instead of the PFNs, to reduce the overhead of
virtio d
The implementation of the current virtio-balloon is not very
efficient, the time spends on different stages of inflating
the balloon to 7GB of a 8GB idle guest:
a. allocating pages (6.5%)
b. sending PFNs to host (68.3%)
c. address translation (6.1%)
d. madvise (19%)
It takes about 4126ms for the
Add a new feature which supports sending the page information with
a bitmap. The current implementation uses PFNs array, which is not
very efficient. Using bitmap can improve the performance of
inflating/deflating significantly
The page bitmap header will used to tell the host some information
abo
On Thu, Jul 21, 2016 at 06:47:56PM +0200, Laurent Vivier wrote:
> As userfaultfd syscall is available on powerpc, migration
> postcopy can be used.
>
> This patch adds the support needed to test this on powerpc,
> instead of using a bootsector to run code to modify memory,
> we use a FORTH script
Under Mac OS X, QEMU's about dialog is not very helpful. It only displays an
icon and the name of the binary. I think this should be improved. Let me know
what you think of this idea:
Version:
Git commit version:
Build date:
Example:
Hi, We've got an unusual use case for our qemu virtual machines.
We're using a qemu-based system to run a bunch of instrumented
test cases. QEMU provides the instrumented execution environment.
Before we start testing we setup the test environment, which includes
booting an operating system as a g
We don't need to call a helper for trap always and trap never
which are used by Linux under some circumstances.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 48 ++--
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/t
Use a single translate when not crossing a page boundary and avoid
going through layers of helpers. MacOS uses those instructions
a lot, so does OpenBIOS.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mem_helper.c | 69 +
1 file changed, 69
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mem_helper.c | 9 +
target-ppc/translate.c | 4
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index e20
Use tlb_vaddr_to_host to do a fast path single translate for
the whole cache line. Also make the reservation check match
the entire range.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mem_helper.c | 46 +-
target-ppc/translate.c | 11 -
Move the NIP update to after the conditional branch so that we
don't do it if we aren't going to take the alignment exception
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc
Some operations aren't allowed in LE mode, use a helper rather than
open coding the exception generation.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate
Just generate an alignment interrupt
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index df9a5bd..3a6de20 100644
--- a/target-ppc/translate.c
+++
Those are always naturally aligned, so cannot cross a page boundary,
thus instead of generating two 8-byte loads with translation on each
(and double swap for LE on LE), we use a helper that will do a single
translation and memcpy the result over (or do appropriate swapping
if needed).
Signed-off-
We were one instruction off
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5288e02..57e9a12 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/tra
The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.
Instead, pass the releavant opcode bits via the error_code.
There ar
We need to pass it to the raise helper since we don't update it
before the calls.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mmu-hash64.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 5de1358
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/excp_helper.c | 6 --
target-ppc/translate.c | 8
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target-ppc/excp_
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mem_helper.c | 11 ++-
target-ppc/translate.c | 6 --
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
in
We make env->nip almost always point to the faulting instruction,
thus avoiding a mess of "store_current" vs "store_next" in the
exception handling. The syscall exception knows to move the PC by
4 and that's really about it.
This actually fixes a number of cases where the translator was
setting en
This is no longer necessary as the helpers will properly retrieve
the return address when needed. Also remove gen_update_current_nip()
which didn't seem to make much sense to me.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 -
target-ppc/misc_helper.c| 9 +---
We don't use it so let's not generate the updates.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 57e9a12..fcff24a 100644
--- a/target-ppc/translate.c
++
This is no longer necessary as the helpers will properly retrieve
the return address when needed
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/timebase_helper.c | 23 +--
target-ppc/translate.c | 12
2 files changed, 13 insertions(+), 22 deletions(-)
We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/excp_helper.c | 11
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mmu_helper.c | 12 ++--
target-ppc/translate.c | 1 -
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target-ppc/mmu_hel
No other change
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/fpu_helper.c | 122
1 file changed, 61 insertions(+), 61 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index d9795d0..e1f600a 100644
--- a/target-p
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 1069 +--
target-ppc/translate/vmx-impl.c | 829 ++
target-ppc/translate/vmx-ops.c | 246 +
3 files changed, 1
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 994 +---
target-ppc/translate/vsx-impl.c | 721 +
target-ppc/translate/vsx-ops.c | 271 +++
3 files changed, 99
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 1205 +---
target-ppc/translate/fp-impl.c | 1098
target-ppc/translate/fp-ops.c | 111
3 files changed, 12
This is no longer necessary as the helpers will properly retrieve
the return address.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate/fp-impl.c | 28
target-ppc/translate/vsx-impl.c | 6 --
2 files changed, 34 deletions(-)
diff --git a/target-pp
1 - 100 of 317 matches
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