On Mon, 07/04 14:40, Paolo Bonzini wrote:
> Now that json-streamer tries not to leak tokens on incomplete parse,
> the tokens can be freed twice if QEMU destroys the json-streamer
> object during the parser->emit call. To fix this, create the new
> empty GQueue earlier, so that it is already in pl
On Tue, Jul 05, 2016 at 03:19:24PM +1000, Sam Bobroff wrote:
> Advertise HTM support in ibm, pa-features if KVM indicates support when
> queried via a new capability (KVM_CAP_PPC_HTM).
>
> If KVM returns false for the capability (which may indicate that the
> host kernel doesn't support the capabi
On Tue, Jul 05, 2016 at 03:19:23PM +1000, Sam Bobroff wrote:
> Signed-off-by: Sam Bobroff
Ok, so the usual procedure for updates to linux-headers is this:
1. Get the change merged on the kernel side
2. Use scripts/update-linux-headers.sh to update the whole
linux-headers subtree to t
On Mon, Jul 04, 2016 at 06:14:41PM +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 21, 2016 at 03:47:33PM +0800, Peter Xu wrote:
> > In ACPI DMA remapping report structure, enable INTR flag when specified.
> >
> > Signed-off-by: Peter Xu
> > ---
> > hw/i386/acpi-build.c | 11 ++-
On Tue, Jul 05, 2016 at 07:49:38AM +0200, Igor Mammedov wrote:
> On Tue, 5 Jul 2016 10:46:07 +0530
> Bharata B Rao wrote:
>
> > On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote:
> > > On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote:
> > > > Consolidates cpu vmstate_[un]r
On Tue, Jul 05, 2016 at 03:19:22PM +1000, Sam Bobroff wrote:
> There are a few issues with our handling of the ibm,pa-features
> HTM bit:
>
> - We don't support transactional memory in PR KVM, so don't tell
> the OS that we do.
>
> - In full emulation we have a minimal implementation of HTM tha
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it
didn't previously do. This means we're now double decoding the page size
because we check it int he fault path after ppc64_hash64_htab_lookup()
returns.
To avoid this duplication have ppc_hash64_pteg_search() and
ppc_hash64_
From: Bharata B Rao
During CPU core realization, we create all the thread objects and parent
them to the core object in a loop. However, the realization of thread
objects is done separately by walking the threads of a core using
object_child_foreach(). With this, there is no guarantee on the orde
On Mon, 4 Jul 2016 16:17:09 -0300
Eduardo Habkost wrote:
> On Fri, Jun 24, 2016 at 06:05:55PM +0200, Igor Mammedov wrote:
> > CPU added with device_add help won't have APIC ID set,
> > so set it according to socket/core/thread ids provided
> > with device_add command.
> >
> > Signed-off-by: Igor
From: Anton Blanchard
xsrdpi, xvrdpi and xvrspi use the round ties away method, not round
nearest even.
Signed-off-by: Anton Blanchard
Signed-off-by: David Gibson
---
target-ppc/fpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/ta
From: Alexey Kardashevskiy
There are going to be multiple IOMMUs per a container. This moves
the single host IOMMU parameter set to a list of VFIOHostDMAWindow.
This should cause no behavioral change and will be used later by
the SPAPR TCE IOMMU v2 which will also add a vfio_host_win_del() helpe
The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3'
into staging (2016-07-04 17:27:54 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/p
On Tue, Jul 05, 2016 at 03:10:34PM +1000, David Gibson wrote:
> The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3'
> into staging (2016-07-04 17:27:54 +0100)
>
&
From: Alexey Kardashevskiy
The sPAPR TCE tables manage 2 copies when VFIO is using an IOMMU -
a guest view of the table and a hardware TCE table. If there is no VFIO
presense in the address space, then just the guest view is used, if
this is the case, it is allocated in the KVM. However since the
On Tue, 5 Jul 2016 10:46:07 +0530
Bharata B Rao wrote:
> On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote:
> > On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote:
> > > Consolidates cpu vmstate_[un]register calls into separate
> > > routines. No functionality change except
Signed-off-by: Sam Bobroff
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index e60e21b..37cb3e8 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -866,6 +866,7 @@ struct kvm_ppc_smmu_
From: Alexey Kardashevskiy
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
The "ddw" property is enabled by default on a PHB but for compatibility
the pseries-2.6 machine and older disable it.
This also creat
ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and
SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field
and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check
all of these bits at once with a suitable ptem value. So, consolidate all
the comp
Advertise HTM support in ibm, pa-features if KVM indicates support when
queried via a new capability (KVM_CAP_PPC_HTM).
If KVM returns false for the capability (which may indicate that the
host kernel doesn't support the capability itself) attempt to
determine availability using a fallback method
From: Benjamin Herrenschmidt
We need to ignore the segment page size and essentially treat
all pages as coming from a 4K segment.
Signed-off-by: Benjamin Herrenschmidt
[dwg: Adjusted for differences in my version of the prereq patches]
Signed-off-by: David Gibson
---
target-ppc/mmu-hash64.c |
From: Alexey Kardashevskiy
This makes use of the new "memory registering" feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this information, the host
kernel can pin them all once per user process, do locked page
On Tue, 2016-07-05 at 15:32 +1000, David Gibson wrote:
> On Tue, Jul 05, 2016 at 03:10:34PM +1000, David Gibson wrote:
> > The following changes since commit
> > 11659423113d2fbcf055085b5e8285d590addfaa:
> >
> > Merge remote-tracking branch 'remotes/kraxel/t
On Tue, 2016-07-05 at 15:10 +1000, David Gibson wrote:
> From: Benjamin Herrenschmidt
>
> We need to ignore the segment page size and essentially treat
> all pages as coming from a 4K segment.
NAK
The arguments are still wrong to ppc_hash64_pteg_search
> Signed-off-by: Benjamin Herrenschmidt
The architecture specifies that when searching a PTEG for PTEs, entries
with a page size encoding that's not valid for the current segment should
be ignored, continuing the search.
The current implementation does this with ppc_hash64_pte_size_decode()
which is a very incomplete implementation of t
From: Alexey Kardashevskiy
New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management.
This adds ability to VFIO common code to dynamically allocate/remove
DMA windows in the host kernel when new VFIO container is added/removed.
This adds a helper to vfio_listener_region_add which m
From: Benjamin Herrenschmidt
This adds proper support for translating real mode addresses based
on the combination of HV and LPCR bits. This handles HRMOR offset
for hypervisor real mode, and both RMA and VRMA modes for guest
real mode. PAPR mode adjusts the offsets appropriately to match the
RMA
From: Alexey Kardashevskiy
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
The "ddw" property is enabled by default on a PHB but for compatibility
the pseries-2.6 machine and older disable it.
This also creat
From: Cédric Le Goater
The segment page shift parameter is never used. Let's remove it.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr_hcall.c| 4 ++--
target-ppc/mmu-hash64.c | 6 +-
target-ppc/mmu-hash64.h | 3 +--
3 files changed, 4 insertions(+), 9 de
On Tue, Jul 05, 2016 at 02:56:53PM +1000, David Gibson wrote:
> On Tue, Jul 05, 2016 at 10:12:49AM +0530, Bharata B Rao wrote:
> > Introduce CPUState.prefer_arch_id_over_cpu_index and
> > MachineClass.prefer_arch_id_over_cpu_index that allow target
> > machines to optionally switch to using arch_id
On Mon, 4 Jul 2016 19:42:07 +0300
"Michael S. Tsirkin" wrote:
> On Mon, Jul 04, 2016 at 06:15:42PM +0200, Igor Mammedov wrote:
> > On Mon, 4 Jul 2016 17:17:51 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Fri, Jun 24, 2016 at 06:05:57PM +0200, Igor Mammedov wrote:
> > > > currently present
From: Benjamin Herrenschmidt
This adds proper support for translating real mode addresses based
on the combination of HV and LPCR bits. This handles HRMOR offset
for hypervisor real mode, and both RMA and VRMA modes for guest
real mode. PAPR mode adjusts the offsets appropriately to match the
RMA
From: Greg Kurz
kvmppc_smt_threads() returns 1 if KVM is not enabled.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 843f19
On Mon, Jul 04, 2016 at 06:17:47PM +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 21, 2016 at 03:47:30PM +0800, Peter Xu wrote:
> > Instead of searching the device tree every time, one static variable is
> > declared for the default system x86 IOMMU device. Also, some VT-d
> > macros are replaced
On Tue, Jul 05, 2016 at 03:12:15PM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2016-07-05 at 15:10 +1000, David Gibson wrote:
> > From: Benjamin Herrenschmidt
> >
> > We need to ignore the segment page size and essentially treat
> > all pages as coming from a 4K segment.
>
> NAK
>
> The argu
From: Alexey Kardashevskiy
This makes use of the new "memory registering" feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this information, the host
kernel can pin them all once per user process, do locked page
On Mon, Jul 04, 2016 at 06:16:08PM +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 21, 2016 at 03:47:30PM +0800, Peter Xu wrote:
> > Instead of searching the device tree every time, one static variable is
> > declared for the default system x86 IOMMU device. Also, some VT-d
> > macros are replaced
Hi David,
Anton asked me to have a look at this, so here is an attempt at a
re-implementation of his: "spapr: Better handling of ibm, pa-features TM bit"
addressing your comments and those from Paul Mackerras. I've broken the
patch into one to unconditionally disable the HTM bit in pa-features a
From: Benjamin Herrenschmidt
We need to ignore the segment page size and essentially treat
all pages as coming from a 4K segment.
Signed-off-by: Benjamin Herrenschmidt
[dwg: Adjusted for differencesin my version of the prereq patches]
Signed-off-by: David Gibson
---
target-ppc/mmu-hash64.c |
There are a few issues with our handling of the ibm,pa-features
HTM bit:
- We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
- In full emulation we have a minimal implementation of HTM that always
fails, so for performance reasons lets not tell the OS that we
On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote:
> On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote:
> > Consolidates cpu vmstate_[un]register calls into separate routines.
> > No functionality change except that vmstate_unregister calls are
> > now done under !CONFIG_USER
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it
didn't previously do. This means we're now double decoding the page size
because we check it int he fault path after ppc64_hash64_htab_lookup()
returns.
To avoid this duplication have ppc_hash64_pteg_search() and
ppc_hash64_
The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3'
into staging (2016-07-04 17:27:54 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/p
From: Alexey Kardashevskiy
New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management.
This adds ability to VFIO common code to dynamically allocate/remove
DMA windows in the host kernel when new VFIO container is added/removed.
This adds a helper to vfio_listener_region_add which m
From: Alexey Kardashevskiy
There are going to be multiple IOMMUs per a container. This moves
the single host IOMMU parameter set to a list of VFIOHostDMAWindow.
This should cause no behavioral change and will be used later by
the SPAPR TCE IOMMU v2 which will also add a vfio_host_win_del() helpe
The architecture specifies that when searching a PTEG for PTEs, entries
with a page size encoding that's not valid for the current segment should
be ignored, continuing the search.
The current implementation does this with ppc_hash64_pte_size_decode()
which is a very incomplete implementation of t
From: Cédric Le Goater
The segment page shift parameter is never used. Let's remove it.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr_hcall.c| 4 ++--
target-ppc/mmu-hash64.c | 6 +-
target-ppc/mmu-hash64.h | 3 +--
3 files changed, 4 insertions(+), 9 de
ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and
SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field
and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check
all of these bits at once with a suitable ptem value. So, consolidate all
the comp
From: Anton Blanchard
xsrdpi, xvrdpi and xvrspi use the round ties away method, not round
nearest even.
Signed-off-by: Anton Blanchard
Signed-off-by: David Gibson
---
target-ppc/fpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/ta
From: Bharata B Rao
During CPU core realization, we create all the thread objects and parent
them to the core object in a loop. However, the realization of thread
objects is done separately by walking the threads of a core using
object_child_foreach(). With this, there is no guarantee on the orde
From: Greg Kurz
kvmppc_smt_threads() returns 1 if KVM is not enabled.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 843f19
From: Alexey Kardashevskiy
The sPAPR TCE tables manage 2 copies when VFIO is using an IOMMU -
a guest view of the table and a hardware TCE table. If there is no VFIO
presense in the address space, then just the guest view is used, if
this is the case, it is allocated in the KVM. However since the
On Tue, Jul 05, 2016 at 10:12:49AM +0530, Bharata B Rao wrote:
> Introduce CPUState.prefer_arch_id_over_cpu_index and
> MachineClass.prefer_arch_id_over_cpu_index that allow target
> machines to optionally switch to using arch_id instead of cpu_index
> as instance_id in vmstate_register(). This wil
On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote:
> Consolidates cpu vmstate_[un]register calls into separate routines.
> No functionality change except that vmstate_unregister calls are
> now done under !CONFIG_USER_ONLY to match with vmstate_register calls.
>
> Signed-off-by: Bharat
On Tue, Jul 05, 2016 at 10:12:51AM +0530, Bharata B Rao wrote:
> xics maintains an array of ICPState structures which is indexed
> by cpu_index. Change this to index the ICPState array by arch_id
> for pseries-2.7 onwards. This allows migration of guest to suceed
> when there are holes in cpu_index
On Tue, Jul 05, 2016 at 10:12:50AM +0530, Bharata B Rao wrote:
> Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
Longer term we should probably change the field name to arch_id. In
theory we could have something like this on a platform that didn't do
device trees.
> ---
> target-ppc/t
On Mon, Jul 04, 2016 at 01:33:02PM +1000, Alexey Kardashevskiy wrote:
> Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
> where devices are allowed to do DMA. These ranges are called DMA windows.
> By default, there is a single DMA window, 1 or 2GB big, mapped at zero
>
xics maintains an array of ICPState structures which is indexed
by cpu_index. Change this to index the ICPState array by arch_id
for pseries-2.7 onwards. This allows migration of guest to suceed
when there are holes in cpu_index range due to CPU hot removal.
Signed-off-by: Bharata B Rao
---
hw/i
Signed-off-by: Bharata B Rao
---
target-ppc/translate_init.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8f257fb..b810624 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10357,6 +10357,1
Introduce CPUState.prefer_arch_id_over_cpu_index and
MachineClass.prefer_arch_id_over_cpu_index that allow target
machines to optionally switch to using arch_id instead of cpu_index
as instance_id in vmstate_register(). This will help allow successful
migration in cases where holes are introduced i
Starting from pseries-2.7, prefer the use of arch_id (cpu_dt_id) over
cpu_index for cpu vmstate registration and in XICS code.
This allows migration to work when CPU cores are not necessarily
unplugged in LIFO order.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 2 ++
hw/ppc/spapr_
device_add/del based CPU hotplug and unplug support is upstream for
sPAPR PowerPC and is under development for x86. Both of these will
support CPU device removal in random order (and not necessarily in LIFO
order). Random order removal will result in holes in cpu_index range
which causes migration
Consolidates cpu vmstate_[un]register calls into separate routines.
No functionality change except that vmstate_unregister calls are
now done under !CONFIG_USER_ONLY to match with vmstate_register calls.
Signed-off-by: Bharata B Rao
---
exec.c | 47 ---
On Mon, Jul 04, 2016 at 06:39:00PM +0300, Michael S. Tsirkin wrote:
> On Fri, Jun 24, 2016 at 05:20:22PM +0800, Peter Xu wrote:
> > On Fri, Jun 24, 2016 at 03:10:21PM +0800, Peter Xu wrote:
> > > When user specify "kernel-irqchip=on", throw error and then quit.
> > >
> > > Signed-off-by: Peter Xu
On Tue, 2016-07-05 at 12:33 +1000, David Gibson wrote:
> Here are 3 fixes and cleanups to the path to look up hashed PTEs and
> decode their page size. This series is functionally equivalent to
> BenH's earlier posted "ppc/hash64: Various fixes in PTE search in the
> hash" but split up for clarity
The architecture specifies that when searching a PTEG for PTEs, entries
with a page size encoding that's not valid for the current segment should
be ignored, continuing the search.
The current implementation does this with ppc_hash64_pte_size_decode()
which is a very incomplete implementation of t
ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and
SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field
and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check
all of these bits at once with a suitable ptem value. So, consolidate all
the comp
Here are 3 fixes and cleanups to the path to look up hashed PTEs and
decode their page size. This series is functionally equivalent to
BenH's earlier posted "ppc/hash64: Various fixes in PTE search in the
hash" but split up for clarity and with some unnnecessary renames removed.
David Gibson (3):
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it
didn't previously do. This means we're now double decoding the page size
because we check it int he fault path after ppc64_hash64_htab_lookup()
returns.
To avoid this duplication have ppc_hash64_pteg_search() and
ppc_hash64_
From: Shannon Zhao
These two are spot by Coverity 1357232 and 1357233.
Signed-off-by: Shannon Zhao
---
hw/block/m25p80.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index d9b2793..ca8c12c 100644
--- a/hw/block/m25p80.c
+++ b/h
On 07/04/2016 07:49 AM, Peter Lieven wrote:
> Hi,
>
> the above commit:
>
> commit d05aa8bb4a8b6aa9a915ec5074fb12ae632d2323
> Author: Eric Blake
> Date: Wed Jun 1 15:10:03 2016 -0600
>
> block: Add .bdrv_co_pwrite_zeroes()
>
> introduces a regression (at least for me).
>
> The Limits fr
On 2016/7/4 20:22, Baptiste Reynal wrote:
On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang
wrote:
For now, we still didn't support live memory snapshot, we have discussed
a scheme which based on userfaultfd long time ago.
You can find the discussion by the follow link:
https://lists.nongnu.org/arc
On 07/04/2016 03:41 AM, Lluís Vilanova wrote:
> Signed-off-by: Lluís Vilanova
> Reviewed-by: Stefan Hajnoczi
> ---
> hmp-commands-info.hx |6 +-
> hmp-commands.hx |7 +-
> monitor.c| 17 +-
> qapi/trace.json | 32 +--
> qmp-commands.hx | 35 ++
W dniu 04.07.2016 o 17:48, Cédric Le Goater pisze:
> On 07/04/2016 05:23 PM, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote:
>>
>>
>> W dniu 04.07.2016 o 15:41, Cédric Le Goater pisze:
>>> On 07/04/2016 02:57 PM, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote:
> -Original Message-
ping
On 2016/7/3 12:00, Zhou Jie wrote:
Hi Alex,
On 2016/6/30 9:45, Zhou Jie wrote:
Hi Alex,
On 2016/6/30 2:22, Alex Williamson wrote:
On Wed, 29 Jun 2016 16:54:05 +0800
Zhou Jie wrote:
Hi Alex,
And yet we have struct pci_dev.broken_intx_masking and we test for
working DisINTx via pci_i
Hi Peter,
On Tuesday, July 5, 2016, Peter Maydell wrote:
> On 2 July 2016 at 19:23, Peter Maydell > wrote:
> > On 2 July 2016 at 17:25, Chanho Park >
> wrote:
> >> I've got a kpartx crash frin qemu-aarch64 user emulation.
> >> The version of qemu-aarch64-static is 2.5.0 and it was also occurred
Hi Peter,
On Tuesday, July 5, 2016, Peter Maydell wrote:
> This patchset fixes a couple of ioctl bugs which were
> causing problems with running kpartx:
> (1) add the missing ioctls for the loop-control device
> (2) fix the BLKSSZGET ioctl not to trash memory on
> 64-bit guests
>
> Peter
On 2016/7/4 23:51, Igor Mammedov wrote:
> Replace repeated pattern
>
> for (i = 0; i < nb_numa_nodes; i++) {
> if (test_bit(idx, numa_info[i].node_cpu)) {
>...
>break;
>
> with a helper function to lookup numa node index for cpu.
>
> Suggested-by: Michael S.
On Mon, Jul 04, 2016 at 05:05:36PM -0300, Eduardo Habkost wrote:
> On Mon, Jul 04, 2016 at 11:02:00PM +0300, Michael S. Tsirkin wrote:
> > On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > The CPU GPs if we try and
On Tue, Jul 05, 2016 at 12:01:49AM +0200, Marc-André Lureau wrote:
> On Mon, Jul 4, 2016 at 5:46 PM, Michael S. Tsirkin wrote:
> > Let's just work on handling it. If we need debug messages to help us
> > reach that goal fine. But I don't see many reasons to propagate
> > return codes back and fort
On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote:
> Hi
>
> On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote:
> > Why does vhost_user_set_log_base need to return error?
> > If backend is not there to handle this message,
> > then it is not changing memory so it's ok to ign
On Sat, Jul 02, 2016 at 08:09:35 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
> > On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote:
> >> From: Sergey Fedorov
> > (snip)
> >> @@ -333,7 +338,7 @@ static inline TranslationBlock *tb_find_fast(CPUState
> >> *cpu,
> >> is
On Fri, Jul 01, 2016 at 17:32:01 -0700, Richard Henderson wrote:
> On 07/01/2016 05:17 PM, Emilio G. Cota wrote:
> >On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote:
> >>From: Sergey Fedorov
> >(snip)
> >>@@ -333,7 +338,7 @@ static inline TranslationBlock *tb_find_fast(CPUState
> >>*cpu,
On Mon, Jul 04, 2016 at 12:45:52 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
> > On Fri, Jul 01, 2016 at 17:16:10 +0100, Alex Bennée wrote:
> >> Lock contention in the hot path of moving between existing patched
> >> TranslationBlocks is the main drag in multithreaded performance. Thi
On Mon, Jul 4, 2016 at 5:46 PM, Michael S. Tsirkin wrote:
> Let's just work on handling it. If we need debug messages to help us
> reach that goal fine. But I don't see many reasons to propagate
> return codes back and forth if caller just prints and ignores it.
> Print it where it's detected :)
Hi
On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote:
> Why does vhost_user_set_log_base need to return error?
> If backend is not there to handle this message,
> then it is not changing memory so it's ok to ignore the error.
How do you know it's not changing the memory?
Furthermore, if
It turned out that this is not a bug but instead I overlooked to add a
channel for qemu-ga via virt-manager. Don't know how it got lost on the
working machine, but nvm, it works now.
Anyone feel free to close this (didn't find an option to do so).
** Changed in: qemu
Status: New => Invalid
On Mon, Jul 04, 2016 at 08:16:09PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Add some sanity checks on the phys-bits setting now that
> the user can set it.
>a) That it's in a sane range (52..32)
>b) Warn if it mismatches the host and isn't the old de
Signed-off-by: Gerd Hoffmann
---
Makefile | 2 +-
src/clock.c | 1 +
src/misc.c | 2 +
src/optionroms.c | 4 +-
src/sercon.c | 545 +++
src/util.h | 3 +
6 files changed, 555 insertions(+), 2 deletions(-)
Signed-off-by: Gerd Hoffmann
---
src/std/cp437.h | 258
1 file changed, 258 insertions(+)
create mode 100644 src/std/cp437.h
diff --git a/src/std/cp437.h b/src/std/cp437.h
new file mode 100644
index 000..fafb864
--- /dev/null
+++ b/sr
Signed-off-by: Gerd Hoffmann
---
src/kbd.c | 17 -
src/util.h | 2 ++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/kbd.c b/src/kbd.c
index 61d9df0..7c43129 100644
--- a/src/kbd.c
+++ b/src/kbd.c
@@ -51,7 +51,7 @@ kbd_init(void)
, x + FIELD_SIZE
Hi,
Next round of patches. Changes:
* Moved it all to a new sercon.c file.
* Code maps cp437 to utf8 now, giving a much nicer display. Compare
"Use the ↑ and ↓ keys to change the selection." (this series) with
"Use the ^ and v keys to change the selection." (sgabios) ;-)
* Simplifie
On Wed, Jun 15, 2016 at 03:21:52PM +0300, David Kiarie wrote:
> Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
> depending on emulated IOMMU.
>
> Signed-off-by: David Kiarie
> ---
> hw/acpi/aml-build.c | 2 +-
> hw/i386/acpi-build.c| 95
> ++
On Mon, Jul 04, 2016 at 08:16:07PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> A special case based on the previous phys-bits property; if it's
> the magic value 0 then use the hosts capabilities.
>
> This becomes the default on new machine types.
>
> Signed-
Hi,
> > void sercon_putchar(char *ptr)
> > {
> > char c = GET_GLOBAL(ptr[0]);
> > [ ... ]
> >
> > ... work?
>
> Yes. See output.c:puts_cs() as an example. It only works if it's a
> constant string (as opposed to a string built on the stack).
After cleaning up the code only three fix
On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> QEMU sets the guests physical address bits to 40; this is wrong
> on most hardware, and can be detected by the guest.
> It also stops you using really huge multi-TB VMs.
>
> Red Hat
On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote:
[...]
> @@ -2084,6 +2085,27 @@ static int kvm_get_msrs(X86CPU *cpu)
> }
>
> assert(ret == cpu->kvm_msr_buf->nmsrs);
> +/*
> + * MTRR masks: Each mask consists of 5 parts
> + * a 10..0: must be zer
Hi,
> I found what I was looking for though - it was in the sgabios
> design.txt file instead of the revision history:
> So, if I read the above correctly, it was lilo that inspired the
> "feature". Anyway, something to keep in mind.
Oh. lilo. Interesting.
I didn't expect http://www.qemu-a
On Mon, Jul 04, 2016 at 11:03:59PM +0300, Michael S. Tsirkin wrote:
> On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > Fill the bits between 51..number-of-physical-address-bits in the
> > MTRR_PHYSMASKn variable range mtrr ma
Hi,
> > Unfortunately, the screen can be larger than 80x25.
>
> It can with SVGA BIOS, but Gerd here only supports mode 3, doesn't he?
Current code yes, but that doesn't imply it'll stay that way forever.
Supporting other sizes is just a matter of making sercon_1000()
recognizing the mode numb
On Mon, Jul 04, 2016 at 11:02:00PM +0300, Michael S. Tsirkin wrote:
> On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > The CPU GPs if we try and set a bit in a variable MTRR mask above
> > the limit of physical address bits o
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