Oh, sorry, also one modification about TILEGX_EXCP_OPCODE_UNIMPLEMENTED
left. I shall send patch v2 for it.
Thanks.
On 10/3/15 16:54, gang.chen.5...@gmail.com wrote:
> From: Chen Gang
>
> For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for
> TILEGX_EXCP_OPCODE_UNIMPLEMENTED.
>
>
On 10/3/15 10:43, gang.chen.5...@gmail.com wrote:
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 6853628..40f9b12 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -990,6 +990,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
> Our intention since the beginning was to protect the host from the
> illegal guest operations. But you do have an interesting point about
> flaws on qemu itself. Perhaps this might be something I could work on to
> improve (start a bigger whitelist and get it tighter before guest
> launches).
Th
> The pull request will be delayed a little bit due to some new patches
> incoming. Let's just set an agreement on how to approach regarding the
> "-runas and -chroot" patch and will prepare just a single batch for pull
> reuqest to Peter.
I also noticed that I had made that patch over the chroot
> If we intend seccomp to protect against flaws during QEMU setup, then having
> it earlier is neccessary. eg QEMU opening a corrupt qcow2 image which might
> exploit QEMU before the guest CPUs start.
> If the latter is the case, then we could start with a relaxed seccomp
> sandbox which included
A future patch will enable error reporting from the various
QAPISchema*.check() methods. But to report an error related
to an implicit type, we'll need to associate a location with
the type (the same location as the top-level entity that is
causing the creation of the implicit type), and once we d
Detect attempts to declare two object members that would result
in the same C member name, by keying the 'seen' dictionary off
of the C name rather than the qapi name. It also requires passing
info through some of the check() methods.
This fixes two previously-broken tests, and the resulting erro
Future commits will migrate semantic checking away from parsing
and over to the various QAPISchema*.check() methods. But to
report an error message about an incorrect semantic use of a
member of an object type, it helps to know which type, command,
or event owns the member. Rather than making all
Right now, simple unions have a quirk of using 'kind' in the C
struct to match the QMP wire name 'type'. This has resulted in
messy clients each doing special cases. While we plan to
eventually rename things to match, it is better in the meantime
to consolidate the quirks into a special subclass,
For simple unions, we were creating the implicit 'type' tag
member during the QAPISchemaObjectTypeVariants constructor.
This is different from every other implicit QAPISchemaEntity
object, which get created by QAPISchema methods. Hoist the
creation to the caller (renaming _make_tag_enum() to
_make
Rename alternate-clash to alternate-clash-members, and add a
new test alternate-clash-type. While similar to the earlier
addition of union-clash-type, we have one major difference: a
future patch will be simplifying alternates to not need an
implict AlternateKind enum, but we still need to detect
A future patch will move some error checking from the parser
to the various QAPISchema*.check() methods, which run only
after parsing completes. It will thus be possible to create
a python instance representing an implicit QAPI type that
parses fine but will fail validation during check(). Since
Pending prerequisite: Markus' qapi-next branch (which has my
subset A patches):
git://repo.or.cz/qemu/armbru.git qapi-next
http://thread.gmane.org/gmane.comp.emulators.qemu/365827/focus=366351
Also available as a tag at this location:
git fetch git://repo.or.cz/qemu/ericb.git qapi-cleanupv7b
and
Similar to the previous commit, move the detection of a collision
in enum values from parse time to QAPISchemaEnumType.check().
This happens to also detect collisions in union branch names,
so for a decent error message, we have to determine if the enum
is implicit (and if so where the real collisi
It should be fairly obvious that qapi base classes need to
form an acyclic graph, since QMP cannot specify the same
key more than once, while base classes are included as flat
members alongside other members added by the child. But the
old check_member_clash() parser function was not prepared to
c
Commit ac88219a had several TODO markers about whether we needed
to automatically create the corresponding array type alongside
any other type. It turns out that most of the time, we don't!
As part of lazy creation of array types, this patch now assigns
an 'info' to array types at their point of
With the previous commit, we have two different locations for
detecting member name clashes - one at parse time, and another
at QAPISchema*.check() time. Consolidate some of the checks
into a single place, which is also in line with our TODO to
eventually move all of the parse time semantic checki
The alternate-good.json test was already covered by
qapi-schema-test.json. As future commits will be tweaking
how alternates are laid out, removing the duplicate test now
reduces churn.
Signed-off-by: Eric Blake
---
v7: new patch
---
tests/Makefile| 1 -
tests/qapi-sch
Previously, qapi-types and qapi-visit filtered out implicit
objects during visit_object_type() by using 'info' (works since
implicit objects do not [yet] have associated info); meanwhile
qapi-introspect filtered out all schema types on the first pass
by returning a python type from visit_begin(), w
The next few patches will start migrating error checking from
ad hoc parse methods into the QAPISchema*.check() methods. But
for an error message to display, we first have to fix the
overall 'try' to catch those errors. We also want to enable a
few more assertions, such as making sure every attem
On Fri, Oct 02, 2015 at 02:07:32PM +0200, Paolo Bonzini wrote:
> On 02/10/2015 13:14, Laszlo Ersek wrote:
> > On 10/02/15 10:34, Paolo Bonzini wrote:
> >> On 01/10/2015 21:17, Laszlo Ersek wrote:
> >>> - In the firmware, allocate an array of bytes, dynamically. This array
> >>> will have no decla
On Sat, Oct 3, 2015 at 5:21 PM, Guenter Roeck wrote:
> On 10/03/2015 02:31 PM, Peter Crosthwaite wrote:
>>
>> Hi,
>>
>> I have done an audit of the ARMv7 boards to see what can boot a
>> vanilla linux kernel. The basic approach is to build ARM
>> multi_v7_defconfig kernel and boot QEMU using the D
On 10/03/2015 02:31 PM, Peter Crosthwaite wrote:
Hi,
I have done an audit of the ARMv7 boards to see what can boot a
vanilla linux kernel. The basic approach is to build ARM
multi_v7_defconfig kernel and boot QEMU using the DTBs built out by
the kernel. The intersection of what mainline Linux ha
From: Gabriel Somlo
Make fw_cfg entries of type "file" available via sysfs. Entries
are listed under /sys/firmware/qemu_fw_cfg/by_key, in folders
named after each entry's selector key. Filename, selector value,
and size read-only attributes are included for each entry. Also,
a "raw" attribute all
From: "Gabriel Somlo"
Allow access to QEMU firmware blobs, passed into the guest VM via
the fw_cfg device, through SysFS entries. Blob meta-data (e.g. name,
size, and fw_cfg key), as well as the raw binary blob data may be
accessed.
The SysFS access location is /sys/firmware/qemu_fw_cfg/... and
From: Gabriel Somlo
Each fw_cfg entry of type "file" has an associated 56-char,
nul-terminated ASCII string which represents its name. While
the fw_cfg device doesn't itself impose any specific naming
convention, QEMU developers have traditionally used path name
semantics (i.e. "etc/acpi/rsdp") t
From: Gabriel Somlo
Instead of blindly probing fw_cfg registers at known IOport and MMIO
locations, use the ACPI subsystem to determine whether a QEMU fw_cfg
device is present, and, if found, to initialize it.
This limits portability to architectures which support ACPI (x86 and
UEFI-enabled aarc
From: Gabriel Somlo
Signed-off-by: Gabriel Somlo
---
lib/kobject.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/kobject.c b/lib/kobject.c
index 3e3a5c3..bea2c9b 100644
--- a/lib/kobject.c
+++ b/lib/kobject.c
@@ -842,6 +842,7 @@ struct kobject *kset_find_obj(struct kset *kset, const c
On Sat, Oct 3, 2015 at 3:14 PM, Peter Crosthwaite
wrote:
> On Sat, Oct 3, 2015 at 2:51 PM, Peter Maydell
> wrote:
>> On 3 October 2015 at 22:31, Peter Crosthwaite
>> wrote:
>>> Hi,
>>> vexpress:
>>>
>>> vexpress boots up to rootfs probing, however the only storage media
>>> that seems to be su
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 44 +---
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c108248..0ec5909 100644
--- a/target-arm/helper.c
From: "Edgar E. Iglesias"
Introduce ARMMMUFaultInfo to propagate MMU Fault information
across the MMU translation code path. This is in preparation for
adding State-2 translation.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c| 32 -
From: "Edgar E. Iglesias"
Add support for applying S2 translation to 64bit S1
page-table walks.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c| 50 --
target-arm/op_helper.c | 4 ++--
2 files changed, 50 insertions(+), 4 deletions(
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/op_helper.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index d4715f4..2ccd1c9 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_hel
From: "Edgar E. Iglesias"
The starting level for S2 pagetable walks is computed
differently from the S1 starting level. Implement the S2
variant.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 39 +++
1 file changed, 27 insertions(+), 12 deletion
From: "Edgar E. Iglesias"
Avoid inline for get_phys_addr() to prepare for future recursive use.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target
From: "Edgar E. Iglesias"
Add support for applying S2 translation to 32bit S1
page-table walks.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f
From: "Edgar E. Iglesias"
Hi,
Another round of patches towards EL2 support. This one adds partial
support for 2-stage MMU. The AArch32/ARMv7 support is untested.
Some of the details of error reporting are intentionally missing, I
was thinking to add those incrementally as they get quite involve
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 12
2 files changed, 13 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cc1578c..895f2c2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -2
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 41 +
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 507324f..610f1b5 100644
--- a/target-arm/helper.c
+++
On Sat, Oct 3, 2015 at 2:51 PM, Peter Maydell wrote:
> On 3 October 2015 at 22:31, Peter Crosthwaite
> wrote:
>> Hi,
>>
>> I have done an audit of the ARMv7 boards to see what can boot a
>> vanilla linux kernel. The basic approach is to build ARM
>> multi_v7_defconfig kernel and boot QEMU using t
On 3 October 2015 at 22:31, Peter Crosthwaite
wrote:
> Hi,
>
> I have done an audit of the ARMv7 boards to see what can boot a
> vanilla linux kernel. The basic approach is to build ARM
> multi_v7_defconfig kernel and boot QEMU using the DTBs built out by
> the kernel. The intersection of what mai
Hi,
I have done an audit of the ARMv7 boards to see what can boot a
vanilla linux kernel. The basic approach is to build ARM
multi_v7_defconfig kernel and boot QEMU using the DTBs built out by
the kernel. The intersection of what mainline Linux has a DTB for and
what QEMU models is tested. The boa
On Thu, Oct 01, 2015 at 05:49:20PM -0700, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Hi,
>
> Another round of patches towards EL2 support. This one adds partial
> support for 2-stage MMU for AArch64. I've marked it RFC because I
> expect a few iterations. Once we can settle on the
On Thu, Oct 01, 2015 at 03:29:50PM +0100, Peter Maydell wrote:
> Gather up all the fields currently in CPUState which deal with the CPU's
> AddressSpace into a separate CPUAddressSpace struct. This paves the way
> for allowing the CPU to know about more than one AddressSpace.
>
> The rearrangement
On 3 October 2015 at 19:04, Peter Crosthwaite
wrote:
> On Thu, Sep 24, 2015 at 5:13 PM, Peter Maydell
> wrote:
>> On 4 September 2015 at 00:13, Pavel Fedin wrote:
>>> Peter Maydell wrote:
Did you report the bug where the pci controller driver
fails to start if the second region is out
On Thu, Sep 24, 2015 at 5:13 PM, Peter Maydell wrote:
> On 4 September 2015 at 00:13, Pavel Fedin wrote:
>> Peter Maydell wrote:
>>> Did you report the bug where the pci controller driver
>>> fails to start if the second region is out of its range
>>> to the kernel mailing list? (It would be nice
On 10/01/2015 10:31 PM, Eric Blake wrote:
> The error message when a simple union or alternate contains a
> branch named 'kind' is ugly, because it is tied to the Schema
> member named 'type'. A future patch will fix the generated C
> to match QMP, but until that point, we can hack things with
> a
24.09.2015 10:18, Stefan Weil wrote:
> Am 24.09.2015 um 09:06 schrieb Markus Armbruster:
>> Ping?
>
>> Markus Armbruster writes:
>
>>> g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also
>>> safer, for two reasons. One, it catches multiplication
>>> overflowing size_t. Two, it retu
24.09.2015 19:18, Markus Armbruster wrote:
> Michael, could you take this one through trivial? Assuming Scott and
> Jiri don't mind, and with s/patchas/patch as/ in the commit message.
>
> Markus Armbruster writes:
>
>> g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
>> fo
23.09.2015 08:27, David Gibson wrote:
> ed173cb ".travis.yml: remove "make check" from main matrix" stopped running
> make check for all the Travis build targets for various reasons. It
> continued to run make check on one Travis build, which builds for a big
> list of all (? nearly all) our suppo
25.09.2015 17:36, Shraddha Barke wrote:
> Compress lines and remove the variable.
Applied to -trivial, removing the Coccinelle script
from the commit message.
Thanks!
/mjt
25.09.2015 17:36, Shraddha Barke wrote:
> Compress lines and remove the variable.
Applied to -trivial, removing the Coccinelle script
from the commit message.
Thanks,
/mjt
Applied to -trivial, thanks!
/mjt
25.09.2015 19:08, Eric Blake wrote:
> On 09/25/2015 08:03 AM, marcandre.lur...@redhat.com wrote:
>> From: Marc-André Lureau
>>
>> ---
>> monitor.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Trivial, can be applied now without waiting for pending qapi patches.
>
> Reviewed-by:
25.09.2015 23:25, Stefan Weil wrote:
> The NSIS installer configuration is maintained by me.
Hopefully this is okay to go to -trivial... ;)
Thanks!
/mjt
25.09.2015 11:37, Shraddha Barke wrote:
> Compress lines and remove the variable.
Applied to -trivial, removing this piece of commit message:
---
> Change made using Coccinelle script
>
> @@
> expression ret;
> @@
> - if (ret) return ret;
> - return 0;
> + return ret;
> @@
> local idexpression r
25.09.2015 11:37, Shraddha Barke wrote:
> Compress lines and remove the variable .
Applied to -trivial, removing this piece of commit message:
---
> Change made using Coccinelle script
>
> @@
> expression ret;
> @@
> - if (ret) return ret;
> - return 0;
> + return ret;
> @@
> local idexpression
25.09.2015 17:42, Christopher Covington wrote:
> This should help clarify the purpose of the function that returns
> the host system's CPU cycle count.
Applied to -trivial, thank you!
/mjt
On Fri, Oct 02, 2015 at 06:18:51PM +0200, Paolo Bonzini wrote:
>
>
> On 24/09/2015 15:20, Michael S. Tsirkin wrote:
> > From: Yuanhan Liu
> >
> > Quote from Michael:
> >
> > We really should rename VHOST_RESET_OWNER to VHOST_RESET_DEVICE.
>
> Where is the corresponding Linux patch for thi
According to comments in /usr/include/linux/eventpoll.h,
poll_event is packed only on x86_64.
And to be sure fields are correctly aligned in epoll_data,
use abi_XXX types for all of them.
Moreover, fd type is wrong: fd is int, not ulong.
This has been tested with a ppc guest on an x86_64 host:
w
20.09.2015 20:48, Peter Crosthwaite пишет:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
05.07.2015 23:26, Peter Crosthwaite пишет:
Hi Dmitry,
Based on my comment earlier, this is what I came up with RE consolidation
of
thos
On 10/03/2015 12:20 AM, Alex Williamson wrote:
On Fri, 2015-10-02 at 17:58 +1000, Alexey Kardashevskiy wrote:
On 09/10/2015 04:34 AM, Alex Williamson wrote:
On Wed, 2015-09-09 at 17:17 +1000, Alexey Kardashevskiy wrote:
On 07/20/2015 12:40 PM, Alexey Kardashevskiy wrote:
On 07/20/2015 03:15 A
From: Chen Gang
For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for
TILEGX_EXCP_OPCODE_UNIMPLEMENTED.
When analyzing issues, the related output is incorrect (e.g. grep UIMP
in the output log for finding qemu tilegx umimplementation issues).
Signed-off-by: Chen Gang
---
target-til
> On 02 Oct 2015, at 21:20, Sair, Umair wrote:
>
>> On linux it always runs on IPv4
>> and on Windows, it always runs on IPv6. Can you please help me out in
>> resolving this problem?
I remember I had the same problem when building GNU ARM Eclipse QEMU.
You can take a look at:
https://githu
If I am understanding correct, you are saying that we should set addr->has_ipv6
and addr->has_ipv4 to true in any case, then in my opinion we should simply
ignore the value of addr->has_ipv* while evaluating the value of ipv4 and ipv6
variables in inet_addr_to_opts (bool ipv4 = addr->ipv4; bool
65 matches
Mail list logo
