On 16 June 2015 at 01:35, Laurent Vivier wrote:
> When executing a 64bit target chroot on 64bit host,
> the ioctl() command can mismatch.
>
> It seems the previous commit doesn't solve the problem in
> my case:
>
> 9c6bf9c7 linux-user: Fix ioctl cmd type mismatch on 64-bit targets
>
> For
On Mon, Jun 15, 2015 at 12:19 PM, Andrea Arcangeli wrote:
>
> Yes, it would leave the other blocked, how is it different from having
> just 1 reader and it gets killed?
Either is completely wrong. But the read() code can at least see that
"I'm returning early due to a signal, so I'll wake up any
MAINTAINERS grew since I posted this patch, copy the new guy.
Markus Armbruster writes:
> Since we now require GLib 2.22+ (commit f40685c), we don't have to
> work around lack of g_hash_table_iter_init() & friends anymore.
>
> This reverts commit f8833a37c0c6b22ddd57b45e48cfb0f97dbd5af4.
>
> Sig
On Tue, 16 Jun 2015 15:40:05 +1000
David Gibson wrote:
> On Mon, Jun 15, 2015 at 10:15:09AM +0200, Thomas Huth wrote:
> > On Mon, 15 Jun 2015 16:59:08 +1000
> > David Gibson wrote:
> >
> > > On Fri, Jun 05, 2015 at 09:55:55AM +0530, Bharata B Rao wrote:
> > > > Factor out bits of sPAPR specific
Ping?
Markus Armbruster writes:
> Since we now require GLib 2.22+ (commit f40685c), we don't have to
> work around lack of g_strcmp0() anymore.
>
> This reverts commit 8f4774789947bc4bc4c8d026a289fe980d3d2ee1.
>
> Conflicts:
> qemu-ga.c
>
> Signed-off-by: Markus Armbruster
> ---
> qga/ma
Ping...
On 05/15/2015 03:51 PM, Wen Congyang wrote:
> If bus_size is less than 0, the command fails.
> If buf_size is 0, use DEFAULT_MIRROR_BUF_SIZE.
> If buf_size % granularity is not 0, mirror_free_init() will
> do dangerous things.
>
> Signed-off-by: Wen Congyang
> Reviewed-by: Fam Zheng
> -
Use cpu_set_pc across the board for setting program counters. This
removes instances of system level code having to reach into the CPU
env.
Signed-off-by: Peter Crosthwaite
---
Changed since v1:
Lease thumb masking in boot.c
---
hw/arm/boot.c | 19 +++
1 file changed, 7 insertion
Use cpu_set_pc for setting program counters when bootloading. This
removes an instance of system level code having to reach into the CPU
env.
Signed-off-by: Peter Crosthwaite
---
hw/microblaze/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/microblaze/boot.c b/hw/mi
Use the cpu_set_pc helper which will take care of CPUClass retrieval
for us.
Signed-off-by: Peter Crosthwaite
---
gdbstub.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 75563db..ceb60ac 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -754,12 +754,
Add a wrapper around the CPUClass::set_pc hook. Accepts an error
pointer to report the case where the hook is not set.
Signed-off-by: Peter Crosthwaite
---
include/qom/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7db
Wrap the CPUClass::set_pc fn hook in a caller helper to reduce
verbosity of calls. Simplify the call from the gdbstub.
Then use the call to abstract away the PC env fields from the ARM and
Microblaze bootloaders.
This moves towards the goal of minimising system level code of the CPU
env (and one
On Mon, Jun 15, 2015 at 10:15:09AM +0200, Thomas Huth wrote:
> On Mon, 15 Jun 2015 16:59:08 +1000
> David Gibson wrote:
>
> > On Fri, Jun 05, 2015 at 09:55:55AM +0530, Bharata B Rao wrote:
> > > Factor out bits of sPAPR specific CPU initialization code into
> > > a separate routine so that it can
Reorganize CPU device tree generation code so that it be reused from
hotplug path. CPU dt entries are now generated from spapr_finalize_fdt()
instead of spapr_create_fdt_skel().
Note: This is how the split-up looks like now:
Boot path
-
spapr_finalize_fdt
spapr_populate_cpus_dt_node
sp
Keep cpu_model field in MachineState uptodate so that it can be used
from the CPU hotplug path.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/mac_newworld.c | 10 +-
hw/ppc/mac_oldworld.c | 7 +++
hw/ppc/ppc440_bamboo.c | 7 +++
hw/ppc/prep.c |
When supporting CPU hot removal by parking the vCPU fd and reusing
it during hotplug again, there can be cases where we try to reenable
KVM_CAP_IRQ_XICS CAP for the vCPU for which it was already enabled.
Introduce a boolean member in ICPState to track this and don't
reenable the CAP if it was alrea
Add CPU_FOREACH_REVERSE that walks CPUs in reverse.
Needed for PowerPC CPU device tree reorganization.
Signed-off-by: Bharata B Rao
Reviewed-by: Andreas Färber
---
include/qom/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 39f0f19..42f42
Use max_cpus instead of smp_cpus when intializating xics system. Also
report max_cpus in ibm,interrupt-server-ranges device tree property of
interrupt controller node.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/s
Factor out bits of sPAPR specific CPU initialization code into
a separate routine so that it can be called from CPU hotplug
path too.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 54 +-
1 file changed, 29 insertions(+), 25 deletions(-)
di
Hi,
This patchset carries the changes that are pre-requisites to support
CPU hotplug for sPAPR guests.
Changes in v5
-
- Fixed indentation issues pointed by Alexey.
- Removed the user of MSR_EP with the understanding that this or an
equivalent define can be used/introduced in a sepa
Add support for ibm,lrdr-capacity since this is needed by the guest
kernel to know about the possible hot-pluggable CPUs and Memory. With
this, pseries kernels will start reporting correct maxcpus in
/sys/devices/system/cpu/possible.
Also define the minimum hotpluggable memory size as 256MB.
Sign
On 06/15/2015 08:12 PM, Thibaut Collet wrote:
> After a resume operation the guest always kicks the backend for each
> virtual queues.
> A live migration does a suspend operation on the old host and a resume
> operation on the new host. So the backend has a kick after migration.
>
> I have checke
Make sure to not modify the branch target. This ensure that the
branch target is not corrupted during partial retranslation.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/s390/tcg-target.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
On 2015/06/15 23:08, Stefan Hajnoczi wrote:
> On Fri, May 29, 2015 at 01:42:26PM +0900, Tetsuya Mukawa wrote:
>>- Change user interface to be able to specify each feature by name.
> I disagree with this change, the uint64_t backend_features option was
> better because:
>
> The text options will
On 2015/06/15 22:58, Stefan Hajnoczi wrote:
> On Fri, May 29, 2015 at 01:42:29PM +0900, Tetsuya Mukawa wrote:
>> The patch enables 'nowait' option for server mode, and 'reconnect'
>> option for client mode.
>>
>> Signed-off-by: Tetsuya Mukawa
>> ---
>> net/vhost-user.c | 6 ++
>> 1 file chang
On 2015/06/15 22:58, Stefan Hajnoczi wrote:
> On Fri, May 29, 2015 at 01:42:30PM +0900, Tetsuya Mukawa wrote:
>> diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
>> index 3af6faf..7fbb306 100644
>> --- a/hw/net/virtio-net.c
>> +++ b/hw/net/virtio-net.c
>> @@ -366,6 +366,17 @@ static int peer_
On 2015/06/15 22:40, Stefan Hajnoczi wrote:
> On Fri, May 29, 2015 at 01:42:28PM +0900, Tetsuya Mukawa wrote:
>> When wrong vhost-user message are passed, the connection should be
>> shutdown.
>>
>> Signed-off-by: Tetsuya Mukawa
>> ---
>> hw/virtio/vhost-user.c | 17 ++---
>> include/
On 2015/06/15 22:32, Stefan Hajnoczi wrote:
> On Fri, May 29, 2015 at 01:42:27PM +0900, Tetsuya Mukawa wrote:
>> Current QEMU cannot detect vhost-user backend disconnection. The
>> patch adds ability to know it.
>> To know disconnection, add watcher to detect G_IO_HUP event. When
>> G_IO_HUP event
On Mon, Jun 15, 2015 at 04:02:14PM +0100, Stefan Hajnoczi wrote:
> Reclaim the dirty bitmap if an incremental backup block job is
> cancelled. The ret variable may be 0 when the job is cancelled so it's
> not enough to check ret < 0.
>
> Reviewed-by: John Snow
> Signed-off-by: Stefan Hajnoczi
>
On Thu, May 28, 2015 at 04:21:43PM +0200, Paolo Bonzini wrote:
> Draining is not necessary, I/O can happen as soon as the
> commit coroutine yields. Draining can be necessary before
> reopening the file for read/write, or while modifying the
> backing file chain, but that is done separately in
> b
On Wed, May 13, 2015 at 11:11:13AM +0800, Fam Zheng wrote:
> Before, we only yield after initializing dirty bitmap, where the QMP
> command would return. That may take very long, and guest IO will be
> blocked.
>
> Add sleep points like the later mirror iterations.
>
> Signed-off-by: Fam Zheng
>
On 06/15/2015 05:44 PM, John Snow wrote:
>> Note that while this returns the desired 16 or 32 bits in the low
>> order side of the result, it does not guarantee that the remaining
>> upper bytes are all 0. I don't know if it matters to callers, or
>> even what real hardware does, but you may want
On 06/15/2015 04:44 PM, Michael S. Tsirkin wrote:
> On Mon, Jun 15, 2015 at 03:43:13PM +0800, Jason Wang wrote:
>>
>> On 06/12/2015 10:28 PM, Michael S. Tsirkin wrote:
>>> On Fri, Jun 12, 2015 at 03:55:33PM +0800, Jason Wang wrote:
On 06/11/2015 08:13 PM, Michael S. Tsirkin wrote:
> On T
Implement support for TPM on ppc64 by implementing the vTPM CRQ
interface (following PAPR) as a frontend.
Have the frontend call the existing passthrough TPM device backend
using data structures from the TPM TIS hardware interface emulation
(tpm_tis.c). The TIS implements a superset of functionali
Compile the TPM passthrough device emulation on ppc64.
Signed-off-by: Stefan Berger
---
configure | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 409edf9..d260057 100755
--- a/configure
+++ b/configure
@@ -3029,7 +3029,8 @@ fi
#
Remove the direct TPMState usage from the TPM backend. This allows different
frontends to use the backend. A few more parameters now need to be passed to the
backend.
Other frontends may need different TPMState structures if for example
the device types they are using are not always visible during
The following series of patches adds TPM support for ppc64.
The CUSE TPM backend, which is part of the TPM passthrough backend,
should be considered for providing a private vTPM to a VM. The
series implementing support for this has recently been posted here:
http://lists.nongnu.org/archive/html/q
On Mon, Jun 15, 2015 at 6:16 PM, Alistair Francis
wrote:
> Originally the pvr-full PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis
> ---
> V3:
> - Convert PVR to an 8-bit ui
From: "Edgar E. Iglesias"
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f822ea0..76f4611 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -407,6 +407,10 @@ static void c
From: "Edgar E. Iglesias"
Replace magic constants with macros from
hw/arm/virt.h and hw/intc/arm_gic_common.h.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/virt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 3 ++-
target-arm/helper.c | 68
4 files changed, 73 insertions(+), 1 deletion(-)
diff --git a
From: "Edgar E. Iglesias"
Prepare for adding the Hypervisor timer, no functional change.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 98 +
1 file changed, 76 insertions(+), 22 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Adds control for trapping selected timer and counter accesses to EL2.
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 34 --
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-a
From: "Edgar E. Iglesias"
Adds support for the virtual timer offset controlled by EL2.
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 47 +--
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/targ
From: "Edgar E. Iglesias"
Hi,
This is what is left of round 3 of our series towards support for EL2 for
AArch64.
Comments welcome!
Best regards,
Edgar
v4 -> v5:
* Fix timer compare logic
* Fix cval reads
* Fix CNTHCTL exception priority
* Comment on CNTHCTL reset value
* Added AArch32 HYP tim
On 2015/6/16 2:13, Michael S. Tsirkin wrote:
> On Mon, Jun 15, 2015 at 05:59:06PM +0100, Peter Maydell wrote:
>> On 15 June 2015 at 17:32, Andrew Jones wrote:
>>> On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrot
Hi Andrew,
On 2015/6/16 2:09, Andrew Jones wrote:
> On Fri, Jun 12, 2015 at 06:21:35PM +0200, Igor Mammedov wrote:
>> On Fri, 12 Jun 2015 15:55:22 +0100
>> Peter Maydell wrote:
>>
>>> On 1 June 2015 at 11:15, wrote:
From: Shannon Zhao
Add GICv2m description in ACPI MADT table, s
This code is already being run in the mb_cpu_realizefn()
function. As PVR registers are preserved on reset this
code is not required.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Crosthwaite
---
target-microblaze/cpu.c |4
1 files changed, 0 insert
Move the hard coded register values to the init function.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
The hardcoded PVR0 values can be removed as they are setting
the endianness and stack protection, which is already done
or invalid.
Sign
Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
---
V3:
- Convert PVR to an 8-bit uint instead of a bool
V2:
- Rename DTS mapping
target-microblaze/cpu-qo
Remove the hardcoded values from the machine specific reset
function, as the same values are already set in the standard
MicroBlaze reset.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E.
Originally the endi PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Crosthwaite
---
hw/microblaze/petalogix_ml605_mmu.c |2 +-
Rename the usefpu variable to use_fpu.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
target-microblaze/cpu-qom.h |2 +-
target-microblaze/cpu.c |8
target-microblaze/translate.c |6 +++---
3 files changed, 8 insertions(+), 8 deletions(-)
diff -
This patch series extends the MicroBlaze properties
that I have been working on. It applies on top of my
original work:
'Add Microblaze configuration options'.
This patch series converts various MicroBlaze PVR registers
to properties. This then allows the individual Microblaze
machine reset functi
On Mon, Jun 15, 2015 at 12:34 AM, Peter Maydell
wrote:
> On 15 June 2015 at 03:21, Peter Crosthwaite
> wrote:
>> Move the ARM coprocessor API to a new C file. helper.c is huge and
>> splitting off this self contained piece increases modularity.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> I
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 06/15/2015 07:28 PM, Eric Blake wrote:
> On 06/15/2015 05:09 PM, John Snow wrote:
>
>>>
This wrapper will support aligned 8 byte reads, but will
make no effort to support unaligned 8 byte reads, which
although they will work on
On 06/15/2015 05:09 PM, John Snow wrote:
>>
>>> This wrapper will support aligned 8 byte reads, but will make
>>> no effort to support unaligned 8 byte reads, which although they
>>> will work on real hardware, are not guaranteed to work and do
>>> not appear to be used by either Windows or Linux.
On 06/15/2015 06:55 PM, Eric Blake wrote:
> On 06/15/2015 04:22 PM, John Snow wrote:
>> The only guidance the AHCI specification gives on memory access is:
>> "Register accesses shall have a maximum size of 64-bits; 64-bit access
>> must not cross an 8-byte alignment boundary."
>>
>> In practice,
On 06/15/2015 04:22 PM, John Snow wrote:
> The only guidance the AHCI specification gives on memory access is:
> "Register accesses shall have a maximum size of 64-bits; 64-bit access
> must not cross an 8-byte alignment boundary."
>
> In practice, a real Q35/ICH9 responds to 1, 2, 4 and 8 byte re
On 06/15/2015 04:35 PM, Laurent Vivier wrote:
> When executing a 64bit target chroot on 64bit host,
> the ioctl() command can mismatch.
>
>
> The origin of the problem is in syscall.c:do_ioctl().
>
> static abi_long do_ioctl(int fd, abi_long cmd, abi_long arg)
It's annoying that Linux pi
On Mon, Jun 15, 2015 at 12:36 AM, Peter Maydell
wrote:
> On 15 June 2015 at 04:48, Peter Crosthwaite
> wrote:
>> ARM program counters are always at least 16b aligned with the LSB
>> being only used the indicate thumb mode in exchange situations. Mask
>> this bit off in set_pc to ignore the excha
When executing a 64bit target chroot on 64bit host,
the ioctl() command can mismatch.
It seems the previous commit doesn't solve the problem in
my case:
9c6bf9c7 linux-user: Fix ioctl cmd type mismatch on 64-bit targets
For example, a ppc64 chroot on an x86_64 host:
bash-4.3# ls
Unsuppo
Test that we can survive a couple of cycles of running a basic identify
test, some IO, and resetting the HBA. Ensures that we can bring the HBA
back to compliant spec during the lifecycle of the VM.
Signed-off-by: John Snow
---
tests/ahci-test.c | 24
1 file changed, 24
The only guidance the AHCI specification gives on memory access is:
"Register accesses shall have a maximum size of 64-bits; 64-bit access
must not cross an 8-byte alignment boundary."
In practice, a real Q35/ICH9 responds to 1, 2, 4 and 8 byte reads
regardless of alignment. Windows 7 can also be
This is a small handful of fixes for the ahci-tests/ahci device,
alongside two new tests. I have a larger series of NCQ patches
coming shortly, but these patches were unrelated so I cleaned them
up and am sending them out separately.
_
Test that the FIS delivered after a nondata command has appropriately
updated registers, just as we'd expect a data command to do.
Signed-off-by: John Snow
---
tests/ahci-test.c | 50 +-
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git
There's a handful of trivial bugs in the libqos/ahci functions,
squish them together.
- Zero cached pointers after freeing them
- The Command List Buffer is an array of 32x 32 byte structures, not
32x 8 byte pointers -- it's 1MiB, not 256 bytes. Zero it ALL.
- Free the correct command in ahci_pi
On Mon, Jun 15, 2015 at 08:19:07AM -1000, Linus Torvalds wrote:
> What if the process doing the polling never doors anything with the end
> result? Maybe it meant to, but it got killed before it could? Are you going
> to leave everybody else blocked, even though there are pending events?
Yes, it w
On Jun 15, 2015 11:43 AM, "Andrea Arcangeli" wrote:
>
> Several times I got very hardly reproducible bugs noticed purely
> because of BUG_ON (not VM_BUG_ON)
Feel free to use them while developing. Don't send me patches with your
broken debug code, though.
For users, a dead machine means that it
On Mon, Jun 15, 2015 at 08:11:50AM -1000, Linus Torvalds wrote:
> On Jun 15, 2015 7:22 AM, "Andrea Arcangeli" wrote:
> >
> > + if (cmd != UFFDIO_API) {
> > + if (ctx->state == UFFD_STATE_WAIT_API)
> > + return -EINVAL;
> > + BUG_ON(ctx->state
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> In particular, don't include it into headers.
>
> Signed-off-by: Markus Armbruster
> ---
> 29 files changed, 4 insertions(+), 29 deletions(-)
Again, it might be nice to call out in the commit message how you
determined which files could drop i
On Mon, Jun 15, 2015 at 8:49 AM, Peter Maydell wrote:
> On 15 June 2015 at 16:36, Alex Züpke wrote:
>> So this is the way to go:
>>
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -4084,6 +4084,7 @@ static void gen_nop_hint(DisasContext *s, int val)
>> gen_set_pc_im
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> In particular, don't include it into headers.
>
> Signed-off-by: Markus Armbruster
> ---
> 46 files changed, 25 insertions(+), 21 deletions(-)
Assuming this was done by deleting from headers, then adding it into .c
files that no longer compile
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> 57 files changed, 59 insertions(+), 3 deletions(-)
>
> diff --git a/include/qapi/qmp/qerror.h b/include/qapi/qmp/qerror.h
> index f8182c7..842b27a 100644
> --- a/include/qapi/qmp/qerror.h
> +++ b/includ
Hi,
We were confused with the behavior of interrupt distribution across CPUs in
Qemu guest VM.
We were using Qemu-kvm 1.1.2 and OSes of the both guest and host were
CentOS 6.5. We found that the interrupts were evenly distributed as long as
the number of CPU cores were no more than 8. Otherwise,
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> Remove it except for two things in qerror.h:
>
> * Two #include to be cleaned up separately to avoid cluttering this
> patch.
>
> * The QERR_ macros. Mark as obsolete.
>
> Signed-off-by: Markus Armbruster
> ---
> block/qapi.c
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> The traditional QMP command handler interface
>
> int qmp_FOO(Monitor *mon, const QDict *params, QObject **ret_data);
>
> doesn't provide for returning an Error object. Instead, the handler
> is expected to stash it in the monitor with qerro
Hi Aurelien,
Le 12/06/2015 01:30, Aurelien Jarno a écrit :
On 2015-06-11 22:30, Hervé Poussineau wrote:
This workarounds a bug in memory management.
To reproduce the problem, try to start the Windows NT 4.0/MIPS installer.
After loading some files, you should see a screen saying
"To set up Win
On 15 June 2015 at 16:18, Luiz Capitulino wrote:
> On Sat, 13 Jun 2015 16:20:51 +0200
> Markus Armbruster wrote:
>
>> Error classes other than ERROR_CLASS_GENERIC_ERROR should not be used
>> in new code. Hiding them in QERR_ macros makes new uses hard to spot.
>> Fortunately, there's just one su
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> qerror_report() is a transitional interface to help with converting
> existing monitor commands to QMP. It should not be used elsewhere.
> Replace by error_report().
>
> Signed-off-by: Markus Armbruster
> ---
> tpm.c | 10 --
> 1 file c
On 06/15/2015 09:18 AM, Luiz Capitulino wrote:
> On Sat, 13 Jun 2015 16:20:51 +0200
> Markus Armbruster wrote:
>
>> Error classes other than ERROR_CLASS_GENERIC_ERROR should not be used
>> in new code. Hiding them in QERR_ macros makes new uses hard to spot.
>> Fortunately, there's just one such
This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
the main differences being the DSP instructions and an optional FPU.
Created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible
CPU that uses DSP instructions, and manually added it to the M4 in its initfn.
Am 15.06.2015 um 20:58 schrieb Peter Maydell:
On 15 June 2015 at 16:05, Alex Züpke wrote:
Am 15.06.2015 um 16:51 schrieb Peter Maydell:
On 15 June 2015 at 15:44, Alex Züpke wrote:
Am 12.06.2015 um 20:03 schrieb Peter Maydell:
Probably the best approach would be to have something in
arm_cpu_
On 15 June 2015 at 16:05, Alex Züpke wrote:
> Am 15.06.2015 um 16:51 schrieb Peter Maydell:
>> On 15 June 2015 at 15:44, Alex Züpke wrote:
>>> Am 12.06.2015 um 20:03 schrieb Peter Maydell:
Probably the best approach would be to have something in
arm_cpu_set_irq() which says "if we are C
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), an
This patchset makes the ARM and Thumb encodings of the YIELD hint
instruction in the ARM cause the TCG CPU to yield control back
to the top level loop. This brings them into line with the A64
encoding which already did this.
Patch 1 splits out DISAS_YIELD from DISAS_WFE, because although
we curren
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a
Document the behavior of fw_cfg_modify_iXX() for leak-less updating
of integer-type blobs.
Currently only fw_cfg_modify_i16() is coded, but 32- and 64-bit versions
may be added later if necessary..
Signed-off-by: Gabriel Somlo
---
docs/specs/fw_cfg.txt | 11 +++
1 file changed, 11 inser
On 15 June 2015 at 16:05, Alex Züpke wrote:
> Here's a simple IPI tester sending IPIs from CPU #0 to CPU #1 in an endless
> loop.
> The IPIs are delayed until the timer interrupt triggers the main loop.
>
> http://www.cs.hs-rm.de/~zuepke/qemu/ipi.elf
> 3174 bytes, md5sum 8d73890a60cd9b24a4f913950
Am 15.06.2015 um 17:57 schrieb Aurelien Jarno:
> The I/O-Interruption Subclass field corresponds to bits 2 to 5 (BE
> notation) of the Interruption-Identification Word. The value should
> be shift by 27 instead of 24.
>
> Cc: Christian Borntraeger
> Cc: Cornelia Huck
> Cc: Alexander Graf
> Sign
On Mon, 2015-06-15 at 17:45 +, Yehuda Yitschak wrote:
>
> From: Alex Williamson
> Sent: Monday, June 15, 2015 8:15 PM
> To: Yehuda Yitschak
> Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a gu
On Mon, Jun 15, 2015 at 05:59:06PM +0100, Peter Maydell wrote:
> On 15 June 2015 at 17:32, Andrew Jones wrote:
> > On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
> >> On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
> >> > I'm still confused about when fields in
On Jun 15, 2015 7:22 AM, "Andrea Arcangeli" wrote:
>
> Blocking reads can easily use exclusive wakeups. Poll in theory could
> too but there's no poll_wait_exclusive in common code yet.
NAK.
Tie while commit message is crap, and so us the comment
No, your really cannot "easily use exclusive wai
On Jun 15, 2015 7:22 AM, "Andrea Arcangeli" wrote:
>
> + if (cmd != UFFDIO_API) {
> + if (ctx->state == UFFD_STATE_WAIT_API)
> + return -EINVAL;
> + BUG_ON(ctx->state != UFFD_STATE_RUNNING);
> + }
NAK.
Once again: we don't add BUG_ON(
On Fri, Jun 12, 2015 at 06:21:35PM +0200, Igor Mammedov wrote:
> On Fri, 12 Jun 2015 15:55:22 +0100
> Peter Maydell wrote:
>
> > On 1 June 2015 at 11:15, wrote:
> > > From: Shannon Zhao
> > >
> > > Add GICv2m description in ACPI MADT table, so guest can use MSI when
> > > booting with ACPI.
>
On 06/15/2015 07:45 PM, Yehuda Yitschak wrote:
>
>
> From: Alex Williamson
> Sent: Monday, June 15, 2015 8:15 PM
> To: Yehuda Yitschak
> Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a guest VM
>
According to PAPR+ 3.2.2.2, the TCE is implemented as follows:
bits 0-51: real page number
bits 52-61: reserved for future use
bits 62-63: page protection (read-only, write-only, read-write)
Possible values for the protection bits are necessarly non-zero and thus
H_PUT_TCE
From: Alex Williamson
Sent: Monday, June 15, 2015 8:15 PM
To: Yehuda Yitschak
Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
Subject: Re: Assigning an eth port to a guest VM
On Mon, 2015-06-15 at 16:52 +, Yehuda Yitschak wrote:
>>
fimd_swap_data() includes code to reverse the bits in a
64-bit integer, but an off-by-one error meant that it would
try to shift off the top of the integer. Correct the bug
(spotted by Coverity).
Signed-off-by: Peter Maydell
Message-id: 1432912615-23107-1-git-send-email-peter.mayd...@linaro.org
-
From: Shannon Zhao
Add cortex-a53 cpu support in machine virt, so it can be used for TCG
and KVM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Peter Maydell
Message-id: 1433207452-4512-3-git-send-email-shannon.z...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/v
From: "Aurelio C. Remonda"
Create an ARM_FEATURE_THUMB_DSP controlling the Thumb encodings of
the 85 DSP instructions (these are all Thumb2). This is enabled for
all non-M-profile CPUs with Thumb2 support, as the instructions are
mandatory for R and A profiles. On M profile they are optional and
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