On Mon, Jun 15, 2015 at 6:16 PM, Alistair Francis
<alistair.fran...@xilinx.com> wrote:
> Originally the pvr-full PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
> ---
> V3:
> - Convert PVR to an 8-bit uint instead of a bool
> V2:
> - Rename DTS mapping
>
> target-microblaze/cpu-qom.h | 1 +
> target-microblaze/cpu.c | 7 ++++---
> target-microblaze/helper.c | 4 ++--
> 3 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 7da25fa..34f6273 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
> bool dcache_writeback;
> bool endi;
> char *version;
> + uint8_t pvr;
> } cfg;
>
> CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index df3dd89..b1ffa8e 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
>
> qemu_init_vcpu(cs);
>
> - env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
> - | PVR0_USE_BARREL_MASK \
> + env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
> | PVR0_USE_DIV_MASK \
> | PVR0_USE_HW_MUL_MASK \
> | PVR0_USE_EXC_MASK \
> @@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
> (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
> (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
> (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
> - (version_code << 16);
> + (version_code << 16) |
> + (cpu->cfg.pvr == 2 ? PVR0_PVR_FULL_MASK : 0);
>
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -228,6 +228,7 @@ static Property mb_properties[] = {
> false),
> DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> + DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, 2),
The encodings should be macroified:
#define C_PVR_NONE = 0;
#define C_PVR_BASIC = 1;
#define C_PVR_FULL = 2;
Otherwise,
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 5156c12..fa783ff 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw,
> mmu_available = 0;
> if (cpu->cfg.use_mmu) {
> mmu_available = 1;
> - if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
> - && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
> + if ((cpu->cfg.pvr == 2) &&
> + (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
> mmu_available = 0;
> }
> }
> --
> 1.7.1
>
>
