From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi,
This is what is left of round 3 of our series towards support for EL2 for AArch64. Comments welcome! Best regards, Edgar v4 -> v5: * Fix timer compare logic * Fix cval reads * Fix CNTHCTL exception priority * Comment on CNTHCTL reset value * Added AArch32 HYP timer regs * Reorder HYP timer regs * Use CP_CONST for RES0 HYP timer regs (EL3 but no EL2) v3 -> v4: * Add comment clarifing the unsigned/signed timer hit arithmetics * Replace GIC magic constants with macros * Slightly expanded commit messages v2 -> v3: * Use CP_ACCESS_TRAP_EL2 instead of setting target_el v1 -> v2: * Drop PAR_EL1 * Add AArch32 mappings of MAIR_EL2 * Add AArch32 mappings of TCR_EL2 * Add AArch32 mappings of SCTLR_EL2 * Add AArch32 mappings of TTBR0_EL2 * Add AArch32 mappings of TPIDR_EL2 * Add AArch32 mappings of CNTHCTL_EL2 * Add AArch32 mappings of CNTVOFF_EL2 * Tag CNTVOFF_EL2 and CNTVOFF as ARM_CP_IO * Rename TLIBALLE2 -> TLBI_ALLE2 * Break down TLB_LOCKDOWN to v7 level Edgar E. Iglesias (6): target-arm: Add CNTVOFF_EL2 target-arm: Add CNTHCTL_EL2 target-arm: Pass timeridx as argument to various timer functions target-arm: Add the Hypervisor timer hw/arm/virt: Replace magic IRQ constants with macros hw/arm/virt: Connect the Hypervisor timer hw/arm/virt.c | 13 ++- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 + target-arm/cpu.h | 5 +- target-arm/helper.c | 245 +++++++++++++++++++++++++++++++++++++++++++++------ 5 files changed, 233 insertions(+), 33 deletions(-) -- 1.9.1
