From: Shannon Zhao
valgrind complains about:
==9276== 13 bytes in 1 blocks are definitely lost in loss record 1,046 of 3,673
==9276==at 0x4C2845D: malloc (in
/usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so)
==9276==by 0x2EAFBB: malloc_and_trace (vl.c:2556)
==9276==by 0x64C770E:
All of the core-code usages of this API have the cpu pointer handy so
pass it in. There are only 3 architecture specific usages (2 of which
are commented out) which can just use ENV_GET_CPU locally to get the
cpu pointer. The reduces core code usage of the CPU env, which brings
us closer to common-
The callers (most of them in target-foo/cpu.c) to this function all
have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU from
core code (in exec.c).
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Peter Maydell
Cc: "Edgar E. Iglesias"
Cc: "Andreas Färber"
Cc: Eduardo Habkost
Cc: Mich
The sole caller of this function navigates the cpu->env_ptr only for
this function to take it back the cpu pointer straight away. Pass in
cpu pointer instead and grab the env pointer locally in the function.
Removes a core code usage of ENV_GET_CPU.
Signed-off-by: Peter Crosthwaite
---
cpus.c |
Hi Andreas, Richard and all,
I'm moving towards the goal of having no core code usages of ENV_GET_CPU.
This has two advantages:
1: It means we are closer to common-obj'ing core code like exec.c, cpus.c
and friends.
2: Multi arch is easier if ENV_GET_CPU stays arch specific. It means I
don't need
All callsites to this function navigate the cpu->env_ptr only for the
function to take the env ptr back to the original cpu ptr. Change the
function to just pass in the CPU pointer instead. Removes a core code
usage of ENV_GET_CPU (in gdbstub.c).
Cc: Riku Voipio
Signed-off-by: Peter Crosthwaite
2015-05-23 6:55 GMT+03:00 Kevin O'Connor :
> Out of curiosity, I ran some additional timing tests. With SeaBIOS
> fully stripped down (via Kconfig), it takes ~20ms to get to the boot
> phase on my old AMD system. Of that 20ms, ~7ms is to enable shadow
> ram, 2ms is to calibrate the cpu timestamp
On Sun, May 24, 2015 at 9:58 PM, Edgar E. Iglesias
wrote:
> On Sun, May 24, 2015 at 08:31:40PM -0700, Peter Crosthwaite wrote:
>> Instantiate and realise the CPU directly, rather than using
>> cpu_mb_init. Microblazes cpu_model argument is a dummy so remove the
>> default cpu_model set logic.
>
>
On Sun, May 24, 2015 at 08:31:40PM -0700, Peter Crosthwaite wrote:
> Instantiate and realise the CPU directly, rather than using
> cpu_mb_init. Microblazes cpu_model argument is a dummy so remove the
> default cpu_model set logic.
Reviewed-by: Edgar E. Iglesias
I've put this in my mb queue.
BTW,
Alexey Kardashevskiy writes:
> On 05/19/2015 06:26 PM, Nikunj A Dadhania wrote:
>> Each hardware instance has a platform unique location code. The OF
>> device tree that describes a part of a hardware entity must include
>> the “ibm,loc-code” property with a value that represents the location
>>
Alexey Kardashevskiy writes:
> On 05/19/2015 06:26 PM, Nikunj A Dadhania wrote:
>> All the PCI enumeration and device node creation was off-loaded to
>> SLOF. With PCI hotplug support, code needed to be added to add device
>> node. This creates multiple copy of the code one in SLOF and other in
>
On Mon, May 18, 2015 at 4:14 PM, Alistair Francis
wrote:
> Originally the use-fpu PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis
> ---
> Changes since RFC:
> - Tidy up the
On Mon, May 18, 2015 at 4:14 PM, Alistair Francis
wrote:
> Rename the "xlnx.base-vectors" string to "base-vectors" and
> move the base_vectors variable into the cfg struct.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
> ---
>
> target-microblaze/cpu-qom.h |3 ++-
> t
On Mon, May 18, 2015 at 4:13 PM, Alistair Francis
wrote:
> Microblaze stack protection is configurable and isn't always enabled.
> This patch allows the stack protection to be disabled from the CPU
> properties.
>
> Signed-off-by: Alistair Francis
> ---
> Changes since RFC:
> - Move the cfg.stac
On Mon, May 18, 2015 at 4:13 PM, Alistair Francis
wrote:
> Move the Microblaze PVR registers to the end of the CPUMBState
> and preserve them during reset. This is similar to what the
> QEMU ARM model does with some of it's registers.
>
> This allows the Microblaze PVR registers to only be set onc
On Tue, 05/19 15:54, Stefan Hajnoczi wrote:
> On Tue, May 19, 2015 at 10:51:01AM +, Fam Zheng wrote:
> > This callback is called by main loop before polling s->fd, if it returns
> > false, the fd will not be polled in this iteration.
> >
> > This is redundant with checks inside read callback.
On Mon, May 18, 2015 at 4:12 PM, Alistair Francis
wrote:
> Fix up the incorrect indentation level in the helper_stackprot() function.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
> ---
>
> target-microblaze/op_helper.c | 10 +-
> 1 files changed, 5 insertions(+
Instantiate and realise the CPU directly, rather than using
cpu_mb_init. Microblazes cpu_model argument is a dummy so remove the
default cpu_model set logic.
Signed-off-by: Peter Crosthwaite
---
hw/microblaze/petalogix_s3adsp1800_mmu.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-
The tests for device type "ide_cd" should only be tested for the pc
platform.
The default device id of hard disk on the s390 platform differs to that
of the x86 platform. A new variable device_id is defined and "virtio0"
set for the s390 platform. A x86 platform specific output file is also
needed.
when creating an image qemu-img enable us specifying the size of the
image using -o size=xx options. But when we specify an invalid size
such as a negtive size then different platform gives different result.
parse_option_size() function in util/qemu-option.c will be called to
parse the size, a cas
From: Xiao Guang Chen
There is no 'ide-cd' device defined on s390 platform, so
test_medium_not_found() test should be skipped.
Reviewed-by: Max Reitz
Reviewed-by: Michael Mueller
Signed-off-by: Xiao Guang Chen
---
tests/qemu-iotests/055 | 9 +
1 file changed, 9 insertions(+)
diff --
The default device id of hard disk on the s390 platform is "virtio0"
which differs to the "ide0-hd0" for the x86 platform. Setting id in
the drive definition, ie:"qemu -drive id=testdisk", will be the same
on all platforms.
Reviewed-by: Max Reitz
Signed-off-by: Bo Tu
---
tests/qemu-iotests/130
From: Xiao Guang Chen
This patch fixes an io test suite issue that was introduced with the
commit c88930a6866e74953e931ae749781e98e486e5c8 'qemu-char: Permit only
a single "stdio" character device'. The option supresses the creation of
default devices such as the floopy and cdrom. Output files fo
From: Xiao Guang Chen
There is no 'ide-cd' device defined on s390 platform, so
test_medium_not_found() test should be skipped.
Reviewed-by: Max Reitz
Reviewed-by: Michael Mueller
Signed-off-by: Xiao Guang Chen
---
tests/qemu-iotests/041 | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Xiao Guang Chen
This patch adds qemu machine type support to the io test suite.
Based on the qemu default machine type and alias of the default machine type
the reference output file can now vary from the default to a machine specific
output file if necessary. When using a machine specific
v9.
1.Fix issue of line over 80 characters for test 049
2.Add Reviewed-by statements for test 051,130
3.Please apply the series if there are no further objections
v8.
1.Modify error message in qemu-option.c when image size is invalid
2.Remove Reviewed-by statements if any functional changes in a n
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index ebce504..5
From: Shannon Zhao
Initialize VirtGuestInfoState and register a machine_init_done notify to
call virt_acpi_build().
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
From: Shannon Zhao
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c| 29
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 17 +
include/hw/acpi/aml-build.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index bd9
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 11 +++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/a
From: Shannon Zhao
As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86
to make it only for x86. ARM doesn't support cpu and memory hotplug, add
CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them
for target-arm.
Signed-off-by: Shannon Zhao
Signed-off-by: S
From: Shannon Zhao
Add PCIe controller in ACPI DSDT table, so the guest can detect
the PCIe.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 154 +++
1 file changed, 154 insertions(+)
diff --git a/hw/arm/virt-
From: Shannon Zhao
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86.
Here we still use RSDT as UEFI puts ACPI tables below 4G address space,
and UEFI ignore the RSDT or XSDT.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/ac
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 18 ++
include/hw/acpi/aml-build.h | 5 +
2 files changed, 23 insertions(+)
diff --git a/hw/acpi/aml-build.c
From: Shannon Zhao
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/h
From: Shannon Zhao
According to ACPI spec, DefBuffer can take two parameters: BufferSize
and ByteList. Make it consistent with the spec. Uninitialized buffer
could be requested by passing ByteList as NULL to reserve space.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Ig
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 12
hw/i386/acpi-build.c| 58 +++---
include/hw/acpi/aml-build.h | 68 ++
From: Shannon Zhao
Generate MCFG table for PCIe controller.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-b
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 7 +++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-buil
From: Shannon Zhao
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c | 57
in
From: Shannon Zhao
To generate ACPI table for PCIe controller, we need the base and size of
the PCIe ranges. Record these ranges in MemMapEntry array, then we could
share and use them for generating ACPI table.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c
From: Shannon Zhao
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 53 +
include/hw/acpi/aml-build.h | 1 +
2 fil
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 8
include/hw/acpi/aml-build.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-bui
From: Shannon Zhao
Move some common definitions to virt.h. These will be used by
generating ACPI tables.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c | 21 +--
include/hw/arm/virt.h | 56 +++
From: Shannon Zhao
Add aml_memory32_fixed() for describing device mmio region in resource
template. These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
Reviewed-by: Igor Mammedov
Reviewed-by: Michael S.
From: Shannon Zhao
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Sig
From: Shannon Zhao
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described usi
From: Shannon Zhao
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Igor Mammedov
---
hw/acpi/aml-build.c | 27 +++
From: Shannon Zhao
This patch series generate seven ACPI tables for machine virt on ARM.
The set of generated tables are:
- RSDP
- RSDT
- MADT
- GTDT
- FADT
- DSDT
- MCFG (For PCIe host bridge)
These tables are created dynamically using the function of aml-build.c,
taking into account the needed
From: Shannon Zhao
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
On Sat, 05/23 19:11, Max Reitz wrote:
> On 21.05.2015 08:43, Fam Zheng wrote:
> >We don't want new requests from guest, so block the operation around the
> >nested poll.
> >
> >It also avoids looping forever when iothread is submitting a lot of requests.
> >
> >Signed-off-by: Fam Zheng
> >---
> >
On Sat, 05/23 18:51, Max Reitz wrote:
> On 22.05.2015 06:54, Fam Zheng wrote:
> >On Thu, 05/21 15:32, Fam Zheng wrote:
> >>On Thu, 05/21 15:06, Wen Congyang wrote:
> >>>On 05/21/2015 02:42 PM, Fam Zheng wrote:
> It blocks device IO.
>
> All bdrv_op_block_all/blk_op_block_all callers ar
On Sun, May 24, 2015 at 08:16:30PM +1000, Alexey Kardashevskiy wrote:
> On 12.05.2015 19:58, Alexey Kardashevskiy wrote:
> >On 05/07/2015 05:10 PM, Alexey Kardashevskiy wrote:
> >>The changelog is:
> >> > version: update to 20150429
> >> > pci: Use QEMU created PCI device nodes
> >> > usb: su
On Thu, May 21, 2015 at 01:24:11PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> and use it in loadvm_state and ram_load.
>
> Where ever it's used, check the return and error if it failed.
>
> Minor: ram_load was using a 257 byte array for its string, the
>
On Wed, May 13, 2015 at 12:29:33PM +0200, Greg Kurz wrote:
> XICS needs to know the upper value for cpu_index as it is used to compute
> the number of servers:
>
> smp_cpus * kvmppc_smt_threads() / smp_threads
>
> When passing -smp cpus=1,threads=9 on a POWER8 host, we end up with:
>
> 1
On Thu, May 21, 2015 at 10:32:06AM +0530, Bharata B Rao wrote:
> Add an Error argument to cpu_exec_init() to let users collect the
> error. This is in preparation to change the CPU enumeration logic
> in cpu_exec_init(). With the new enumeration logic, cpu_exec_init()
> can fail if cpu_index values
On Thu, May 21, 2015 at 10:32:07AM +0530, Bharata B Rao wrote:
> Currently CPUState.cpu_index is monotonically increasing and a newly
> created CPU always gets the next higher index. The next available
> index is calculated by counting the existing number of CPUs. This is
> fine as long as we only
On Mon, May 18, 2015 at 09:43:21AM +0200, Thomas Huth wrote:
> Some recent patches require functions from libfdt version 1.4.0,
> so we should check for this version during the configure step
> already. Unfortunately, there does not seem to be a proper #define
> for the version number in the libfdt
On Thu, May 21, 2015 at 01:24:12PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Split qemu_savevm_state_begin to:
> qemu_savevm_state_header That writes the initial file header.
> qemu_savevm_state_beginThat sets up devices and does the first
>
On Thu, May 21, 2015 at 01:24:14PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> There are currently lots of pieces of incoming migration state scattered
> around, and postcopy is adding more, and it seems better to try and keep
> it together.
>
> allocate MIS i
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
fpu/softfloat-specialize.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index fa1214a..6dd41d8 100644
--- a/fpu/softfloat-specialize.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 2 +-
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/misc_helper.c | 19 +++
target-s390x/translate.c | 7 +++
5 files changed, 30
We currently use an hardcoded value for the STFL instruction. Move that
to a still hardcoded value but computed from bit values. This is more
maintainable and can be reused for the STFLE instruction.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h
LOAD LENGTHENED and LOAD ROUNDED are considered as FP operations and
thus need to convert input sNaN into corresponding qNaN.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/fpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
The cpu_mmu_index function wrongly looks at PSW P bit to determine the
MMU index, while this bit actually only control the use of priviledge
instructions. The addressing mode is detected by looking at the PSW ASC
bits instead.
This used to work more or less correctly up to kernel 3.6 as the kernel
LY is part of the long-displacement facility.
RISBHG and RISBLG are part of the high-word facility.
STCMH is part of the z/Architecture.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 8
1 file changed, 4 insertions(+), 4 deleti
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 8bda2e0..35bfdec 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -169
runtime_exception computes the psw.addr value using the actual exception
address and the instruction length computed by calling the get_ilen
function. However as explained above the get_ilen code, it returns the
actual instruction length, and not the ILC. Therefore there is no need to
multiply the
The s390x floating point unit detects tininess before rounding, so set
the softfloat fp_status up appropriately.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-s390x/cpu.c b/target
This complete the general-instructions-extension facility, enable it.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 2 +-
target-s390x/insn-data.def | 3 +++
target-s390x/translate.c | 35 +++
3 files
This patchset fixes a few issues with the s390x emulation and improves
it a bit by a emulating a few more instructions.
With this patchset and the ones posted a few days ago, I have been able
to build the GNU libc in both a 64-bit guest with 64-bit userland and a
64-bit guest with a 31-bit userlan
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 12 +++--
target-sh4/helper.h| 1 -
target-sh4/op_helper.c | 118 -
target-sh4/tra
This patchset improves the SH4 emulation by using the recently added
TCG instructions, namely add2, sub2 and movcond. For that the T, Q and
M bits are split out from the SR register. This allow the optimizer and
the liveness analysis to do some more optimisations.
The last two patches are doing cl
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 882c8d8..38d4a6f 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6 @@
*
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 212
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d5b448e..250632a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -795,12 +795,12 @@ s
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index daea268..882c8d8 100644
--- a/target-sh4/translate.c
+++ b/target-
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index a7a8f39..d5b448e 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30 ++--
target-sh4/gdbstub.c |
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index f9bc24c..a7a8f39 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -642,17 +642,15 @@
On Sat, May 23, 2015 at 03:06:52PM -0700, Richard Henderson wrote:
> As reported by Rich the other day. As I don't have a user-land
> binary that depends on this, I merely note that it still runs
> the linux-user-test sh4 binary. And gdb confirms that the LLSC
> bit does get set.
>
> Rich, can
On 2015-05-23 15:06, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> linux-user/main.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 3f32db0..7e0a439 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -39
On 2015-05-23 15:06, Richard Henderson wrote:
> As reported by Rich the other day. As I don't have a user-land
> binary that depends on this, I merely note that it still runs
> the linux-user-test sh4 binary. And gdb confirms that the LLSC
> bit does get set.
How would you like to see this patc
Move the target_disas() cris specifics to the QOM disas_set_info hook
and delete the cris specific code in disas.c.
This also now adds support for monitor disas to cris.
E.g.
(qemu) xp 0x40004000
40004000: 0x1e6f25f0
And before this patch:
(qemu) xp/i 0x40004000
0x40004000: Asm output no
Cris has the complication of variable length instructions and has
a check in place to clamp memory reads in case the disas request
doesn't have enough bytes for the instruction being disas'd. This
breaks down in the case where disassembling for the monitor where
the buffer length is defaulted to 0.
On 2015-05-23 15:06, Richard Henderson wrote:
> Only exposing FPU and LLSC as the only features
> supported by the translator.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/elfload.c | 29 +
> 1 file changed, 29 insertions(+)
>
> diff --git a/linux-user/elf
Move the target_disas() ARM specifics to the QOM disas_set_info hook
and delete the ARM specific code in disas.c.
This has the extra advantage of the more fully featured target_disas()
implementation now applying to monitor_disas().
Currently, target_disas() has multi-endian, thumb and AArch64
su
Add the print_insn pointer to the disassemble info structure. This is
to prepare for QOMification support, where a QOM CPU hook function will
be responsible for setting the print_insn function. Add this function
to the existing struct to consolidate such that only the one struct
needs to be passed
Move the target_disas() MB specifics to the QOM disas_set_info hook
and delete the MB specific code in disas.c.
This also now adds support for monitor disas to Microblaze.
E.g.
(qemu) xp 0x9000
9000: 0x94208001
And before this patch:
(qemu) xp/i 0x9000
0x9000: Asm output
Add a QOM function hook for target-specific disassembly setup. This
allows removal of the #ifdeffery currently implementing target specific
disas setup from disas.c.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Crosthwaite
---
disas.c | 22 ++
include/qom/cp
In a normal disassembly flow, the printf and stream being used varies
from disas job to job. In particular it varies if mixing monitor_disas
and target_disas.
Make both the printfer function and target stream settable in the
QEMUDisassmbler class. Remove the stream_ initialisation from the
constru
Depends on series: [PATCH v2 0/2] monitor+disas: Remove uses of ENV_GET_CPU
Intended for QOM queue.
These two functions are mostly trying to do the same thing, which is
disassemble a target instruction (sequence) for printfing. The
architecture specific setup is largely duped between the two func
For "Hello world" with shared glibc, it needs to implement additional
instructions and fix one additional bug (it is about syscall_nr.h: need
stat64 and fstatat64).
I shall send patch v11 within this month. :-)
Thanks.
On 5/22/15 09:48, Chen Gang wrote:
> On 05/22/2015 07:40 AM, Chris Metcalf
On Mon, May 18, 2015 at 9:31 AM, Peter Maydell wrote:
> On 9 May 2015 at 21:11, Peter Crosthwaite wrote:
>> Move the target_disas() ARM specifics to the QOM disas_set_info hook
>>
>> +static int
>> +print_insn_thumb1(bfd_vma pc, disassemble_info *info)
>> +{
>> + return print_insn_arm(pc | 1, i
On Mon, May 11, 2015 at 8:57 AM, Richard Henderson wrote:
> On 05/09/2015 01:11 PM, Peter Crosthwaite wrote:
>> class QEMUDisassembler : public Disassembler {
>> public:
>> -explicit QEMUDisassembler(FILE *stream) : stream_(stream) { }
>> +QEMUDisassembler() {
>> +printf_ = NULL;
The monitor currently has one helper, mon_get_cpu() which will return
an env pointer. The target specific users of this API want an env, but
all the target agnostic users really just want the cpu pointer. These
users then need to use the target-specifically defined ENV_GET_CPU to
navigate back up t
disas does not need to access the CPU env for any reason. Change the
APIs to accept CPU pointers instead. Small change pattern needs to be
applied to all target translate.c. This brings us closer to making
disas.o a common-obj and less architecture specific in general.
Cc: Richard Henderson
Cc: P
Neither the monitor or disassembly core has a good reason to navigate from an
env pointer to a cpu pointer. Disas should not need env awarness at all, that
is removed in P2.
The monitor is trickier, the env is still needed by some #ifdef switched target
specific code but all common code only needs
Hi Saket,
On Tue, May 5, 2015 at 10:11 PM, Saket Sinha wrote:
> Hi,
>
> I am trying to run u-boot as a coreboot payload on qemu-x86.Currently
> facing some difficulty in the process.
>
> Has anyone tried running u-boot bare-metal or as a coreboot payload on
> qemu-x86 before?
>
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