will it be solved in the next qemu upload, right? how long will it take
to have it on launchpad builders?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1042388
Title:
qemu: Unsupported syscall: 257
Il 20/12/2013 08:05, Fam Zheng ha scritto:
> As other tests, the image file is created in /tmp other than current
> dir. Thus there will not be an unignored file under tests for intree
> build.
>
> Signed-off-by: Fam Zheng
> ---
> tests/acpi-test.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
2013/12/18 Konrad Rzeszutek Wilk
> On Wed, Dec 18, 2013 at 07:15:43PM +, Stefano Stabellini wrote:
> > Hi all,
> > the xenpv machine provides Xen paravirtualized backends for console,
> > disk and framebuffer. xenfb in particular is the only open source
> > framebuffer backend available.
> >
As other tests, the image file is created in /tmp other than current
dir. Thus there will not be an unignored file under tests for intree
build.
Signed-off-by: Fam Zheng
---
tests/acpi-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/acpi-test.c b/tests/acpi-test.
Hi,
this patch or one of the two following patches breaks compilation with
--enable-debug (lots of TCGv_i32 - TCGv_i64 mismatches).
Cheers,
Stefan
Am 20.12.2013 02:00, schrieb Alexander Graf:
> From: Tom Musta
>
> This patch adds the VSX Select (xxsel) instruction.
>
> The xxsel instruction has
Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL -no32 S
152 00100 11000 CTRL yes-3
This removes not supported SPR from CPU classes.
Alexey Kardashevskiy (5):
target-ppc: fix LPCR SPR number
target-ppc: remove powerpc 970gx
target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
target-ppc: remove unsupported SPRs fr
The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.
This removes 970GX.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/STATUS | 9
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5
bookIV nor PowerISA 2.04, the numbers assigned to them are not defined
either so remove them.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 39 ---
1 file changed,
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so
remove it from POWER7/8 class as it is "S" (server) category.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 46 -
1 file changed, 46 deletions(-)
diff --
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of
316.
This fixes the definition of LPCR SPR.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 2 +-
target-ppc/translate_init.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tar
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ebd7dc..d52d
Currently, if compile with Werror option, the error message shows
below:
GEN config-host.h
GEN trace/generated-tracers.h
CHK version_gen.h
GEN trace/generated-tracers.c
CCvl.o
vl.c: In function ‘get_boot_devices_list’:
vl.c:1257:21: error: ‘bootpath’ may be used uninitial
Now "enum AIOContext" will generate AIO_CONTEXT instead of A_I_O_CONTEXT,
"X86CPU" will generate X86_CPU instead of X86_C_P_U.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
include/qapi/qmp/qerror.h |2 +-
scripts/qapi.py | 26 +++---
target-i386/cpu
Alexander Graf writes:
> On 19.12.2013, at 07:55, Aneesh Kumar K.V
> wrote:
>
>> Alexander Graf writes:
>>
>>> On 07.11.2013, at 15:31, Aneesh Kumar K.V
>>> wrote:
>>>
From: "Aneesh Kumar K.V"
With kvm enabled, we store the hash page table information in the
hypervis
Signed-off-by: Wenchao Xia
---
docs/qapi-code-gen.txt |8 +++-
scripts/qapi-visit.py |6 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/docs/qapi-code-gen.txt b/docs/qapi-code-gen.txt
index a2e7921..c92add9 100644
--- a/docs/qapi-code-gen.txt
+++ b/docs/qapi-co
Prior to this patch, qapi-visit.py used custom code to generate enum
names used for handling a qapi union. Fix it to instead reuse common
code, with identical generated results, and allowing future updates to
generation to only need to touch one place.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric
After this patch, hidden enum type BlockdevOptionsKind will not
be generated, and other API can use enum BlockdevDriver.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
qapi-schema.json | 14 +-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/qapi-schema.jso
Test for inherit and complex union.
Signed-off-by: Wenchao Xia
---
tests/qapi-schema/qapi-schema-test.json | 22 ++
tests/qapi-schema/qapi-schema-test.out |9 +++
tests/test-qmp-input-visitor.c | 93 +
tests/test-qmp-output-visitor.c | 116 +
It will check whether the values specified are written correctly,
and whether all enum values are covered, when discriminator is a
pre-defined enum type
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi-visit.py | 17 +
scripts/qapi.py | 31 ++
Later both qapi-types.py and qapi-visit.py need a common function
for enum name generation.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi-types.py | 10 --
scripts/qapi.py | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/s
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
is specified as a pre-defined enum type in schema. After this patch,
the pre-defined enum type will be really used as the switch case
condition in generated C co
Later other scripts will need to check the enum values.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi.py| 18 ++
tests/qapi-schema/comments.out |2 +-
tests/qapi-schema/qapi-schema-test.out |4 +++-
3 files changed,
This series address two issues:
1. support using enum as discriminator in union.
For example, if we have following define in qapi schema:
{ 'enum': 'EnumOne',
'data': [ 'value1', 'value2', 'value3' ] }
{ 'type': 'UserDefBase0',
'data': { 'base-string0': 'str', 'base-enum0': 'EnumOne' } }
Bef
It is bad that same key was specified twice, especially when a union have
two branches with same condition. This patch can prevent it.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi.py |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/scripts/qapi.py
On Thu, Nov 28, 2013 at 12:05:33PM +0530, Bharat Bhushan wrote:
> This patch adds pci pin to irq_num routing callback
> Without this patch we gets below warning
>
> "
> PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
> qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500
On Fri, Dec 20, 2013 at 04:15:09AM +, bharat.bhus...@freescale.com wrote:
>
>
> > -Original Message-
> > From: Michael S. Tsirkin [mailto:m...@redhat.com]
> > Sent: Friday, December 20, 2013 12:02 AM
> > To: Alexander Graf
> > Cc: Bhushan Bharat-R65777; Wood Scott-B07421; QEMU Develop
On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell wrote:
> Update the generic cpreg support code to also handle AArch64:
> AArch64-visible registers coexist in the same hash table with
> AArch32-visible ones, with a bit in the hash key distinguishing
> them.
>
> Signed-off-by: Peter Maydell
> ---
>
On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell wrote:
> On 19 December 2013 06:01, Peter Crosthwaite
> wrote:
>> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
>> wrote:
>>> +*key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>>> + r-
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Friday, December 20, 2013 12:02 AM
> To: Alexander Graf
> Cc: Bhushan Bharat-R65777; Wood Scott-B07421; QEMU Developers; qemu-ppc
> Subject: Re: [PATCH 2/2] ppc-e500: implement PCI INTx routing
>
> On Thu, D
On Fri, Dec 20, 2013 at 10:49 AM, Anthony Liguori wrote:
> On Wed, Dec 18, 2013 at 8:59 AM, Luiz Capitulino
> wrote:
>> The following changes since commit e157b8fdd412d48eacfbb8c67d3d58780154faa3:
>>
>> Merge remote-tracking branch 'bonzini/virtio' into staging (2013-12-13
>> 11:10:33 -0800)
On Wed, Dec 18, 2013 at 07:15:43PM +, Stefano Stabellini wrote:
> Hi all,
> the xenpv machine provides Xen paravirtualized backends for console,
> disk and framebuffer. xenfb in particular is the only open source
> framebuffer backend available.
> On ARM we don't need QEMU to emulate any hardwa
On 12/05/2013 08:39 PM, Alexey Kardashevskiy wrote:
> On 11/20/2013 04:39 PM, Alexey Kardashevskiy wrote:
>> This adds a put_tce() callback to the SPAPR TCE TABLE device class.
>> The new callback allows to have different IOMMU types such as upcoming
>> VFIO IOMMU and it will be used more by the up
On 12/05/2013 08:39 PM, Alexey Kardashevskiy wrote:
> On 11/21/2013 03:08 PM, Alexey Kardashevskiy wrote:
>> Here are few reworks for spapr-pci PHB which I'd like to have to support
>> VFIO.
>> QOM, errors printing, traces, nothing really serious. Thanks!
>>
>> Alexey Kardashevskiy (4):
>> spapr
From: Tom Musta
This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs. Additionally, the VSX instructions
are added to the list of TCG-enabled instruction.
Signed-off-by: Tom Musta
Signed-o
There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").
The big downside to calling it different from anyone else is that tools
that pass -device get confused. They are looking for a bus "pci.0" rather
than "pci".
To make life easier for everyone, le
From: Tom Musta
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 15 +++
1 file changed, 15 insertions(+)
d
From: Alexey Kardashevskiy
The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory block reported in
the LPAR’s device tree.
So SLOF only maps the first block and that block needs to span
the full RMA.
This makes sure that the RMA area is
From: Paolo Bonzini
spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=" option. Instead, tie it to -pflash like
other non-volatile RAM devices. This provides the following possibilities
for adding a backend for the sPAPR non-volatile RAM:
* -pflash filename
From: Tom Musta
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Ab
From: Tom Musta
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/target-p
On Thu, Dec 19, 2013 at 3:00 AM, Luiz Capitulino wrote:
> From: Paolo Bonzini
>
> Signed-off-by: Paolo Bonzini
> Reviewed-By: Igor Mammedov
> Signed-off-by: Luiz Capitulino
> ---
> qom/object.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/qom/object.c b/qo
On 20.12.2013, at 03:14, Alexey Kardashevskiy wrote:
> Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
> a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
> breaks compile.
>
> This fixes compiler errors.
>
> Signed-off-by: Alexey Kardashevskiy
Thanks, a
From: Tom Musta
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 41
From: Alexey Kardashevskiy
So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.
This adds a new family class, PVR base and mask values and moves
Power7+ v2.1 CPU to a new family. The class init f
From: Alexey Kardashevskiy
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of alr
On Thu, Dec 19, 2013 at 3:00 AM, Luiz Capitulino wrote:
> From: Paolo Bonzini
>
> Add two commands that are the monitor counterparts of -object. The commands
> have the same Visitor-based implementation, but use different kinds of
> visitors so that the HMP command has a DWIM string-based syntax
Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
breaks compile.
This fixes compiler errors.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 5 +++--
1 file changed, 3 insertions(+), 2 d
From: Tom Musta
This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.
The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchar
From: Alexey Kardashevskiy
This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.
The only parameter handled at the moment is
"platform-processor-diagnostics-run-mode" which is always disabled and
does not support changing. This is expected to make
"p
From: Tom Musta
This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 16
1 file changed, 16 insertio
From: Tom Musta
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-
From: Tom Musta
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.
This improves vmdk_create to use bdrv_* functions to replace qemu_open
and other fd functions. The error handling are improved as well. One
difference is that bdrv_pwrite will round up buffer to sectors, so for
description file, an extra bdrv_truncate is used in the end to drop
inding zeros.
Notes
On 2013年12月19日 21:12, Stefan Hajnoczi wrote:
On Tue, Dec 17, 2013 at 08:00:00PM +0800, Fam Zheng wrote:
@@ -1511,48 +1521,55 @@ static int vmdk_create_extent(const char *filename,
int64_t filesize,
header.check_bytes[3] = 0xa;
/* write all the data */
-ret = qemu_write_full(fd,
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
From: Tom Musta
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henders
From: Tom Musta
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are alrea
From: Tom Musta
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
in
From: Tom Musta
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd (Scalar Negative Absolute Value Double-Precision)
- xsnegdp (Scalar Negate Double-Precision)
- xscpsgndp (Scalar Copy Sign Double-Precision)
A common generator
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to e
From: Peter Crosthwaite
The qemu_devtree API is a wrapper around the fdt_ set of APIs.
Rename accordingly.
Signed-off-by: Peter Crosthwaite
[agraf: also convert hw/arm/virt.c]
Signed-off-by: Alexander Graf
---
device_tree.c| 62 ++---
hw/arm/boot.c| 2
From: Peter Crosthwaite
Looking at the implementation, this doesn't really have a lot to do
with arrays. Its just a pointer to a buffer and is passed through
to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it
consistent with libfdt, which in the wrapped function just calls it
"v
From: Paul Mackerras
This makes sure that all NUMA memory blocks reside within RAM or
have zero length.
Reviewed-by: Thomas Huth
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
d
We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too which indicate whether
we're still in the same translation block cache bucket.
Signed-off-by: Alexander Graf
---
target-ppc/helper_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 de
From: Tom Musta
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translat
From: Tom Musta
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.
The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This
overloading is done in m
From: Alexey Kardashevskiy
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/intc/xics.c | 24
hw/nvram/spapr_nvram.c | 16
hw/ppc/spapr_events.c | 6 +++---
hw/ppc/spapr_pci.c | 42 +
From: Tom Musta
This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.
Signed-off-by: Tom Musta
Signed-off-by: Ant
From: Tom Musta
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 28
1 file changed, 28 insert
Hi Blue / Aurelien / Anthony,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit 3dc7e2a3fedafc2f951bd62300b342c84e3606f8:
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into
staging (2013-12-19 11:56:33 -0800)
are available
From: Greg Kurz
The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `k
From: Tom Musta
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
Signed-off-by: Alexander Graf
---
target-ppc/translate.c |
From: Tom Musta
This patch adds the lxvd2x instruction.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
ind
This has been fixed in Git in the following commits:
commit f4f1e10a58cb5ec7806d47d20671e668a52c3e70
Author: Erik de Castro Lopo
Date: Fri Nov 29 18:39:23 2013 +1100
linux-user: Implement handling of 5 POSIX timer syscalls.
Implement timer_create, timer_settime
On Wed, Dec 18, 2013 at 8:59 AM, Luiz Capitulino wrote:
> The following changes since commit e157b8fdd412d48eacfbb8c67d3d58780154faa3:
>
> Merge remote-tracking branch 'bonzini/virtio' into staging (2013-12-13
> 11:10:33 -0800)
>
> are available in the git repository at:
Sorry, you lost the me
Peter Maydell wrote:
On 18 December 2013 16:59, Luiz Capitulino wrote:
qerror: Remove assert_no_error()
This broke my target-arm pullreq :-(
Yes, QMP queue and qemu-arm queue will conflict,
because patch "target-arm/cpu: Convert reset CBAR to a property"
used assert_no_e
On 18 December 2013 16:59, Luiz Capitulino wrote:
> qerror: Remove assert_no_error()
This broke my target-arm pullreq :-(
-- PMM
On 20 December 2013 00:14, Anthony Liguori wrote:
> Peter Maydell writes:
>
>> Only took a week for the target-arm queue to fill up again :-)
>> Please pull...
>
> ubuntu@build:~/build/qemu$ make
> CCaarch64-softmmu/gdbstub-xml.o
> CCaarch64-softmmu/target-arm/cpu.o
> /home/ubuntu/git
Peter Maydell writes:
> Only took a week for the target-arm queue to fill up again :-)
> Please pull...
ubuntu@build:~/build/qemu$ make
CCaarch64-softmmu/gdbstub-xml.o
CCaarch64-softmmu/target-arm/cpu.o
/home/ubuntu/git/qemu/target-arm/cpu.c: In function ‘arm_cpu_post_init’:
/home/ub
Il 19/12/2013 20:15, Michael S. Tsirkin ha scritto:
> On Fri, Dec 06, 2013 at 05:54:23PM +0100, Paolo Bonzini wrote:
>> PCI is handling resetting of its devices before the bus is reset,
>> but this is only necessary because qdev is broken and usually does
>> pre-order reset. Post-order is a much b
On 12/04/2013 01:09 PM, Alexey Kardashevskiy wrote:
> On 12/03/2013 10:09 PM, Igor Mammedov wrote:
>> On Tue, 3 Dec 2013 14:42:48 +1100
>> Alexey Kardashevskiy wrote:
>>
>>> This adds suboptions support for -cpu. This keeps @cpu_model in order not
>>> to break the existing architectures/machines.
On 12/19/2013 12:47 PM, Max Reitz wrote:
> Move the check whether there actually is a config file into the
> read_config() function.
>
> Signed-off-by: Max Reitz
> Reviewed-by: Kevin Wolf
> ---
> block/blkdebug.c | 36 +++-
> 1 file changed, 19 insertions(+), 17
On 19.12.2013, at 20:57, Anthony Liguori wrote:
> Alexander Graf writes:
>
>> Hi Blue / Aurelien / Anthony,
>>
>> This is my current patch queue for s390. Please pull.
>>
>> Alex
>>
>>
>> The following changes since commit f46e720a82ccdf1a521cf459448f3f96ed895d43:
>> Laszlo Ersek (1):
>>
On 12/19/2013 12:47 PM, Max Reitz wrote:
> This function basically parses command-line options given as a QDict
> replacing a config file.
>
> For instance, the QDict {"section.opt1": 42, "section.opt2": 23}
> corresponds to the config file:
>
> [section]
> opt1 = 42
> opt2 = 23
Thanks for the e
On 19 December 2013 22:00, Peter Maydell wrote:
> We implement a number of float-to-integer conversions using conversion
> to an integer type with a wider range and then a check against the
> narrower range we are actually converting to. If we find the result to
> be out of range we correctly rais
On 18 December 2013 20:19, Tom Musta wrote:
> The comment preceding the float64_to_uint64 routine suggests that
> the implementation is broken. And this is, indeed, the case.
>
> This patch properly implements the conversion of a 64-bit floating
> point number to an unsigned, 64 bit integer.
>
>
We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then a check against the
narrower range we are actually converting to. If we find the result to
be out of range we correctly raise the Invalid exception, but we must
also suppress other
If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
exponent field is all zeroes). This means that when we convert
it to our unpacked encoding the unpacked exponent must be one
greater than for a normal number, which represen
Quoting Markus Armbruster (2013-12-17 01:20:16)
> [Cc: Anthony, Mike for QAPI schema expertise]
>
> Luiz Capitulino writes:
>
> > On Tue, 10 Dec 2013 19:15:05 +0100
> > Paolo Bonzini wrote:
> >
> >> -BEGIN PGP SIGNED MESSAGE-
> >> Hash: SHA1
> >>
> >> Il 10/12/2013 19:00, Eric Blake ha
On 12/19/2013 12:47 PM, Max Reitz wrote:
> Reversing qdict_array_split(), qdict_flatten() should flatten QLists as
> well by interpreting them as QDicts where every entry's key is its
> index.
>
> This allows bringing QDicts with QLists from QMP commands to the same
> form as they would be given a
On 18 December 2013 20:19, Tom Musta wrote:
> The float64_to_uint32 has several flaws:
>
> - for numbers between 2**32 and 2**64, the inexact exception flag
>may get incorrectly set. In this case, only the invalid flag
>should be set.
>
>test pattern: 425F81378DC0CD1F / 0x1.f8137
On 18 December 2013 20:19, Tom Musta wrote:
> The float64_to_uint64_round_to_zero routine is incorrect.
>
> For example, the following test pattern:
>
> 46697351FF4AEC29 / 0x1.97351ff4aec29p+103
>
> currently produces 8000 instead of .
>
> This patch re-implements t
On 18 December 2013 20:19, Tom Musta wrote:
> The float64_to_uint32_round_to_zero routine is incorrect.
>
> For example, the following test pattern:
>
> 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
>
> will erroneously set the inexact flag.
>
> This patch re-implements the routine to use the
> fl
On Tue, Nov 26, 2013 at 01:38:33AM -0500, Xu Wang wrote:
> Check the backing file for a loop during image boot, to avoid a lack or
> response or segfault.
>
> Signed-off-by: Xu Wang
> ---
> blockdev.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/blockdev.c b/blockdev.c
> inde
On 12/12/2013 05:34 AM, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno
> ---
> target-mips/translate.c | 119
> +--
> 1 file changed, 52 insertions(+), 67 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/11/2013 04:17 PM, Aurelien Jarno wrote:
> The comments apply to 8-bit stores, not 8-byte stores.
>
> Cc: Richard Henderson
> Signed-off-by: Aurelien Jarno
> ---
> tcg/i386/tcg-target.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 19 December 2013 21:26, Richard Henderson wrote:
> On 12/19/2013 01:23 PM, Peter Maydell wrote:
>> Hmm. I clearly don't entirely understand the rules here.
>> The TCG README says "temporaries are only live
>> in a basic block" and "After the end of a basic block, the
>> content of temporaries i
On 18 December 2013 20:19, Tom Musta wrote:
> This patch adds the float32_to_uint64() routine, which converts a
> 32-bit floating point number to an unsigned 64 bit number.
>
> This contribution can be licensed under either the softfloat-2a or -2b
> license.
>
> V2: Reduced patch to just this sing
On 12/19/2013 01:23 PM, Peter Maydell wrote:
> Hmm. I clearly don't entirely understand the rules here.
> The TCG README says "temporaries are only live
> in a basic block" and "After the end of a basic block, the
> content of temporaries is destroyed", which I took to
> mean that the value in the
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