Am 30.06.2013 03:27, schrieb Alexander Graf:
> Soon we will introduce intermediate processing pauses which will
> allow the bottom half to restart a DMA request that couldn't be
> fulfilled yet.
>
> For that to work, move the processing variable into the io struct
> which is what DMA providers wor
Am 30.06.2013 03:26, schrieb Alexander Graf:
> The macio code is basically undebuggable as it stands today, with no
> debug prints anywhere whatsoever. DBDMA was better, but I needed a
> few more to create reasonable logs that tell me where breakage is.
>
> Add a DPRINTF macro in the macio source
Am 30.06.2013 03:26, schrieb Alexander Graf:
> s/^I//g on the file with a few manual tweaks to align things.
>
> Signed-off-by: Alexander Graf
> ---
> hw/misc/macio/mac_dbdma.c | 102
> +++---
> 1 file changed, 51 insertions(+), 51 deletions(-)
>
Am 30.06.2013 03:26, schrieb Alexander Graf:
> On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
> on some random PCI device. Move it there to become more compatible.
>
> While at it, also clean up the IDE channel connection logic.
>
> Signed-off-by: Alexander Graf
>
> ---
On Sun, 2013-06-30 at 10:59 +1000, Alexey Kardashevskiy wrote:
> > 1) A PCI bus function to do the MSI -> virq mapping
> > 2) On x86 (and e500), this is implemented by calling
> > kvm_irqchip_add_msi_route()
> > 3) On pseries, this just returns msi->data
> >
> > Perhaps (2) can just be the defaul
Am 30.06.2013 03:45, schrieb Alexander Graf:
> When running QEMU with "-cpu ?" we walk through every alias for every
> target CPU we know about. This takes several seconds on my very fast
> host system.
>
> Let's introduce a class object cache in the alias table. Using that we
> don't have to go t
Public bug reported:
when doing
device_add usb-host,hostaddr=010
taking 010 in the format of both lsusb or udev, qemu parses an octal number and
assumes hostaddr=8.
(i used a 2.0 device on the ehci.0 bus)
at least to me that is confusing.
also:
when adding a non-existent usb device (bogus hos
ps: when using host-libusb.c and tested on 1.5.1.tgz
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1196145
Title:
usb-host: hostaddr=0XX is parsed as octal number
Status in QEMU:
New
Bug descri
Am 30.06.2013 03:44, schrieb Alexander Graf:
> From: Scott Wood
>
> Enables support for the in-kernel MPIC that thas been merged into the
> KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex
> Graf (along with some other improvements).
>
> Note from Alex regarding kvm_irqchip_c
When network disconnection occurs during live migration, the migration thread
will be stuck in the function sendmsg(), as the migration socket is in
~O_NONBLOCK mode now.
Signed-off-by: Zeng Junliang
---
include/migration/migration.h |4
migration-tcp.c | 23 ++
Mac OS X accesses fancy timer registers inside of the mac-io on bootup.
These really should be ticking at the mac-io bus frequency, but I don't
see anyone upset when we just make them as fast as we want to.
With this patch on top of my previous patch queue and latest OpenBIOS
I am able to boot Ma
From: Andreas Färber
Previous code has #define POWERPC_INSNS2_ PPC_NONE in some
places for macrofied assignment to insns_flags2 field.
PPC_NONE is defined as zero though and QOM classes are zero-initialized,
so drop any pcc->insns_flags2 = PPC_NONE; assignments.
PPC_NONE itself is still in use
When running QEMU with "-cpu ?" we walk through every alias for every
target CPU we know about. This takes several seconds on my very fast
host system.
Let's introduce a class object cache in the alias table. Using that we
don't have to go through the tedious work of finding our target class.
Inst
Mac OS X's debugging serial driver accesses the ESCC through a different
register layout, called "escc-legacy". This layout differs from the normal
escc register layout purely by the location of the respective registers.
This patch adds a memory alias region that takes normal escc registers and
ma
From: Fabien Chouteau
"(qemu) info tlb" is a very useful tool for debugging, so I implemented
the missing 6xx version.
Signed-off-by: Fabien Chouteau
[agraf: fix printfs on hwaddr to PRI]
Signed-off-by: Alexander Graf
---
target-ppc/mmu_helper.c | 92 ++
From: Anthony Liguori
RTAS is a hypervisor provided binary blob that a guest loads and
calls into to execute certain functions. It's similar to the
vsyscall page in Linux or the short lived VMCI paravirt interface
from VMware.
The QEMU implementation of the RTAS blob is simply a passthrough
tha
From: Andreas Färber
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.
Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 4 +++-
target-ppc/translate_init.c | 16 +++-
2
From: Alexey Kardashevskiy
This adds a missing code to save CR (condition register) via
kvm_arch_put_registers(). kvm_arch_get_registers() already has it.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
Signed-off-by: Alexander Graf
---
target-ppc/kvm.c | 5 +
1 file chan
Mac OS X requires a second uninorth register set to be mapped a few
bytes above the first one. Let's just expose it to make it happy.
Signed-off-by: Alexander Graf
---
hw/ppc/mac_newworld.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
inde
From: Andreas Färber
SysBus can deal with NULL SysBusDeviceClass::init since 4ce5dae.
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/ppc/mpc8544_guts.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mp
From: Scott Wood
Enables support for the in-kernel MPIC that thas been merged into the
KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex
Graf (along with some other improvements).
Note from Alex regarding kvm_irqchip_create():
On x86, one would call kvm_irqchip_create() to
From: Scott Wood
KVM in-kernel MPIC support is going to expand this even more,
so let's keep it contained.
Signed-off-by: Scott Wood
Signed-off-by: Alexander Graf
---
hw/ppc/e500.c | 56 ++--
1 file changed, 34 insertions(+), 22 deletions(-)
Support in fwcfg has been around for exposure of the clock-frequency
CPU property. OpenBIOS reads it, we just never exposed it.
Since Mac OS X is very picky about its clock frequency values, let's
just take a known good value and always expose that.
Reported-by: Mark Cave-Ayland
Signed-off-by: A
From: Andreas Färber
Introduce type constant, cast macro and rename parent field.
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/ppc/mpc8544_guts.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_gut
We have stayed at 800x600x15 as default graphics mode for the last 9 years.
If there ever was a reason to be there, surely nobody remembers it.
However, recently non-Linux PPC guests started to show bad effects on 15 bit
color mode. They do work just fine with 32 bits however.
So let's switch to
From: David Gibson
Currently, for qemu-system-ppc64, the default machine type is 'mac99'.
The mac99 machine is not being actively maintained, and represents a
bizarre hybrid of components that never actually existed as a real system.
This patch changes the default machine to 'pseries', which is a
From: Andreas Färber
Split qdev initfn into instance_init and realize functions.
Change one occurrence of "klass" while at it.
Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
Signed-off-by: Alexander Graf
---
hw/intc/openpic.c | 34 +++---
1 file chan
From: David Gibson
I'm no longer at IBM, and therefore no long actively working on the pseries
(aka sPAPR) qemu machine type. This patch removes my information in the
MAINTAINERS file.
While we're at it, I've added some extra file patterns for pseries specific
files that weren't included in the
From: Scott Wood
...for use by the KVM in-kernel irqchip stub.
Signed-off-by: Scott Wood
Signed-off-by: Alexander Graf
---
hw/intc/openpic.c| 40 ++--
include/hw/ppc/openpic.h | 11 +++
2 files changed, 29 insertions(+), 22 deletions(-)
dif
From: Stefan Weil
This kind of type cast must use uintptr_t or target_ulong to be portable
for hosts with sizeof(void *) != sizeof(long).
Here the value is assigned to a variable of type target_ulong.
Signed-off-by: Stefan Weil
[agraf: fix compilation on 32bit hosts]
Signed-off-by: Alexander G
From: Andreas Färber
Introduce type constant and cast macro.
Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
Signed-off-by: Alexander Graf
---
hw/intc/openpic.c| 17 +++--
hw/ppc/e500.c| 2 +-
hw/ppc/mac_newworld.c| 2 +-
include/hw/ppc/open
From: Bharat Bhushan
Limit watchdog and fit timer to maximum timeout value which
qemu timer can support (INT64_MAX). This maximum timeout will be
hundreds of years, so limiting to max timeout is pretty safe.
Signed-off-by: Bharat Bhushan
Signed-off-by: Alexander Graf
---
hw/ppc/ppc_booke.c |
From: Andreas Färber
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
default-configs/ppcemb-softmmu.mak | 1 +
hw/intc/openpic_kvm.c | 54 +++---
hw/ppc/e500.c | 2 +-
include/hw/ppc/openpic.h | 1 +
There are cases where a kvm provided function is called from generic
hw code that doesn't know whether kvm is available or not. Provide
a stub file which can provide simple replacement functions for those
cases.
Signed-off-by: Alexander Graf
Reviewed-by: Paolo Bonzini
---
target-ppc/Makefile.ob
The L2CR register contains a number of bits that either impose configuration
which we can't deal with or mean "something is in progress until the bit is
0 again".
Since we don't model the former and we do want to accomodate guests using the
latter semantics, let's just ignore writes to L2CR. That
Mac OS X expects the uninorth control register set to contain one
register that always reads back what it writes in. Expose that.
This is just a temporary hack. Eventually, we want to expose the
uninorth (/uni-n in device tree) as a separate QOM device.
Signed-off-by: Alexander Graf
---
hw/ppc/
Hi Blue / Aurelien,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit ffeec223b55ea696567ed544016824199cd7c7bc:
Merge remote-tracking branch 'mjt/trivial-patches' into staging (2013-06-28
15:48:35 -0500)
are available in the git repository at:
From: Andreas Färber
6544 -> 8544
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/ppc/mpc8544_guts.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index 193beab..98540a4 100644
--- a/hw/ppc/mpc8544_guts.c
+
The usual MSI injection mechanism writes msi.data into memory using an
le32 wrapper. So on big endian guests, this swaps msg.data into the
expected byte order.
For irqfd however, we don't swap the payload right now, rendering
in-kernel MPIC emulation broken on PowerPC.
Swap msg.data to the correc
On PPC, we don't support MP state. So far it's not necessary and I'm
not convinced yet that we really need to support it ever.
However, the current idle logic in QEMU assumes that an in-kernel PIC
also means we support MP state. This assumption is not true anymore.
Let's split up the two cases in
The current logic updates KVM's view of our interrupt map every time we
change it. While this is nice and bullet proof, it slows things down
badly for me. QEMU spends about 3 seconds on every start telling KVM what
news it has on its routing maps.
Instead, let's just synchronize the whole irq rout
From: Fabien Chouteau
On PPC 6xx, data and code have separated TLBs. Until now QEMU was only
looking at data TLBs, which is not good when GDB wants to read code.
This patch adds a second call to get_physical_address() with an
ACCESS_CODE type of access when the first call with ACCESS_INT fails.
On PPC, we can have different types of interrupt controllers, so we really
only know that we are going to use one when we created it.
Export kvm_init_irq_routing() to common code, so that we don't have to call
kvm_irqchip_create().
Signed-off-by: Alexander Graf
---
include/sysemu/kvm.h | 1 +
k
From: Hervé Poussineau
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau
Reviewed-by: Andreas Färber
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target-ppc/t
We need to know when the IDE core starts a DMA transfer. Add a notifier
function so we have the chance to start transmitting data.
Signed-off-by: Alexander Graf
---
hw/ide/macio.c | 40
hw/ppc/mac.h | 2 ++
2 files changed, 42 insertions(+)
diff --git
s/^I//g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 102 +++---
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_db
We should only start processing DMA requests when we have data to process.
Hold off working through the DMA shuffling until the IDE core told us that
it's ready.
This is required because the guest can program the DMA engine or the IDE
transfer first. Both are legal.
Signed-off-by: Alexander Graf
We usually keep struct and constant definitions in header files. Move
them there to stay consistent and to make access to fields easier.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 117
include/hw/ppc/mac_dbdma.h | 118 +
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
Signed-off-by: Alexander Graf
---
hw/misc/maci
The DBDMA controller has a bottom half to asynchronously process DMA
request queues.
This bh was stored as a gross static variable. Move it into the device
struct instead.
While at it, move all users of it to the new generic kick function.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_db
The DBDMA controller can not change its command stream while it's
actively streaming data, true. But the fact that it's in RUN state
doesn't actually indicate anything. It could just as well be in
WAIT while in RUN. And then it's legal to change commands.
This fixes a real world issue I've encount
The DBDMA engine really just reads bytes from a producing device (IDE
in our case) and shoves these bytes into memory. It doesn't care whether
any alignment takes place or not.
Our code today however assumes that block accesses always happen on
sector (512 byte) boundaries. This is a fair assumpti
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disab
There was a debug print that didn't compile for me because the format
and the arguments weren't in sync. Fix it up.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdm
s/^I//g on the file.
Signed-off-by: Alexander Graf
---
hw/ide/macio.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 7a1c573..82409dc 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -55,7 +55,7 @@ static void pmac_ide
We can tell the guest the frequency of its time base through fwcfg.
However, we tell it a different value from the speed tb actually runs
at. Let's fix it and make the tbfreq initialization and the fwcfg exposure
use the same values.
Signed-off-by: Alexander Graf
---
hw/ppc/mac_newworld.c | 5 +
Recently there has been a lot of progress on the OpenBIOS side to get Mac OS X
to boot.
For a while now it seemed there was only very little to make it a fully working
guest os in QEMU.
This patch set is the result of this. With this I can successfully boot Mac OS X
10.2 to 10.4 with the g3beige
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- fix IRQ mapping
---
hw/ide/macio.c|
The DBDMA engine really is running all the time, waiting for input. However
we don't want to waste cycles constantly polling.
So introduce a kick function that data providers can call to notify the
DBDMA controller of new input.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 5 +
On 6/28/13 14:01 , "Laszlo Ersek" wrote:
>On 06/06/13 17:06, Tomoki Sekiyama wrote:
>
>> diff --git a/qga/vss-win32-requester.h b/qga/vss-win32-requester.h
>> new file mode 100644
>> index 000..f180f56
>> --- /dev/null
>> +++ b/qga/vss-win32-requester.h
...
>>+HRESULT vss_init(void);
>
>Can yo
On 06/30/2013 12:28 AM, Anthony Liguori wrote:
> On Sat, Jun 29, 2013 at 8:45 AM, Alexey Kardashevskiy wrote:
>> On PPC64 systems MSI Messages are translated to system IRQ in a PCI
>> host bridge. This is already supported for emulated MSI/MSIX but
>> not for irqfd where the current QEMU allocates
As a side effect this should fix coprocessor register numbering for SMP.
Signed-off-by: Andreas Färber
---
gdbstub.c | 80 ++---
include/qom/cpu.h | 3 ++
qom/cpu.c | 9 +
target-alpha/cpu.c | 1
Use CPUState::env_ptr for Xtensa.
This removes the last user of CPUArchState from gdb_set_stop_cpu().
Signed-off-by: Andreas Färber
---
gdbstub.c | 35 +++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index fa44550..7be234
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-s390x/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index cd9880e..cb
Allows us to drop find_cpu().
Xtensa still needs env for its num_g_regs.
Signed-off-by: Andreas Färber
---
gdbstub.c | 68 +--
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 81a8941..a8fafe2
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3643863..eb96272
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-lm32/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 227a801..6d107
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-xtensa/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dcb90a
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-cris/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 09d0d2b..ce1f0
Use MicroBlazeCPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-microblaze/translate.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
in
This moves setting the Program Counter from gdbstub into target code.
Use uint64_t type as maximum replacement for target_ulong.
Signed-off-by: Andreas Färber
---
gdbstub.c | 39 ++-
include/qom/cpu.h | 1 +
target-alpha/cpu.c
On 28/06/2013 23:44, Mark Cave-Ayland wrote:
On 28/06/13 03:08, Rob Landley wrote:
Commit 467b34689d27 upgraded the openbios image, and ever since my linux
system images hang about the time they try to initialize interrupts.
http://landley.net/aboriginal/bin/system-image-sparc.tar.bz2
Extract
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass instead of CPUXtensaState.
Prepares for storing per-class GDB register count.
Signed-off-by: Andreas Färber
---
gdbstub.c | 17 ---
hw/xtensa/pic_cpu.c | 47 --
target-xt
Since all targets now assign a softmmu-only field, we can drop helpers
cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
Prepares for changing cpu_memory_rw_debug() argument to CPUState.
Signed-off-by: Andreas Färber
---
exec.c | 20 ++--
hw/i
Propagate X86CPU in kvmvapic for simplicity.
Signed-off-by: Andreas Färber
---
cpus.c | 4 +--
disas.c | 4 +--
exec.c | 6 ++--
gdbstub.c | 2 +-
hw/i386/kvmvapic.c | 72 +++-
Also use bool argument while at it.
Prepares for replacing DisasContext::env with CPUState and for moving
singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-alpha/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-alpha/tr
Prepares for changing gdb_register_coprocessor() argument to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 11 ++-
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 1 +
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
Make inline target_memory_rw_debug() always available and change its
argument to CPUState. Let it check if CPUClass::memory_rw_debug provides
a specialized callback and fall back to cpu_memory_rw_debug() otherwise.
The only overriding implementation is for 32-bit sparc.
This prepares for changing
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
bsd-user/main.c| 10 ++
gdbstub.c | 6 +++---
include/exec/gdbstub.h | 2 +-
linux-user/main.c | 35 +++
linux-user/signal.c| 3 ++-
5 fil
In particular reindent to 4 instead of 2 spaces.
Prepares for changing cpu_single_step() argument in gdb_handlesig().
Signed-off-by: Andreas Färber
---
gdbstub.c | 94 +++
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a
Prepares for changing cpu_single_step() argument to CPUState.
Signed-off-by: Andreas Färber
---
cpu-exec.c| 2 +-
cpus.c| 2 +-
exec.c| 10 ++
include/exec/cpu-defs.h | 1 -
include/qom/cpu.h | 1 +
Signed-off-by: Andreas Färber
---
gdbstub.c | 7 +++
include/exec/gdbstub.h | 2 +-
target-arm/helper.c | 7 ---
target-m68k/helper.c| 3 ++-
target-ppc/translate_init.c | 15 ---
5 files changed, 18 insertions(+), 16 deletions(-)
di
Use UniCore32CPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-unicore32/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index e1fe
Callback implementations were specific to arm and m68k, so can easily
cast to ARMCPU and M68kCPU respectively.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 2 +-
include/exec/gdbstub.h | 2 +-
target-arm/arm-semi.c | 8 ++-
Needed for moving singlestep_enabled to CPUState.
Signed-off-by: Andreas Färber
---
target-alpha/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index dd7f0fb..147285a 100644
--- a/target-alpha/translate.
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 292c9e9..2fbe668
Use CPUState::env_ptr for now.
Prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index a8fafe2..cee9c13 100644
--- a/gdbstub.c
+++ b/gdbstub.c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-mips/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 160c0c0..8246c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-i386/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 14b0298..6550c
CPUArchState is no longer directly used since converting CPU loops to
CPUState.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c| 12
include/sysemu/kvm.h | 4 ++--
kvm-all.c| 10 --
kvm-stub.c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-m68k/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 3752094..2d73a
Use CPUState::env_ptr for now.
Needed for GdbState::c_cpu.
Signed-off-by: Andreas Färber
---
exec.c | 4 ++--
gdbstub.c | 9 +
include/exec/cpu-all.h | 6 --
include/qom/cpu.h | 6 ++
4 files changed, 13 insertions(+), 12 deletions(-)
diff --gi
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Signed-off-by: Andreas Färber
---
cpu-exec.c | 8 +++-
include/exec/exec-all.h | 3 ---
include/qemu/typedefs.h | 3 +++
include/qom/cpu.h | 1 +
target-alpha/cpu.h | 5 -
target-arm/cp
Since commit cb446ecab714b2444a270be209e0533bcd2ee534 (kvm: Change
cpu_synchronize_state() argument to CPUState), one was no longer
accessing CPUArchState, the other was just checking existence.
Signed-off-by: Andreas Färber
---
gdbstub.c | 10 +-
1 file changed, 5 insertions(+), 5 delet
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-sparc/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index eb6e800..
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-arm/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index af2aef2..9310c58
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber
---
target-moxie/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 92ca594..8e32584 100644
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn
cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no
longer needed.
Add documentation and make the functions available through qemu/log.h
outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h
was not
x86 was using additional CPU_DUMP_* flags, so make that configurable in
CPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Signed-off-by: Andreas Färber
---
include/qom/cpu.h | 2 ++
qom/cpu.c | 8
target-arm/cpu.c
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber
---
target-unicore32/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 6572f01..2e9
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