This updates the PCI IDE device emulation to use the explicit PCI DMA
wrapper to initialize its scatter/gathjer structure. This means this
driver should not need further changes when the sglist interface is
extended to support IOMMUs.
Signed-off-by: David Gibson
---
hw/ide/pci.c | 19
Alexander Graf writes:
> On 30.10.2011, at 15:30, Stefan Weil wrote:
>
>> Am 30.10.2011 14:41, schrieb Alexander Graf:
>>> On 30.10.2011, at 13:07, Stefan Weil wrote:
Valgrind is a tool which can automatically detect many kinds of bugs.
Running QEMU on Valgrind with x86_64 hosts w
A while back, Eduard - Gabriel Munteanu send a series of patches
implementing support for emulating the AMD IOMMU in conjunction with
qemu emulated PCI devices. A revised patch series added support for
the Intel IOMMU, and I also send a revised version of this series
which added support for the hy
Alexander Graf writes:
> On 30.10.2011, at 13:07, Stefan Weil wrote:
>
>> Valgrind is a tool which can automatically detect many kinds of bugs.
>>
>> Running QEMU on Valgrind with x86_64 hosts was not possible because
>> Valgrind aborts when memalign is called with an alignment larger than
>> 1
Pavel Borzenkov writes:
> Signed-off-by: Pavel Borzenkov
> ---
> Note, that almost all code in the file violates CODING STYLE. The changed
> lines
> are written wrt CODING STYLE (like commits 7d7d975c and c32d766a).
>
> ---
>
> cmd.c | 11 +++
> 1 files changed, 3 insertions(+), 8 de
Please thread together your patches so that the parts appear as replies
to the cover letter. git-send-email should do that by default.
Why? Disconnected parts can easily get separated in the list. When
that happens, your reviewers need to hunt for parts. They may choose to
review something els
Luiz Capitulino writes:
> A simple migration reproduces it:
>
> 1. Start the source VM with:
>
># qemu [...] -S
>
> 2. Start the destination VM with:
>
># qemu -incoming tcp:0:
>
> 3. In the source VM:
>
>(qemu) migrate -d tcp:0:
>
> 4. The source VM will segfault as soon as
tcg/ppc64/tcg-target.c has a couple of places where variables are set
unconditionally, but otherwise used only for softmmu builds, not
userspace only builds. This causes compiler warnings (which are fatal
by default) when compiling for a ppc64 host with gcc 4.6. This patch
fixes the problem by mo
On Sun, Oct 30, 2011 at 07:52:54PM +0200, Michael S. Tsirkin wrote:
> On Sun, Oct 30, 2011 at 06:20:46PM +0100, Alexander Graf wrote:
> >
> > On 14.10.2011, at 11:20, David Gibson wrote:
> >
> > > A while back, Eduard - Gabriel Munteanu send a series of patches
> > > implementing support for emul
On 28 October 2011 11:55, Peter Maydell wrote:
> From: Mathieu Sonet
>
> This driver emulates the ARM AACI interface (PL041) connected to a LM4549
> codec.
> It enables audio playback for the Versatile/PB platform.
Thanks, pushed both changes.
Cheers
Good points below. I forgot to CC Nish, the original patch author on
my post, so I've added him to the list now.
Nish, can you correct these problems and resend the patch please?
On Mon, Oct 31, 2011 at 04:35:54AM +0100, Alexander Graf wrote:
>
> On 31.10.2011, at 04:16, David Gibson wrote:
>
On 30.10.2011, at 21:22, Alexander Graf wrote:
> Hi Blue,
>
> This is my current patch queue for ppc. Please pull.
>
> Alex
>
>
> The following changes since commit 375847a6c0330e3de0fd1589eeb5a364692b791e:
> Max Filippov (1):
>MAINTAINERS: update wiki URL and machine names for targe
From: David Gibson
This patch adds a PCI bus to the pseries machine. This instantiates
the qemu generic PCI bus code, advertises a PCI host bridge in the
guest's device tree and implements the RTAS methods specified by PAPR
to access PCI config space. It also sets up the memory regions we
need
From: David Gibson
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU. A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG. So far, these are only
used to hand
On 31.10.2011, at 04:16, David Gibson wrote:
> This patch adds a PCI bus to the pseries machine. This instantiates
> the qemu generic PCI bus code, advertises a PCI host bridge in the
> guest's device tree and implements the RTAS methods specified by PAPR
> to access PCI config space. It also s
On 31.10.2011, at 04:16, David Gibson wrote:
> The CPU state contains two bitmaps, initialized from the CPU spec
> which describes which instructions are implemented on the CPU. A
> couple of bits are defined which cover instructions (VSX and DFP)
> which are not currently implemented in TCG. S
On 27.10.2011, at 23:15, Richard Henderson wrote:
> If the deposit replaces the entire word, optimize to a move.
>
> If we're inserting to the top of the word, avoid the mask of arg2
> as we'll be shifting out all of the garbage and shifting in zeros.
>
> If the host is 32-bit, reduce a 64-bit
On 31.10.2011, at 04:16, David Gibson wrote:
> From: Nishanth Aravamudan
>
> When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
> qemu monitor reports "dump_mmu: unimplemented". However, during
> bringup work, it can be quite handy to have the SLB entries, which are
> availabl
A basic wildcard matching is supported in both the monitor command
"trace-event" and the events list file. That means you can enable/disable
the events having a common prefix in a batch. For example, virtio-blk trace
events could be enabled using:
trace-event virtio_blk_* on
Signed-off-by: Mar
This patch adds a PCI bus to the pseries machine. This instantiates
the qemu generic PCI bus code, advertises a PCI host bridge in the
guest's device tree and implements the RTAS methods specified by PAPR
to access PCI config space. It also sets up the memory regions we
need to provide windows in
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU. A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG. So far, these are only
used to handle the case of -cpu h
From: Nishanth Aravamudan
When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
qemu monitor reports "dump_mmu: unimplemented". However, during
bringup work, it can be quite handy to have the SLB entries, which are
available in the CPUPPCState. This patch adds an implementation of
Here are several more updates for the ppc target and the pseries
machine in particular. This obsoletes the earlier copies of the first
two patches I sent today.
The first patch more correctly handles CPU features which are present
on some CPUs we know about, but which are not yet emulated in TCG.
It is better to use qiov.size in qed-table.c to get nb_sectors than iov.iov_len.
Signed-off-by: Zhi Yong Wu
---
block/qed-table.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/block/qed-table.c b/block/qed-table.c
index f31f9ff..8ee8443 100644
--- a/block/qed-tabl
On Fri, Oct 28, 2011 at 7:46 PM, Lucas Meneghel Rodrigues
wrote:
> On 10/27/2011 11:17 PM, Zhi Yong Wu wrote:
>>
>> On Fri, Oct 28, 2011 at 2:57 AM, Lucas Meneghel Rodrigues
>> wrote:
>>>
>>> On 10/27/2011 05:17 AM, Stefan Hajnoczi wrote:
On Wed, Oct 26, 2011 at 03:19:17PM -0200, Lucas
The Buildbot has detected a new failure on builder default_x86_64_fedora16
while building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_fedora16/builds/71
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_fedora
On Sun, Oct 30, 2011 at 6:44 PM, Richard Davies
wrote:
> Hi,
>
> I've been following the evolution of this patch with great interest for use
> in our qemu-kvm based IaaS public cloud.
>
> I am not a qemu developer, but have watched this patch go through many
> rounds of review and we are very much
Hi folks, sending this to QEMU devel to inform the current problems we
are able to reproduce on the current master branch.
So, qemu.git is presenting problems as of latest master. None of the
problems mentioned is happening on qemu-kvm.git.
Original Message
Subject: Autotest
On Fri, Oct 28, 2011 at 01:31:20PM +0100, Stefan Hajnoczi wrote:
>Subject: Re: [Qemu-devel] [PATCH v2] block: avoid SIGUSR2
>From: Stefan Hajnoczi
>To: Zhi Yong Wu
>Cc: Paolo Bonzini , Lucas Meneghel Rodrigues
> , aligu...@us.ibm.com, Stefan Hajnoczi
> , qemu-devel@nongnu.org, Frediano Ziglio
> ,
This patch adds a PCI bus to the pseries machine. This instantiates
the qemu generic PCI bus code, advertises a PCI host bridge in the
guest's device tree and implements the RTAS methods specified by PAPR
to access PCI config space. It also sets up the memory regions we
need to provide windows in
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU. A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG. So far, these are only
used to handle the case of -cpu h
On Sun, Oct 30, 2011 at 04:19:51PM +0200, Avi Kivity wrote:
> On 10/30/2011 04:12 PM, Anthony Liguori wrote:
> > On 10/30/2011 09:02 AM, Avi Kivity wrote:
> >> This somewhat controversial patchset converts internal arithmetic in the
> >> memory API to 128 bits.
> >>
> >> It has been argued that wit
On Sun, Oct 30, 2011 at 06:06:51PM +0100, Alexander Graf wrote:
>
> On 28.10.2011, at 03:56, David Gibson wrote:
>
> > From: Alexey Kardashevskiy
> >
> > This patch adds a PCI bus to the pseries machine. This instantiates
> > the qemu generic PCI bus code, advertises a PCI host bridge in the
>
Luiz Capitulino wrote:
> A simple migration reproduces it:
>
> 1. Start the source VM with:
>
># qemu [...] -S
>
> 2. Start the destination VM with:
>
># qemu -incoming tcp:0:
>
> 3. In the source VM:
>
>(qemu) migrate -d tcp:0:
>
> 4. The source VM will segfault as soon as mi
On Sun, Oct 30, 2011 at 05:53:13PM +0100, Alexander Graf wrote:
>
> On 28.10.2011, at 03:56, David Gibson wrote:
>
> > kvmppc_read_int_cpu_dt() returns -1 on errors. However
> > kvmppc_host_cpu_def() assumes that it can use the return value
> > directly for setting the corresponding instruction s
Hello friend,
Great speakers are made not born and the best way to become one is by
emulating the masters. EASIER SAID THAN DONE, especially in Malaysia, but
not anymore.
That's because New York based international presentation, speaking and
media coach, TJ Walker is coming to Malaysia.
Thi
Am 18.10.2011 16:35, schrieb Juan Pineda:
>>> What command line do you use? If using the right arguments you
>>> shouldn't see a window at all. Are you maybe using -drive instead of
>>> -hda and that is not yet handled correctly?
>
> The boot volume dialog appears only when a hard disk file is not
From: David Gibson
The recent usage of MemoryRegion in kvm_ppc.h breaks builds with
CONFIG_USER_ONLY=y. This patch fixes it.
Signed-off-by: David Gibson
Signed-off-by: Alexander Graf
---
target-ppc/kvm_ppc.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-p
The sole reason we have the ppcemb target is to support MMUs that have
less than the usual 4k possible page size. There are very few of these
chips and I don't want to add additional QA and testing burden to everyone
to ensure that code still works when TARGET_PAGE_SIZE is not 4k.
So this patch di
We have several targets in the PPC tree now that basically require libfdt
to function properly, namely the pseries and the e500 targets. This dependency
will rather increase than decrease in the future, so I want to make sure
that people building shiny new 1.0 actually have libfdt installed to get
From: David Gibson
The pseries machine of qemu implements the TCE mechanism used as a
virtual IOMMU for the PAPR defined virtual IO devices. Because the
PAPR spec only defines a small DMA address space, the guest VIO
drivers need to update TCE mappings very frequently - the virtual
network devic
From: David Gibson
For convenience with kvm, x86 allows the user to specify -cpu host on the
qemu command line, which means make the guest cpu the same as the host
cpu. This patch implements the same option for ppc targets.
For now, this just read the host PVR (Processor Version Register) and
s
From: David Gibson
Sufficiently recent PAPR specifications define properties "ibm,vmx"
and "ibm,dfp" on the CPU node which advertise whether the VMX vector
extensions (or the later VSX version) and/or the Decimal Floating
Point operations from IBM's recent POWER CPUs are available.
Currently we
Hi Blue,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit 375847a6c0330e3de0fd1589eeb5a364692b791e:
Max Filippov (1):
MAINTAINERS: update wiki URL and machine names for target-xtensa
are available in the git repository at:
git://repo.or.
The -cpu host feature tries to find out the host capabilities based
on device tree information. However, we don't always have that available
because it's an optional property in dt.
So instead of force unsetting values depending on an unreliable source
of information, let's just try to be clever a
From: David Gibson
Now that we've implemented -cpu host for ppc, this patch updates the
pseries machine to use the host cpu as the guest cpu by default when
running under KVM. This is important because under KVM Book3S-HV the guest
cpu _cannot_ be of a different type to the host cpu (at the mome
Some 32-bit PPC CPUs can use up to 36 bit of physical address space.
Treat them accordingly in the qemu-system-ppc binary type.
Signed-off-by: Alexander Graf
---
configure|2 +-
target-ppc/cpu.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure b/con
From: David Gibson
Alex Graf has already made qemu support KVM for the pseries machine
when using the Book3S-PR KVM variant (which runs the guest in
usermode, emulating supervisor operations). This code allows gets us
very close to also working with KVM Book3S-HV (using the hypervisor
capabiliti
From: David Gibson
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3.
This allows -cpu host to be used on these host cpus.
Signed-off-by: David Gibson
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c |4
1 files changed, 4 insertions(+), 0 deletions
From: David Gibson
At present, using the hypervisor aware Book3S-HV KVM will only work
with qemu on POWER7 CPUs. PPC970 CPUs also have hypervisor
capability, but they lack the VRMA feature which makes assigning guest
memory easier.
In order to allow KVM Book3S-HV on PPC970, we need to specially
From: David Gibson
Currently the kvmppc_get_clockfreq() function reads the host's clock
frequency from /proc/device-tree, which is useful to past to the guest
in KVM setups. However, there are some other host properties
advertised in the device tree which can also be relevant to the
guests.
Thi
From: Fabien Chouteau
SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
for the first instruction, but the second one can have a different mask.
example:
GEN_SPE(efdcmpeq,efdcfs, 0x17, 0x0B, 0x0060, 0x0018,
PPC_SPE_DOUBLE),
Signed-off-by: Fabien Ch
From: David Gibson
In __cpu_ppc_store_decr(), we set up a regular timer used to trigger
decrementer interrupts. This is necessary to implement the decrementer
properly under TCG, but is unnecessary under KVM (true for both Book3S-PR
and Book3S-HV KVM variants), because the kernel handles generat
From: David Gibson
The ppc target contains a ppc_find_by_pvr() function, which looks up a
CPU spec based on a PVR (that is, based on the value in the target cpu's
Processor Version Register). PVR values contain information on both the
cpu model (upper 16 bits, usually) and on the precise revisio
From: David Gibson
This patch updates the SLOF submodule and precompiled image. The new
SLOF versions contains two changes of note:
* The previous SLOF has a bug in SCSI condition handling that was
exposed by recent updates to qemu's SCSI emulation. This update
fixes the bug.
* The pr
From: David Gibson
Sufficiently recent kernels include a KVM call to accelerate use of
PAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices.
This involves qemu mapping the TCE table in from a kernel obtained fd,
which currently we do with PROT_READ only. This is a hangover from
ear
From: David Gibson
Currently, when KVM is enabled, the pseries machine checks if the host
CPU supports VMX, VSX and/or DFP instructions and advertises
accordingly in the guest device tree. It does this regardless of what
CPU is selected on the command line. On the other hand, when in TCG
mode,
From: Liu Yu-B13201
Put trailing statements on next line.
Signed-off-by: Liu Yu
Reviewed-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/ppce500_pci.c | 76 +++--
1 files changed, 56 insertions(+), 20 deletions(-)
diff --git a/hw/ppc
From: Liu Yu-B13201
When access PPCE500_PCI_IW1 the previous index get overflow.
The patch fix the issue and update all to keep consistent style.
Signed-off-by: Liu Yu
Signed-off-by: Alexander Graf
---
hw/ppce500_pci.c | 38 ++
1 files changed, 22 inserti
On Sun, Oct 30, 2011 at 7:39 PM, 陳韋任 wrote:
> Hi, all
>
> I am looking into QEMU's implementation for ARM NEON instructions
> (target-arm/neon_helper.c). Some helper functions will do mask
> operation, neon_add_u8, for example. I thought simply adding a and b
> is enough and can't figure out why
On Sun 30 Oct 2011 07:21:13 PM IST, Blue Swirl wrote:
On Sun, Oct 30, 2011 at 16:51, Saggi Mizrahi wrote:
RFC: This is my suggestion for wrapping the block layer with another
supported API. I added only the bare bones verbs I think we can all agree
on.
It can be expected that the API will onl
LX60 carry 4 Mbyte FLASH and 128 Kbyte SRAM, LX200 carry 16 Mbyte FLASH
and 32 Mbyte SRAM. Either of these memories may be mapped to the system
ROM region.
Select boot from FLASH if -kernel option is not specified, otherwise
boot from SRAM.
Signed-off-by: Max Filippov
---
default-configs/xtensa
Max Filippov (3):
xtensa_lx60: add FLASH support
xtensa_lx60: pass kernel arguments from -append
xtensa_lx60: fix build date code and change memory region names
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
hw/xtensa_bootparam.h
Fix date code to uses MMDD notation.
Change memory region names to reflect specification that defines them.
Signed-off-by: Max Filippov
---
hw/xtensa_lx60.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 069b21c..8947
Create boot parameters in the end of SRAM region, insert kernel
arguments specified in -append there.
Signed-off-by: Max Filippov
---
hw/xtensa_bootparam.h | 25 +
hw/xtensa_lx60.c | 24
2 files changed, 45 insertions(+), 4 deletions(-)
On Mon, Oct 10, 2011 at 02:06:29PM +0800, Lai Jiangshan wrote:
> From: Kenji Kaneshige
>
> In the current seabios MP table description, NMI is connected only to
> BSP's LINT1. But usually NMI is connected to all the CPUs' LINT1 as
> indicated in MP specification. This patch changes seabios MP tab
On Sun, Oct 30, 2011 at 06:20:46PM +0100, Alexander Graf wrote:
>
> On 14.10.2011, at 11:20, David Gibson wrote:
>
> > A while back, Eduard - Gabriel Munteanu send a series of patches
> > implementing support for emulating the AMD IOMMU in conjunction with
> > qemu emulated PCI devices. A revise
On Sun, Oct 30, 2011 at 16:51, Saggi Mizrahi wrote:
> RFC: This is my suggestion for wrapping the block layer with another
> supported API. I added only the bare bones verbs I think we can all agree
> on.
It can be expected that the API will only grow: file descriptor
versions, async APIs, thread
On 14.10.2011, at 11:20, David Gibson wrote:
> A while back, Eduard - Gabriel Munteanu send a series of patches
> implementing support for emulating the AMD IOMMU in conjunction with
> qemu emulated PCI devices. A revised patch series added support for
> the Intel IOMMU, and I also send a revise
On 28.10.2011, at 03:56, David Gibson wrote:
> Sufficiently recent kernels include a KVM call to accelerate use of
> PAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices.
> This involves qemu mapping the TCE table in from a kernel obtained fd,
> which currently we do with PROT_READ
On 28.10.2011, at 03:56, David Gibson wrote:
> From: Alexey Kardashevskiy
>
> This patch adds a PCI bus to the pseries machine. This instantiates
> the qemu generic PCI bus code, advertises a PCI host bridge in the
> guest's device tree and implements the RTAS methods specified by PAPR
> to ac
On 28.10.2011, at 03:56, David Gibson wrote:
> kvmppc_read_int_cpu_dt() returns -1 on errors. However
> kvmppc_host_cpu_def() assumes that it can use the return value
> directly for setting the corresponding instruction support bits. This
> will give invalid results when kvmppc_read_int_cpu_dt()
RFC: This is my suggestion for wrapping the block layer with another
supported API. I added only the bare bones verbs I think we can all agree
on.
Apart from the API please also comment on the Makefile. I kinda stitched
it up and I will appreciate comments on it as well.
libvdisk is a library tha
Some distributions use lib64 directories for 64 bit libraries. Currently
configure would always generate libdir as $PREFIX/lib. By checking if
the current distro has a /lib64 directory we can assume it is using this
convention.
Signed-off-by: Saggi Mizrahi
---
configure |3 +++
1 files chang
On 26.10.2011, at 18:59, Richard Henderson wrote:
> Use target_ulong instead of hard-coded uint32_t.
> Remove the disabled printf's that are redundant with -strace.
>
> Signed-off-by: Richard Henderson
Acked-by: Alexander Graf
Riku, do you want to take these in or should I?
Alex
On 26.10.2011, at 18:59, Richard Henderson wrote:
> Don't confuse the load address with the load bias. They're equal
> for ET_DYN objects (i.e. ld.so) but different for ET_EXEC objects
> (i.e. statically linked).
>
> Signed-off-by: Richard Henderson
Acked-by: Alexander Graf
Alex
On 26.10.2011, at 11:16, q...@buildbot.b1-systems.de wrote:
> The Buildbot has detected a new failure on builder default_s390 while
> building qemu.
> Full details are available at:
> http://buildbot.b1-systems.de/qemu/builders/default_s390/builds/49
>
> Buildbot URL: http://buildbot.b1-systems
On 25.10.2011, at 16:00, Juan Quintela wrote:
> Added sdr1_vmstate because storing the value requires calling
> ppc_store_sdr1().
> The position when the function is called also changes (I think it is save).
Thanks for converting this. I'm fairly sure that vmsave is broken atm anyways
and that
Signed-off-by: Avi Kivity
---
hw/pl031.c | 30 ++
1 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/hw/pl031.c b/hw/pl031.c
index 017a313..4ff96f9 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -32,6 +32,7 @@
typedef struct {
SysBusDevice busdev;
Signed-off-by: Avi Kivity
---
hw/pl061.c | 27 ++-
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/pl061.c b/hw/pl061.c
index d13746c..ce139cd 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -30,6 +30,7 @@
typedef struct {
SysBusDevice busdev;
+
Signed-off-by: Avi Kivity
---
hw/pl080.c | 27 ++-
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/pl080.c b/hw/pl080.c
index 5ba3b08..1efd3bd 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -37,6 +37,7 @@
typedef struct {
SysBusDevice busdev;
+
Signed-off-by: Avi Kivity
---
hw/jazz_led.c | 25 ++---
hw/mips.h |4 +++-
hw/mips_jazz.c |2 +-
3 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index eb472a0..6fab334 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
Signed-off-by: Avi Kivity
---
hw/pl181.c | 26 ++
1 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/hw/pl181.c b/hw/pl181.c
index 0943c09..e13ea8e 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -24,6 +24,7 @@
typedef struct {
SysBusDevice busdev;
+
If you expect anything interesting here, you're looking at the wrong place.
Nevertheless, please review.
Avi Kivity (17):
tosa: convert to memory API
versatilepb: convert to memory API
vexpress: convert to memory API
virtex_ml507: convert to memory API
shix: convert to memory API
jazz_
Signed-off-by: Avi Kivity
---
hw/pl011.c | 27 ++-
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/pl011.c b/hw/pl011.c
index 707a161..9cf6dea 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -12,6 +12,7 @@
typedef struct {
SysBusDevice busdev;
+
Signed-off-by: Benoit Canet
---
hw/pxa.h|4 ++--
hw/pxa2xx.c |4 ++--
hw/pxa2xx_lcd.c | 32 ++--
3 files changed, 18 insertions(+), 22 deletions(-)
diff --git a/hw/pxa.h b/hw/pxa.h
index 15ac760..e778739 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -7
Convert mechanicaly; the access size of the old_mmio fields
seems odd.
Signed-off-by: Benoit Canet
---
hw/pxa.h |3 ++-
hw/pxa2xx.c |4 ++--
hw/pxa2xx_mmci.c | 31 ---
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/hw/pxa.h b/h
The ARM documentation say transfers between the cpu and the
coprocessor are 32 bits wide.
Use 4 as size for coprocessor read and writes.
Signed-off-by: Benoit Canet
---
hw/pxa2xx_pic.c | 31 +--
1 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/hw/pxa
Signed-off-by: Benoit Canet
---
hw/pxa.h |3 ++-
hw/pxa2xx.c|8
hw/pxa2xx_pcmcia.c | 33 +++--
3 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/hw/pxa.h b/hw/pxa.h
index 7e98384..fe99a50 100644
--- a/hw/pxa.h
+++ b/h
Signed-off-by: Avi Kivity
---
hw/pl022.c | 29 +++--
1 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/hw/pl022.c b/hw/pl022.c
index 9a1cb71..e0cf2b0 100644
--- a/hw/pl022.c
+++ b/hw/pl022.c
@@ -42,6 +42,7 @@
typedef struct {
SysBusDevice busdev;
+
Signed-off-by: Avi Kivity
---
hw/zaurus.c | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/zaurus.c b/hw/zaurus.c
index 0eeacf7..3c27cd8 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -28,6 +28,7 @@
struct ScoopInfo {
SysBusDevice busdev;
Signed-off-by: Avi Kivity
---
hw/pl110.c | 27 ++-
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/pl110.c b/hw/pl110.c
index 4ac710a..fbbcb2e 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -40,6 +40,7 @@ enum pl110_version
typedef struct {
SysBu
Signed-off-by: Avi Kivity
---
hw/versatilepb.c | 35 +++
1 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 68402cc..38e8e7a 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -17,12 +17,14 @@
#include
Signed-off-by: Avi Kivity
---
hw/pl050.c | 27 ++-
1 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/pl050.c b/hw/pl050.c
index f7fa2e2..dedd622 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -12,6 +12,7 @@
typedef struct {
SysBusDevice busdev;
+
Signed-off-by: Avi Kivity
---
hw/virtex_ml507.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index d31a204..5313e2e 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -192,7 +192,7 @@ static void virtex_init(ram_addr_t
Signed-off-by: Avi Kivity
---
hw/mips_jazz.c |3 ++-
hw/parallel.c | 27 ---
hw/pc.h|3 ++-
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 6e657dd..f6e3316 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_
Signed-off-by: Benoit Canet
---
hw/pxa2xx_timer.c | 27 +++
1 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index 4235e42..0c8e0d3 100644
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -81,6 +81,7 @@ typedef stru
On 10/30/2011 04:59 PM, Blue Swirl wrote:
> >
> > There is no direct use of signed arithmetic in the API (just in the
> > implementation). Aliases can cause a region to move in either the
> > positive or negative direction, and this requires either signed
> > arithmetic or special casing the two d
Signed-off-by: Avi Kivity
---
hw/tosa.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/tosa.c b/hw/tosa.c
index b992b99..67a71fe 100644
--- a/hw/tosa.c
+++ b/hw/tosa.c
@@ -208,6 +208,7 @@ static void tosa_init(ram_addr_t ram_size,
const char *ini
RAM wasn't actually allocated, only used, so fix that as well.
Signed-off-by: Avi Kivity
---
hw/shix.c | 14 +++---
1 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/shix.c b/hw/shix.c
index dbf4764..670ddb5 100644
--- a/hw/shix.c
+++ b/hw/shix.c
@@ -32,6 +32,7 @@
#in
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