Li, Aubrey wrote:
Hi Jonathan,
Do you have any comments about this proposal?
Thanks,
-Aubrey
Li, Aubrey wrote:
Jonathan Chew wrote:
Thanks for summarizing the metrics. However, I wanted to see a summary
of the overall NUMAtop proposal given the feedback that you have gotten,
so I
anything of these changed given the feedback that you have gotten?
Can you please summarize your latest project proposal including the
description, phases, metrics, and anything else that is useful for
understanding what the project is proposing to do?
Jonathan
Jonathan Chew wrote:
There
There has been a lot of discussion on this since it was proposed last
month. I want to know what is currently being proposed given the
lengthy discussion.
Can someone please summarize what the current proposal is now?
Jonathan
Li, Aubrey wrote:
johansen wrote:
On Tue, Jan 12, 2010 at
johan...@sun.com wrote:
On Thu, Jul 09, 2009 at 12:18:17PM -0500, Bob Friesenhahn wrote:
Do madvise() options like MADV_ACCESS_LWP and MADV_ACCESS_MANY work on
memory allocated via malloc()? If MADV_ACCESS_LWP is specified and
malloc() hands out heap memory which has been used before (e.g
n long ago, I remember the v890 has some NUMA
characteristics, but I don't honestly know if we treat it like a NUMA
machine. Jonathan Chew, who's lurking on the list somewhere, might have
more details.
Lurking?! Who me? I'm innocent. ;-)
I think that Paul already replied an
Eric Saxe wrote:
Eric Saxe wrote:
Also, in the past I've acted as de facto facilitator for this
community...but we've never had a vote around that (at least not one
that I remember).
Are you interested Krister? If so, I nominate you. :)
Krister has accepted my nomination for community facili
+1
Jonathan
Eric Saxe wrote:
> I'd like to put forth a contributer grant nomination for Chad Mynhier,
> for his recent contributions in the area of performance observability,
> including contributing fixes for:
>
> PSARC 2007/598 ptime(1) Improvements
> 6234106 ptime should report microseconds
Eric Saxe wrote:
> johan...@sun.com wrote:
>
>> I'm going to begin this process by voting in favor of renewing akolb,
>> barts, esaxe, johansen, jjc, mpogue, and dp. If andrei or rmc are still
>> interested in participating, I would support renewing their grants. I
>> simply haven't seen any t
Stefan Parvu wrote:
>
>> For papers and books on this, start with the
>> Teamquest site and view their webinar
>> http://teamquest.com/resources/webinars/display/30/index.htm
>> and if you don't mind math, follow up with Neil
>> Gunther's site, http://www.perfdynamics.com/
>>
>
> Right. I have
Manfred Mücke wrote:
> Hi,
>
> I want to enforce migration of thread+allocated memory to another lgroup but
> failed for some threads.
>
Ok. You can give MADV_ACCESS_LWP as the advice to madvise(3C) for the
memory that you want to migrate. This advice tells the Solaris kernel
that the next
OpenSolaris community, on this subject.
That sounds great!
Can you please tell me more about your work or point me at any relevant
papers or docs?
Jonathan
>
>
> Jonathan Chew wrote:
>> I would like to get sponsorship from the OpenSolaris performance
>> community to h
pproved
> Thanks for taking the time to get these projects proposed and into
> OpenSolaris.
>
Sure. No problem. It is long overdue.
Jonathan
> On Fri, Aug 15, 2008 at 03:22:10PM -0700, Jonathan Chew wrote:
>
>> Thanks for the pointers.
>>
>> Here
Thanks for the pointers.
Here are my revised proposals.
Jonathan
[EMAIL PROTECTED] wrote:
Hi Jonathan,
I'm in favor of both of these proposals. However, I think they're
incomplete, at least according to the project instantiation guidelines.
Would you amend these proposals to include the pa
I would like to get sponsorship from the OpenSolaris performance
community to host a NUMA project.
The "Memory Placement Optimization" feature in Solaris has been around
since Solaris 9 and has had web pages in the OpenSolaris performance
community since it started before OpenSolaris projects e
I would like to get sponsorship from the OpenSolaris performance
community to host a CMT project which will focus on observability,
performance enhancements, and potentially more in OpenSolaris for Chip
Multi-Threaded (CMT) processors (including SMT, CMP, etc.).
Specifically, the project will t
Eric Saxe wrote:
> Great suggestions. Richard is already a core contributer in the community.
> I would like to nominate Jim Mauro and Adrian Cockcroft for core
> contributer grants.
>
> Both Adrian and Jim have long standing track records of great
> contributions in the area of Solaris performan
Eric Saxe wrote:
> I'd like to nominate Aubrey Li for a contributer grant in our community.
>
> Aubrey has made (and continues to make) tremendous contributions to the
> perf community sponsored OpenSolaris Tesla project though his code and
> design contributions to the OpenSolaris PowerTop port,
Eric Saxe wrote:
> I'd like to nominate Sherry Moore for a core contributer grant in our
> community.
>
> Sherry is the tech lead for the community sponsored "Enable/Enhance
> Solaris support for Intel Platform" project, and is a Senior Staff
> Engineer in the Solaris Kernel group. Her contribut
Bill Holler wrote:
> I'd like to nominate Robert Kasten for a contributor grant in our community.
>
> Robert has made (and continues to make) tremendous contributions to the
> perf community sponsored OpenSolaris Intel-platform Project.
> He provides code drops for performance improvements and
Sherry Moore wrote:
> I'd like to nominate Ashok Raj for a contributor grant in our community.
>
> Ashok has made (and continues to make) tremendous contributions to the
> perf community sponsored OpenSolaris Intel-platform Project. He not
> only provides code drops for new features and perfor
Rayson Ho wrote:
> On Dec 11, 2007 9:33 PM, Jonathan Chew <[EMAIL PROTECTED]> wrote:
>
>> Yes. If you're interested, there is also an update to that presentation at
>>
>
> I think I've read that one too, and the chapter in the Solaris
>
Rayson Ho wrote:
> On Dec 11, 2007 5:53 PM, Jonathan Chew <[EMAIL PROTECTED]> wrote:
>
>> No, not currently. It just assumes that there is some interconnect
>> between the nodes and may know the latency between them when the system
>> is not loaded.
>>
Rafael Vanoni wrote:
> Hey everyone
>
> Is the kernel aware of the status of the interconnect between different
> NUMA nodes ?
>
No, not currently. It just assumes that there is some interconnect
between the nodes and may know the latency between them when the system
is not loaded.
> For
Ostrovsky, Boris wrote:
> I would like to propose creation of a new project titled "Solaris
> Enhancements for AMD-based Platforms".
>
> The project will address various features that are specific to platforms
> based on AMD processors, such as
> - IOMMU support
> - NUMA topology, parti
Eric Saxe wrote:
I'd like the ask the OpenSolaris performance community for sponsorship
of Project Tesla.
http://www.opensolaris.org/os/project/tesla
The Tesla project seeks to provide OpenSolaris with a platform
independent power management policy architecture,
bringing power awareness to
Henrik Loef wrote:
Hi,
I'm trying to repeat some old experiments I did a couple of months ago an a SF15K machine. We used kstats (module lgrp: "pages migrated to","pages migrated from") to measure the number of pages migrated using madvise(). The domain we used for our previous experiments has
I have to give a presentation to update our Platform Software
Architecture Review Committee (PSARC) on MPO and thought that this might
be a good time to let others in the OpenSolaris (performance) community
to comment too.
The presentation is based on the MPO overview in:
http://www.openso
Marc Rocas wrote On 09/27/05 21:27,:
>
> On 9/26/05, *jonathan chew* <[EMAIL PROTECTED]
> <mailto:[EMAIL PROTECTED]>> wrote:
>
>
> There may be a slightly better way to allocate memory from the lgroup
> containing the least significant physical memory us
; wrote:
Eric, Bart, and Jonathan,
Thanks for your quick replies. See my comments below:
On 9/16/05, *jonathan chew* < [EMAIL PROTECTED]
<mailto:[EMAIL PROTECTED]>> wrote:
Marc Rocas wrote:
I've been playing around with the tools on a Stinger box and
Joe Bonasera wrote:
The x86 HAT (D)ISM code is tricky. Here's why:
pagesize is 4K, a large page is 2Meg (usually).
So a pagetable covers either an entire 512 4K pages
aligned at 2M or 512 2M pages aligned at 1Gig.
To share a page table, the (D)ISM segment has to be
either a multiple of (512
Joe Bonasera wrote:
jonathan chew wrote:
It sounds like Eric Lowe has a theory as to why
madvise(MADV_ACCESS_*) and pmadvise(1) didn't work for migrating your
ISM segment. Joe and Nils are experts on the x86/AMD64 HAT and may
be able to comment on Eric's theory that the lack
Solaris community try them first to
see whether they are useful.
Last but not least, we can try running your application if you want.
Jonathan
-----Original Message-
From: jonathan chew [mailto:[EMAIL PROTECTED]
Sent: Friday, September 09, 2005 6:08 PM
To: David McDaniel (damcdani)
Cc: Er
PPS
I forgot to ask what you did to test whether pmadvise(1) would migrate
your ISM segment and how you know that it didn't.
jonathan chew wrote:
Marc Rocas wrote:
I've been playing around with the tools on a Stinger box and I think
their pretty cool!
I'm glad that you
Marc Rocas wrote:
I've been playing around with the tools on a Stinger box and I think
their pretty cool!
I'm glad that you like them. We like them too and think that they are
fun to play with besides being useful for observability and
experimenting with performance. I hope that our MPO o
server so there is no
stuff of a casueal nature, however there is a lot of what I'll glom into
the category of "support" tasks, ie ntp daemons, nscd flushing caches,
fsflush running around backing up pages, etc. Was that what you meant?
-Original Message-
From: jonathan chew
't use a psrset?
Jonathan
-Original Message-
From: jonathan chew [mailto:[EMAIL PROTECTED]
Sent: Thursday, September 01, 2005 11:50 AM
To: David McDaniel (damcdani)
Cc: Eric C. Saxe; perf-discuss@opensolaris.org
Subject: Re: [perf-discuss] Re: Puzzling scheduler behavior
Dave,
It sou
Dave,
It sounds like you have an interesting application. You might want to
create a processor set, leave some CPUs outside the psrset for other
threads to run on, and run your application in a processor set to
minimize interference from other threads. As long as there are enough
CPUs for y
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