Rayson Ho wrote: > On Dec 11, 2007 9:33 PM, Jonathan Chew <[EMAIL PROTECTED]> wrote: > >> Yes. If you're interested, there is also an update to that presentation at >> > > I think I've read that one too, and the chapter in the Solaris > Internals book... all 3 are interesting :-D > > > >> Thanks for the pointers. I had the funny feeling that Opteron would >> have counters for this, but I'm not so sure about SPARC and what will be >> available on Intel's Nehalem processors with QuickPath. >> > > Don't know about what QuickPath will have (hmm... "QuickPath" seems to > be new to me, as I was so used to the old "CSI" name). However, as it > will support Nehalem as well as Tukwila, it may be interesting to see > what is currently available for Itanium-2: >
Yes, that seems likely. I believe that Nehalem may very well inherit some CPU hardware performance counters, etc. from existing Intel processors. > ... we use the PMU to capture two different types of memory access > data -- long latency loads and data translation lookaside buffer > (DTLB) misses -- section 3: Profile Generation > > "Hardware Profile-guided Automatic Page Placement for ccNUMA Systems" > http://moss.csc.ncsu.edu/~mueller/ftp/pub/mueller/papers/ppopp06.pdf > > And the Gelato ICE presentation: > http://www.ice.gelato.org/apr07/pres_pdf/gelato_ICE07apr_pageplacement_mueller_ncsu.pdf > Thanks for the pointer to the paper and presentation. I only glanced through them, but they seem very similiar in spirit to page migration work that was done in the 1990's by some friends at Rochester, Stanford, and SGI. In fact, I thought that IRIX had some sort of automatic page migration which may have used hardware performance counters to help decide what to migrate where. Jonathan _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
