Rayson Ho wrote: > On Dec 11, 2007 5:53 PM, Jonathan Chew <[EMAIL PROTECTED]> wrote: > >> No, not currently. It just assumes that there is some interconnect >> between the nodes and may know the latency between them when the system >> is not loaded. >> > > Jonathan, I just found out that you are the author of the MPO (Memory > Placement Optimization) presentation: > > http://www.opensolaris.org/os/community/performance/mpo_overview.pdf >
Yes. If you're interested, there is also an update to that presentation at: http://www.opensolaris.org/os/community/performance/numa/mpo_update.pdf >> There may be hardware performance counters that provide some >> observability for this. I'm not sure though and it definitely would >> depend on the processor and platform. >> > > I was looking at the same thing too, but from an application > developer's perspective. I then talked to my AMD friend, and he told > me that CodeAnalyst provides a way to measure the HT bandwidth: > > "HyperTransport link x transmit bandwidth" -- HT links 0, 1, and > 2 (i.e., whether they're used for cache-coherence inter-processor > traffic, or used for non-coherent I/O) > > And I read this document a while ago: > "Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™ ccNUMA > Multiprocessor Systems Application Note" > http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40555.pdf > Thanks for the pointers. I had the funny feeling that Opteron would have counters for this, but I'm not so sure about SPARC and what will be available on Intel's Nehalem processors with QuickPath. Jonathan _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
