Re: [perf-discuss] V890 with US-IV+ : which core should interrupts be delivered to?

2009-06-19 Thread Jonathan Chew
johan...@sun.com wrote: On Fri, Jun 19, 2009 at 05:52:02PM +0200, Nils Goroll wrote: I am trying to reduce context switches on a V890 with 16 cores by delegating one core to interrupt handling (by setting all others to nointr using psradm). The best way to do this is to create process

Re: [perf-discuss] V890 with US-IV+ : which core should interrupts be delivered to?

2009-06-19 Thread Paul Riethmuller - PAE
Nils, the V890 and all other US-III/IV machines except for the E10K/E25K are Uniform Memory Access with respect to I/O, so it should not matter which CPU/core you select. This is because all memory is connected to on-CPU memory controllers and the IO bridge chip (Schizo, pcisch) transacts on the

Re: [perf-discuss] V890 with US-IV+ : which core should interrupts be delivered to?

2009-06-19 Thread johansen
On Fri, Jun 19, 2009 at 05:52:02PM +0200, Nils Goroll wrote: > I am trying to reduce context switches on a V890 with 16 cores by > delegating one core to interrupt handling (by setting all others to > nointr using psradm). The best way to do this is to create processor sets, with the set that ha

[perf-discuss] V890 with US-IV+ : which core should interrupts be delivered to?

2009-06-19 Thread Nils Goroll
Hi, I am trying to reduce context switches on a V890 with 16 cores by delegating one core to interrupt handling (by setting all others to nointr using psradm). Does the hardware design of this machine imply that (a) particular core(s) is best suited for this task? Thanks, Nils ___