DWMAC")
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> b/dr
able_interrupts), with
> equivalent functionality.
>
> This means that clearing interrupts now becomes something that the PHY
> driver is responsible of doing, before enabling interrupts and after
> clearing them. Make this driver follow the new contract.
>
> Cc: Jerome Brunet
&
On Thu, 2018-04-26 at 16:05 +, Yixun Lan wrote:
> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
> is extended from bit[0] to bit[2:0].
> There is no problem if we configure it to the RGMII 1000M PHY mode,
> since the register setting is coincidentally compatible w
On Tue, 2019-02-19 at 20:41 +0100, Simon Huelck wrote:
> Am 19.02.2019 um 09:47 schrieb Jose Abreu:
> > Hi Simon,
> >
> > On 2/18/2019 6:05 PM, Simon Huelck wrote:
> > > disabling EEE doesnt help ( did it via the entry in the .dtb / .dts ),
> > > the results are the same. I can confirm the LPI cou
On Thu, 2019-02-21 at 18:27 +0100, Simon Huelck wrote:
> Hi,
>
>
>
> this was changed recently, with a patch for the EEE stuff , see here:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.0-rc7&id=e35e26b26e955c53e61c154ba26b9bb15da6b858
Hu, I was not aware t
ned-off-by: Jerome Brunet
---
drivers/net/phy/mdio-mux-meson-g12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/mdio-mux-meson-g12a.c
b/drivers/net/phy/mdio-mux-meson-g12a.c
index 6fa29ea8e2a3..6644762ff2ab 100644
--- a/drivers/net/phy/mdio-mux-meson-g1
If we fail to register the mdio bus due to probe defer, we should not
print an error message. Just be silent in this case.
Signed-off-by: Jerome Brunet
---
drivers/net/phy/mdio-mux-mmioreg.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/mdio-mux
On Fri, 2018-05-18 at 14:55 +0100, Jose Abreu wrote:
> This is cutting down performance. Once the timer is armed it should run
> after the time expires for the first packet sent and not the last one.
>
> After this change, running iperf, the performance gain is +/- 24%.
Hi Guys,
Since v4.18, we
On Thu, 2018-08-30 at 11:37 +0100, Jose Abreu wrote:
> [ As for now this is only for testing! ]
>
> This follows David Miller advice and tries to fix coalesce timer in
> multi-queue scenarios.
>
> We are now using per-queue coalesce values and per-queue TX timer. This
> assumes that tx_queues ==
On Mon, 2018-09-03 at 10:36 +0100, Jose Abreu wrote:
> Hi Jerome,
>
> On 03-09-2018 09:56, Jerome Brunet wrote:
> > On Thu, 2018-08-30 at 11:37 +0100, Jose Abreu wrote:
> > > [ As for now this is only for testing! ]
> > >
> > > This follows David Miller
he coalesce frames
> to 25.
>
> Tested in B2B setup between XGMAC2 and GMAC5.
>
> Signed-off-by: Jose Abreu
> Cc: Jerome Brunet
> Cc: Martin Blumenstingl
> Cc: David S. Miller
> Cc: Joao Pinto
> Cc: Giuseppe Cavallaro
> Cc: Alexandre Torgue
> ---
> J
On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote:
> On 03-09-2018 11:16, Jerome Brunet wrote:
> > No notable change. Rx is fine but Tx:
> > [ 5] 3.00-4.00 sec 3.55 MBytes 29.8 Mbits/sec 51 12.7 KBytes
> >
> > I suppose the problem as something to do with
On Mon, 2018-09-03 at 16:22 +0100, Jose Abreu wrote:
> On 03-09-2018 15:10, Jerome Brunet wrote:
> > On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote:
> > > On 03-09-2018 11:16, Jerome Brunet wrote:
> > > > No notable change. Rx is fine but Tx:
> > > >
On Mon, 2018-09-03 at 16:19 +0100, Jose Abreu wrote:
> On 03-09-2018 15:07, Jerome Brunet wrote:
> >
> > You had it on what you sent in the RFT, but this different.
>
> Yeah, I had to fix the logic where tx queues != rx queues...
>
> >
> > Like with the RFT
On Mon, 2018-09-03 at 16:47 +0100, Jose Abreu wrote:
> On 03-09-2018 16:38, Jerome Brunet wrote:
> > On Mon, 2018-09-03 at 16:22 +0100, Jose Abreu wrote:
> > > On 03-09-2018 15:10, Jerome Brunet wrote:
> > > > On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote:
On Tue, 2018-09-04 at 10:57 +0100, Jose Abreu wrote:
> Hi Jerome,
>
> On 03-09-2018 17:22, Jerome Brunet wrote:
> >
> > Situation is even worse with this.
> > I'm using an NFS root filesystem. With your fixup, I'm not reaching the
> > prompt
> &g
On Thu, 2018-09-13 at 09:02 +0100, Jose Abreu wrote:
> The fix for coalesce timer and a fix in tail address setting that impacts
> XGMAC2 operation.
>
> Cc: Florian Fainelli
> Cc: Neil Armstrong
> Cc: Jerome Brunet
> Cc: Martin Blumenstingl
> Cc: David S. Miller
f 1000MHz (and thus is divisible cleanly
> to 250MHz and 25MHz).
>
> Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson
> 8b / GXBB DWMAC")
> Reported-by: Emiliano Ingrassia
> Signed-off-by: Martin Blumenstingl
Makes sense to add ROUND_CLOSEST (no risk if the rate is slightly over the
requested one)
Reviewed-by: Jerome Brunet
On Sat, 2017-12-23 at 18:04 +0100, Martin Blumenstingl wrote:
> Trying to set the rate of m250_div's parent clock makes no sense since
> it's a mux which has neither CLK_MUX_ROUND_CLOSEST nor
> CLK_SET_RATE_PARENT set.
> It even does harm on Meson8b SoCs where the input clock for the mux
> cannot b
On Sat, 2017-12-23 at 18:40 +0100, Jerome Brunet wrote:
> > Trying to set the rate of m250_div's parent clock makes no sense since
> > it's a mux which has neither CLK_MUX_ROUND_CLOSEST nor
> > CLK_SET_RATE_PARENT set.
> > It even does harm on Meson8b SoCs
On Sat, 2017-12-23 at 21:00 +0100, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Sat, Dec 23, 2017 at 6:40 PM, Jerome Brunet wrote:
> > On Sat, 2017-12-23 at 18:04 +0100, Martin Blumenstingl wrote:
> > > Trying to set the rate of m250_div's parent clock makes no
On Sat, 2017-12-23 at 22:49 +0100, Martin Blumenstingl wrote:
> while calculating this with a target frequency of 500MHz manually
> again I saw that there's a remainder of 10Mhz after the initial
> division.
> remainder * SDM_DEN = 16384000 - this value overflows 32-bit,
> things will go downhi
On Thu, 2017-12-28 at 23:21 +0100, Martin Blumenstingl wrote:
> While testing the dwmac-meson8b with an RGMII PHY on Meson8b we
> discovered that the m25_div is not actually a divider but rather a gate.
> This matches with the datasheet which describes bit 10 as "Generate
> 25MHz clock for PHY". Ba
On Fri, 2017-12-29 at 02:31 +0100, Emiliano Ingrassia wrote:
> Hi Martin, Hi Dave,
>
> On Thu, Dec 28, 2017 at 11:21:23PM +0100, Martin Blumenstingl wrote:
> > Hi Dave,
> >
> > please do not apply this series until it got a Tested-by from Emiliano.
> >
> >
> > Hi Emiliano,
> >
> > you reported
On Sat, 2017-12-30 at 00:40 +0100, Martin Blumenstingl wrote:
> > Maybe this bit 10 is indeed a 5/10 divider, as amlogic claims it is. Maybe,
> > as
> > Emiliano suggested, the output rate of div250 actually needs to be 250Mhz in
> > RGMII, before being divided by 10 to produce the 25MHz of div25
, MII, or RGMII interface."
Applying this restriction solves a stability issue observed on Amlogic
gxl platforms operating with RMII interface and the internal PHY.
Fixes: 83bf79b6bb64 ("stmmac: disable at run-time the EEE if not supported")
Signed-off-by: Jerome Brunet
Test
68 insertions(+), 56 deletions(-)
Ethernet works with this series applied (and tweaked DT patches from Emiliano)
Tested-by: Jerome Brunet
On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote:
>
[...]
> @@ -204,12 +200,24 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
> *dwmac)
>
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
> tx_dly_val << PR
On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote:
> Instead of using a custom buffer, snprintf() and devm_kstrdup() we can
> simplify this by using devm_kasprintf().
> No functional changes - this just makes the code shorter.
CCF copies the name from the init_data to its own structures
the 25MHz we set before, with that non-existing
> divide-by-5-or-10 divider).
>
> Special thanks go to Linus Lüssing for testing the various bits and
> checking the results with an oscilloscope on his Odroid-C1!
>
> Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the
e cannot be changed (which is fine
> since it's running at 1GHz, so it's already a multiple of 250MHz and
> 125MHz).
>
> Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson
> 8b / GXBB DWMAC")
> Suggested-by: Jerome Brunet
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
On Mon, 2018-01-15 at 13:08 +0100, Martin Blumenstingl wrote:
> can you share your thoughts how to do this?
> I can devm_kzalloc the memory for struct clk_mux, clk_divider and
> clk_fixed_factor in the function which registers these clocks. but I
> cannot declare them on the stack, because the clk-
On Mon, 2018-01-15 at 13:02 +0100, Martin Blumenstingl wrote:
> > Here you'd allocate memory for each string which will remain until the
> > driver
> > unload. It's not much, but still, it is wasted memory.
>
> good catch, thank you!
> maybe I should drop this patch for now and clean up the clock
On Tue, 2018-01-16 at 16:25 +0800, Yixun Lan wrote:
>
> On 01/16/18 01:10, Martin Blumenstingl wrote:
> > Hi Dave,
> >
> > this series is now successfully tested, thus we think it's ready to be
> > applied to your net-next tree.
> >
> > Emiliano reported [0] that he couldn't get dwmac-meson8b to
On Tue, 2018-01-16 at 12:17 +0100, Martin Blumenstingl wrote:
> > > Hi Martin
> > >
> > > I'm having problem with this series applied.
> > > I've tested on the A113D (AXG) platform, if this patch is applied, the
> > > driver will choose MPLL2 as clk source, and seems it doesn't work out
> > > wi
From: Neil Armstrong
Define registers and bits in meson-gxl PHY driver to make a bit
more human friendly. No functional change
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 111 +---
1 file changed, 93
, MII, or RGMII interface."
Applying this restriction solves a stability issue observed on Amlogic
gxl platforms operating with RMII interface and the internal PHY.
Fixes: 83bf79b6bb64 ("stmmac: disable at run-time the EEE if not supported")
Signed-off-by: Jerome Brunet
---
Hi P
On Sun, 2017-11-12 at 19:25 +0100, Andrew Lunn wrote:
> On Sun, Nov 12, 2017 at 04:16:04PM +0100, Heiner Kallweit wrote:
> > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
> > interrupt on some platforms" ethernet stopped working on my Odroid-C2
> > which has a RTL8211F phy.
>
On Sun, 2017-11-12 at 10:29 -0800, Florian Fainelli wrote:
> Hi Heiner,
>
> On 11/12/2017 07:16 AM, Heiner Kallweit wrote:
> > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
> > interrupt on some platforms" ethernet stopped working on my Odroid-C2
> > which has a RTL8211F phy.
On Sun, 2017-11-12 at 21:06 +0100, Andrew Lunn wrote:
> On Sun, Nov 12, 2017 at 07:36:48PM +0100, Jerome Brunet wrote:
> > On Sun, 2017-11-12 at 19:25 +0100, Andrew Lunn wrote:
> > > On Sun, Nov 12, 2017 at 04:16:04PM +0100, Heiner Kallweit wrote:
> > > > After co
e.
>
> With this patch the phy is working properly in interrupt mode.
>
> Signed-off-by: Heiner Kallweit
Tested-by: Jerome Brunet
On Sun, 2017-06-11 at 08:31 +0200, crow wrote:
> Hi Andrew,
>
> On Sat, Jun 10, 2017 at 5:27 PM, Andrew Lunn wrote:
> > > Also what Martin Blumenstingl wrote is following which is also crucial
> > > for fixing the issue:
> > > Amlogic has given their ethernet PHY driver some updates [2], it now
>
On Tue, 2017-07-25 at 18:56 +0200, crow wrote:
> Hi,
> Today I did test on ArchLinuxArm the Kernel v4.13-rc2. On downloading
> the linux git source the network will eventually get stalled. Here are
> the information
>
> Over SSH (network works).
>
> [root@alarm ~]# uname -a
> Linux alarm 4.13.0-r
-language.txt, section
"Menu structure", 2nd method.
This is fixed by placing the PHYLINK option just before PHYLIB.
Fixes: 9525ae83959b ("phylink: add phylink infrastructure")
Signed-off-by: Jerome Brunet
---
drivers/net/phy/Kconfig | 18 +-
1 file changed
On Tue, 2017-12-05 at 23:23 +0800, Yixun Lan wrote:
> > +static inline int meson_gxl_write_reg(struct phy_device *phydev,
> > + unsigned int bank, unsigned int reg,
> > + uint16_t value)
> > +{
> > + int ret;
> > +
> > + /*
On Tue, 2017-12-05 at 19:01 +0100, Andrew Lunn wrote:
> On Tue, Dec 05, 2017 at 10:33:34AM +0100, Jerome Brunet wrote:
> > From: Neil Armstrong
> >
> > Define registers and bits in meson-gxl PHY driver to make a bit
> > more human friendly. No functional c
Following previous changes, join the other authors of this driver and
take the blame with them
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 861b021b9758
Enable interrupt support in meson-gxl PHY driver
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 37 -
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 5325940fe899
default configuration so far and there is no
reason to change now. Remove CONFIG_A6 poke to make this clear.
Signed-off-by: Jerome Brunet
---
Out of curiosity, I tried to re-apply the ANALOG/DSP settings on speed
changes (patch available here [0] if someone wants to try) but I did
not notice any
river")
Signed-off-by: Jerome Brunet
---
I suppose this patch probably seems a bit hacky, especially the part
about the link partner acknowledge. I'm trying to figure out if the
value in MII_LPA makes sense but I don't have such a deep knowledge
of the ethernet spec.
To me, it does
Define registers and bits in meson-gxl PHY driver to make a bit
more human friendly. No functional change.
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 64 -
1 file changed, 51 insertions(+), 13
Use the generic init function to populate some of the phydev
structure fields
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 05054770aefb
Add read and write helpers to manipulate banked registers on this PHY
This helps clarify the settings applied to these registers in the init
function and upcoming changes.
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 103
1 file
Always check phy_write return values. Better to be safe than sorry
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 50 ++---
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson
patch
CONFIG_A6 settings is removed since this statement was without effect
Finally interrupt support is added, speeding things up a little
This series has been tested on the libretech-cc and khadas VIM
Jerome Brunet (8):
net: phy: meson-gxl: check phy_write return value
net: phy: meson-gxl
On Thu, 2017-12-07 at 16:34 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:12PM +0100, Jerome Brunet wrote:
> > The purpose of this change is to fix the incorrect detection of the link
> > partner (LP) advertised capabilities which sometimes happens with this PHY
> &g
On Thu, 2017-12-07 at 16:54 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:14PM +0100, Jerome Brunet wrote:
> > Enable interrupt support in meson-gxl PHY driver
>
> Hi Jerome
>
> Is it possible to implement did_interrupt()? That allows for shared
> interrup
On Thu, 2017-12-07 at 17:12 +0100, Andrew Lunn wrote:
> > Would it be Ok if send patches 1 to 5 to net ?
> > and 6 to 8 separately on net-next ?
>
> No. The rules for stable is that a patch must really fix something and
> be minimal.
>
> Documentation/process/stable-kernel-rules.rst
>
> What mi
On Thu, 2017-12-07 at 16:49 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:13PM +0100, Jerome Brunet wrote:
> > The PHY performs just as well when left in its default configuration and
> > it makes senses because this poke gets reset just after init.
>
> The o
On Thu, 2017-12-07 at 16:46 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote:
> > Add read and write helpers to manipulate banked registers on this PHY
> > This helps clarify the settings applied to these registers in the init
> >
river")
Signed-off-by: Jerome Brunet
---
I suppose this patch probably seems a bit hacky, especially the part
about the link partner acknowledge. I'm trying to figure out if the
value in MII_LPA makes sense but I don't have such a deep knowledge
of the ethernet spec.
To me, it does
was not declared. Should it be static?
>
> Signed-off-by: Colin Ian King
Indeed, silly mistake, thx for spotting it.
Reviewed-by: Jerome Brunet
s
> b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..138de3bc7cc8 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -20,3 +20,14 @@
> &uart_AO {
> status = "okay";
> };
> +
> +ðmac {
We try to keep nodes alphabetically ordered.
Please put ethmac before uart_A0
thx
>
>
With all the dependencies sorted out, it works
Tested-by: Jerome Brunet
On Thu, 2017-12-14 at 11:02 +0800, Yixun Lan wrote:
> ---
> Changes in v2 since [1]:
> - rebase to kevin's v4.16/dt64 branch
> - add Neil's Reviewed-by
> - move clock info to board.dts instead of in soc.dtsi
You got this comment regarding the pwm clock setup. the setup of the pwm clocks
depends
Use the generic init function to populate some of the phydev
structure fields
Reviewed-by: Andrew Lunn
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
Add read and write helpers to manipulate banked registers on this PHY
This helps clarify the settings applied to these registers and what the
driver actually does
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 130
Following previous changes, join the other authors of this driver and
take the blame with them
Reviewed-by: Andrew Lunn
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
Enable interrupt support in meson-gxl PHY driver
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 37 -
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index ddc92424e8de
Define registers and bits in meson-gxl PHY driver to make a bit
more human friendly. No functional change.
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 86 ++---
1 file changed, 66 insertions(+), 20
down and soft reset, so we will never see the value which
may have been set by the bootloader.
In the end, we have used the default configuration so far and there is no
reason to change now. Remove CONFIG_A6 poke to make this clear.
Reviewed-by: Andrew Lunn
Signed-off-by: Jerome Brunet
---
drivers
Always check phy_write return values. Better to be safe than sorry
Reviewed-by: Andrew Lunn
Signed-off-by: Jerome Brunet
---
drivers/net/phy/meson-gxl.c | 50 ++---
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/net/phy/meson
things up a little
This series has been tested on the libretech-cc and khadas VIM
Changes since v2 [0]:
Drop LPA corruption fix which has been merged through net. Apart from this,
series remains the same.
[0]: https://lkml.kernel.org/r/20171207142715.32578-1-jbru...@baylibre.com
Jerome Brunet (7
ntf() and devm_kstrdup() are not used anymore to generate
> the clock name (these are replaced by a variable on the stack) because
> the common clock framework already uses kstrdup() internally.
>
> No functional changes intended.
>
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
structs out of struct meson8b_dwmac,
> so only meson8b_init_rgmii_tx_clk() and the common clock framework know
> about these configurations.
>
> Suggested-by: Jerome Brunet
> Signed-off-by: Martin Blumenstingl
Acked-by: Jerome Brunet
> ---
> .../net/ethe
On Thu, 2017-01-05 at 23:25 +, Russell King - ARM Linux wrote:
> On Mon, Nov 28, 2016 at 09:54:28AM -0800, Florian Fainelli wrote:
> >
> > If we start supporting generic "enable", "disable" type of
> > properties
> > with values that map directly to register definitions of the HW, we
> > leave
On Fri, 2017-01-06 at 11:42 +, Russell King - ARM Linux wrote:
> On Fri, Jan 06, 2017 at 11:11:36AM +0100, Jerome Brunet wrote:
> >
> > The purpose of this patch is to provide a way to mark as broken a
> > particular eee mode. At first, it had nothing to do with &quo
of this, the concern is that it could be used to implement
configuration policies instead of describing a broken HW.
In the end, having a boolean property for each mode seems to be preferred
over one bit field value mapping the register (too) directly.
Cc: Florian Fainelli
Signed-off-by: Jerome
an option to disable EEE advertisement")
Reported-by: Julia Lawall
Signed-off-by: Jerome Brunet
---
drivers/net/phy/phy_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 9c06f8028f0c..ee5ebadb146
of this, the concern is that it could be used to implement
configuration policies instead of describing a broken HW.
In the end, having a boolean property for each mode seems to be preferred
over one bit field value mapping the register (too) directly.
Cc: Florian Fainelli
Signed-off-by: Jerome
r each EEE broken mode.
[0]:
http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbru...@baylibre.com
[1]:
http://lkml.kernel.org/r/1480348229-25672-1-git-send-email-jbru...@baylibre.com
[2]: http://lkml.kernel.org/r/e14a3b0c-dc34-be14-48b3-518a0ad0c...@gmail.com
Jerome Brunet (3):
net
, Rob Herring wrote:
> On Mon, Nov 28, 2016 at 04:50:26PM +0100, Jerome Brunet wrote:
> >
> > Signed-off-by: Jerome Brunet
> > Tested-by: Yegor Yefremov
> > Tested-by: Andreas Färber
> > Tested-by: Neil Armstrong
> > ---
> > include/dt-bindings/ne
provides a convenient way for these
platforms to disable EEE advertisement and work around the issue.
Signed-off-by: Jerome Brunet
---
drivers/net/phy/phy.c| 3 ++
drivers/net/phy/phy_device.c | 80 +++-
include/linux/phy.h | 3 ++
3 files
, I can rebase on
net-next instead.
Chnages since V1: [1]
- Disable the advertisement of EEE in the generic code instead of the
realtek driver.
[1] :
http://lkml.kernel.org/r/1479220154-25851-1-git-send-email-jbru...@baylibre.com
Jerome Brunet (3):
net: phy: add an option to disable EEE
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/net/phy.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/phy.txt
b/Documentation/devicetree/bindings/net/phy.txt
index bc1c3c8bf8fa..7f066b7c1e2c 100644
--- a/Documentation
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index e6e3491d48a5..b34da077b2f8
On Mon, 2016-11-21 at 17:01 +0100, Andrew Lunn wrote:
> On Mon, Nov 21, 2016 at 04:35:23PM +0100, Jerome Brunet wrote:
> >
> > Signed-off-by: Jerome Brunet
> > ---
> > Documentation/devicetree/bindings/net/phy.txt | 5 +
> > 1 file changed, 5 in
On Mon, 2016-11-21 at 21:35 -0800, Florian Fainelli wrote:
> Le 21/11/2016 à 08:47, Andrew Lunn a écrit :
> >
> > >
> > > What I did not realize when doing this patch for the realtek
> > > driver is
> > > that there is already 6 valid modes defined in the kernel
> > >
> > > #define MDIO_EEE_100T
On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote:
> Currently the dwmac-meson8b stmmac glue driver uses a hardcoded 1/4
> cycle TX clock delay. This seems to work fine for many boards (for
> example Odroid-C2 or Amlogic's reference boards) but there are some
> others where TX traffic is
On Thu, 2016-11-24 at 15:40 +0100, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Mon, Nov 21, 2016 at 4:35 PM, Jerome Brunet
> wrote:
> >
> > This patchset fixes an issue with the OdroidC2 board (DWMAC +
> > RTL8211F).
> > Initially reported as a low
On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote:
> Currently the dwmac-meson8b stmmac glue driver uses a hardcoded 1/4
> cycle TX clock delay. This seems to work fine for many boards (for
> example Odroid-C2 or Amlogic's reference boards) but there are some
> others where TX traffic is
On Thu, 2016-11-24 at 18:05 +0100, Martin Blumenstingl wrote:
> On Thu, Nov 24, 2016 at 4:56 PM, Jerome Brunet
> wrote:
> >
> > On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote:
> > >
> > > Currently the dwmac-meson8b stmmac glue driver uses
On Thu, 2016-11-24 at 18:10 +0100, Martin Blumenstingl wrote:
> On Thu, Nov 24, 2016 at 5:01 PM, Jerome Brunet
> wrote:
> >
> > On Thu, 2016-11-24 at 15:40 +0100, Martin Blumenstingl wrote:
> > >
> > > Hi Jerome,
> > >
> > > On Mon, Nov 21
lot Florian. This is really helping, especially the part about
RGMII delays.
Reviewed-by: Jerome Brunet
> Florian Fainelli (4):
> Documentation: net: phy: remove description of function pointers
> Documentation: net: phy: Add a paragraph about pause frames/flow
> control
>
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/net/phy.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/phy.txt
b/Documentation/devicetree/bindings/net/phy.txt
index 4627da3d52c4..54749b60a466 100644
--- a/Documentation
provides a convenient way for these
platforms to disable EEE advertisement and work around the issue.
Signed-off-by: Jerome Brunet
---
drivers/net/phy/phy.c| 3 ++
drivers/net/phy/phy_device.c | 80 +++-
include/linux/phy.h | 3 ++
3 files
Signed-off-by: Jerome Brunet
---
include/dt-bindings/net/mdio.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/net/mdio.h
diff --git a/include/dt-bindings/net/mdio.h b/include/dt-bindings/net/mdio.h
new file mode 100644
index
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index e6e3491d48a5..5624714d2b16
79220154-25851-1-git-send-email-jbru...@baylibre.com
[2] :
http://lkml.kernel.org/r/1479742524-30222-1-git-send-email-jbru...@baylibre.com
Jerome Brunet (4):
net: phy: add an option to disable EEE advertisement
dt-bindings: net: add EEE capability constants
dt: bindings: add ethernet phy eee
On Mon, 2016-11-28 at 13:31 +0100, Andreas Färber wrote:
> Am 28.11.2016 um 10:46 schrieb Jerome Brunet:
> >
> > Signed-off-by: Jerome Brunet
> > ---
> > arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 16
> >
> > 1 file changed,
l.org/r/1479742524-30222-1-git-send-email-jbru...@baylibre.com
[3] :
http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbru...@baylibre.com
Jerome Brunet (4):
net: phy: add an option to disable EEE advertisement
dt-bindings: net: add EEE capability constants
dt: bindings: add ethern
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