On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote:
> On Meson8b the only valid input clock is MPLL2. The bootloader
> configures that to run at 500002394Hz which cannot be divided evenly
> down to 125MHz using the m250_div clock. Currently the common clock
> framework chooses a m250_div of 2 - with the internal fixed
> "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz
> above the requested 125MHz).
>
> Letting the common clock framework propagate the rate changes up to the
> parent of m250_mux allows us to get the best possible clock rate. With
> this patch the common clock framework calculates a rate of
> very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock
> (which is the mux input). Dividing that by 2 (which is an internal,
> fixed divider for the RGMII TX clock) gives us an RGMII TX clock of
> 124999850Hz (which is only 150Hz off the requested 125MHz, compared to
> 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel
> sources).
>
> SoCs from the Meson GX series are not affected by this change because
> the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine
> since it's running at 1GHz, so it's already a multiple of 250MHz and
> 125MHz).
>
> Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson
> 8b / GXBB DWMAC")
> Suggested-by: Jerome Brunet <jbru...@baylibre.com>
> Signed-off-by: Martin Blumenstingl <martin.blumensti...@googlemail.com>
Reviewed-by: Jerome Brunet <jbru...@baylibre.com>
