> These are implementation specific. Don't forget you're on FPGA device, which
> allows for a lot of flexibility - memory region address and size shifts, 32 vs
> 16 bit wide memory, etc. You have to take into account both, TSE's manual as
> well as the actual implementation docs.
Are you buildin
On 20-10-01 01:59:25, Andrew Lunn wrote:
>
> The subject of this email thread is:
>
> Altera TSE driver not working in 100mbps mode
>
> Are you doing your testing at 1G or 100Mbps? I would suggest starting out at
> 1G if you can.
Well, this is the subject i used some tim
On 20-09-30 21:43:04, David Bilsby wrote:
>
> I've made some progress in integrating your TSE patches, in between doing my
> main work. I've managed to get the code into the later 5.4.44 kernel and
> compile without errors, however my initial attempts failed to configure the
> driver. In case it w
; side. That said none of the LED GPIOs I hooked up seemed to light so
> maybe there is something up there.
> Any hints would be most welcome.
What does ethtool -m show? With a copper module you might not get too
much useful information.
Also, what does ethtool on the link peer show? Has auto-neg worked?
What link modes are being advertised, etc?
The subject of this email thread is:
Altera TSE driver not working in 100mbps mode
Are you doing your testing at 1G or 100Mbps? I would suggest starting
out at 1G if you can.
Andrew
On 18/09/2020 18:14, Petko Manolov wrote:
On 20-09-17 21:29:41, David Bilsby wrote:
On 17/09/2020 07:42, Petko Manolov wrote:
On 20-09-16 22:32:03, David Bilsby wrote:
Hi
Would you consider making the PhyLink modifications to the Altera TSE
driver public as this would be very useful for a boa
On 20-09-17 21:29:41, David Bilsby wrote:
> On 17/09/2020 07:42, Petko Manolov wrote:
> > On 20-09-16 22:32:03, David Bilsby wrote:
> > > Hi
> > >
> > > Would you consider making the PhyLink modifications to the Altera TSE
> > > driver public as this would be very useful for a board we have which
On 20-09-16 22:32:03, David Bilsby wrote:
> Hi
>
> Would you consider making the PhyLink modifications to the Altera TSE driver
> public as this would be very useful for a board we have which uses an SFP PHY
> connected to the TSE core via I2C. Currently we are using a fibre SFP and
> fixing th
Hi
Would you consider making the PhyLink modifications to the Altera TSE
driver public as this would be very useful for a board we have which
uses an SFP PHY connected to the TSE core via I2C. Currently we are
using a fibre SFP and fixing the speed to 1G but would really like to be
able to us
