> These are implementation specific. Don't forget you're on FPGA device, which
> allows for a lot of flexibility - memory region address and size shifts, 32 vs
> 16 bit wide memory, etc. You have to take into account both, TSE's manual as
> well as the actual implementation docs.
Are you building your own fpga image?
If so I'd consider using signaltap to look 'inside' the TSE
logic to see if it actually trying to send anything at all.
David
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