Quoting DENG Qingfang :
On Mon, Apr 12, 2021 at 11:08:36PM +0800, DENG Qingfang wrote:
On Mon, Apr 12, 2021 at 07:04:49AM +, René van Dorst wrote:
> Hi Qingfang,
> > +static void mtk_phy_config_init(struct phy_device *phydev)
> > +{
> > + /* Disable EEE */
&g
Hi Qingfang,
Quoting DENG Qingfang :
Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
The initialization procedure is from the vendor driver, but due to lack
of documentation, the function of some register values remains unknown.
Signed-off-by: DENG Qingfang
---
RFC v3 -> RF
Quoting DENG Qingfang :
Hi Qingfang,
Thanks for the review.
Hi René,
On Sat, Apr 10, 2021 at 6:54 AM René van Dorst wrote:
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2568,6 +2568,11 @@ static void
mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port
This patch adds EEE support.
Signed-off-by: René van Dorst
---
v1 -> v2:
- Refactor the mt753x_{get,set}_mac_eee().
As DENQ Qingfang mentioned, most things are set else were.
These functions only set/report the LPI timeout value/LPI timeout enable bit.
- Removed the variable "eee
This patch adds EEE support.
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 50
drivers/net/dsa/mt7530.h | 16 -
2 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
Quoting Andrew Lunn :
On Thu, Apr 08, 2021 at 11:00:08PM +0800, DENG Qingfang wrote:
Hi René,
On Thu, Apr 8, 2021 at 10:02 PM René van Dorst
wrote:
>
> Tested on Ubiquiti ER-X-SFP (MT7621) with 1 external phy which
uses irq=POLL.
>
I wonder if the external PHY's IRQ can
mdio-bus:1f eth4 (uninitialized): PHY
[mt7530-0:04] driver [MediaTek MT7530 PHY] (irq=28)
[ 13.785656] mt7530 mdio-bus:1f eth5 (uninitialized): PHY
[mdio-bus:07] driver [Qualcomm Atheros AR8031/AR8033] (irq=POLL)
Tested-by: René van Dorst
Greats,
René
) with and without TRGMII mode enabled.
Tested-by: René van Dorst
Greats,
René
Quoting Landen Chao :
On Wed, 2020-08-19 at 00:09 +0800, Andrew Lunn wrote:
On Tue, Aug 18, 2020 at 03:14:10PM +0800, Landen Chao wrote:
> Add new support for MT7531:
>
> MT7531 is the next generation of MT7530. It is also a 7-ports switch with
> 5 giga embedded phys, 2 cpu ports, and the same
Hi Russel and Sean,
Quoting Russell King - ARM Linux admin :
On Tue, Jun 30, 2020 at 11:15:42AM +0100, Russell King wrote:
The SGMII PCS PHY needs to be updated with the link configuration in
the mac_link_up() call rather than in mac_config(). However,
mtk_sgmii_setup_mode_force() programs th
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
---
v2->v3:
* Remove 'status = "okay";' lines, suggested by Rob Herring
v1->v2:
* Adding extra note
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
Tested-by: Frank Wunderlich
Acked-by: Russell King
---
v2->v3:
* No change
* Add tags acked-by and tested-by
v1->v2:
* Refactor "unsupported" phy_interface part in
mt7530_phylink_mac_validate() suggested by Russell K
ay"' lines in patch #2
* Change a port 5 setup message in a debug message in patch #3
* Added ack-by and tested-by tags
v1->v2:
* Mostly phylink improvements after review.
rfc -> v1:
* Mostly phylink improvements after review.
* Drop phy isolation patches. Adds no value for no
with the 2nd GMAC of the SOC.
Signed-off-by: René van Dorst
Tested-by: Frank Wunderlich
Acked-by: Russell King
---
v2->v3:
* Change in mt7530_setup_port5() the port 5 setup message in to a debug
message. Suggested by David Miller
* Add tags acked-by and tested-by
v1->v2:
* Also report 10
Hi Rob,
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list
of additional
required, optional properties and how the integrated switch subnodes must
be specified.
@@ -94,3 +130,185 @@ Example:
};
};
};
+
+Example 2: MT7621: Port 4 i
Hi Rob,
Quoting Rob Herring :
On Wed, Aug 21, 2019 at 04:45:46PM +0200, René van Dorst wrote:
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
v1->v2:
* Adding extra n
ort 2.5Gbit in SGMII mode only in BASE-X mode.
Refactor the code.
René van Dorst (3):
net: ethernet: mediatek: Add basic PHYLINK support
net: ethernet: mediatek: Re-add support SGMII
dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the
new phylink API
.../arm/med
speed = <2500>; is now valid with PHYLINK
* Demagic SGMII register values
* Use phylink state to setup fixed-link mode
Signed-off-by: René van Dorst
--
v3->v4:
* Refactor validate() to incorporate the following items.
* Also report 1000baseX_Full for SGMII and GMII modes.
Suggested b
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst
--
v3->v4:
* In link_down() a ~ was missing before the (, RX and TX bits have to be
cleared. Spotted by Russell King
v2->v3:
* Make link_down() similar as link_up() suggested by R
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.
Signed-off-by: René van Dorst
--
v3->v4:
* no change
v2->v3:
* no change
v1->v2:
*
Hi Russell,
Quoting Russell King - ARM Linux admin :
On Wed, Aug 21, 2019 at 04:45:44PM +0200, René van Dorst wrote:
1. net: dsa: mt7530: Convert to PHYLINK API
This patch converts mt7530 to PHYLINK API.
2. dt-bindings: net: dsa: mt7530: Add support for port 5
3. net: dsa: mt7530: Add
Hi David,
Quoting David Miller :
From: René van Dorst
Date: Wed, 21 Aug 2019 16:45:47 +0200
+ dev_info(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
This is debugging,
Hi Russell,
Quoting Russell King - ARM Linux admin :
Hi René,
On Sat, Aug 24, 2019 at 01:11:17PM +, René van Dorst wrote:
Hi Russell,
Mediatek calls it Turbo RGMII. It is a overclock version of RGMII mode.
It is used between first GMAC and port 6 of the mt7530 switch. Can be used
with
Hi Russell,
Quoting Russell King - ARM Linux admin :
On Fri, Aug 23, 2019 at 03:45:15PM +0200, René van Dorst wrote:
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_F
Hi Russell,
Quoting Russell King - ARM Linux admin :
On Fri, Aug 23, 2019 at 03:45:14PM +0200, René van Dorst wrote:
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst
--
v2->v3:
* Make link_down() similar as link_up() suggested
the extra code in the rx path when mt76x8
was introduced.
Greats,
René
Tested-by: Frank Wunderlich
regards Frank
Gesendet: Freitag, 23. August 2019 um 15:45 Uhr
Von: "René van Dorst"
An: "John Crispin" , "Sean Wang"
, "Nelson Chang"
, "
speed = <2500>; is now valid with PHYLINK.
* Demagic SGMII register values
* Use phylink state to setup fixed-link mode
Signed-off-by: René van Dorst
--
v2->v3:
* Redo validate(), it was totally wrong. Noticed by Russell King.
v1->v2:
* SGMII port only support SGMII at 1Gbit, 10
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst
--
v2->v3:
* Make link_down() similar as link_up() suggested by Russell King
v1->v2:
* Also report 1000Base-X support suggested by Russell King
* Reverse christmas on many places sug
code.
René van Dorst (3):
net: ethernet: mediatek: Add basic PHYLINK support
net: ethernet: mediatek: Re-add support SGMII
dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the
new phylink API
.../arm/mediatek/mediatek,sgmiisys.txt| 2 -
.../dts/mediatek/mt76
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.
Signed-off-by: René van Dorst
--
v2->v3:
* no change
v1->v2:
* SGMII port only suppo
Hi Russell,
Quoting Russell King - ARM Linux admin :
On Wed, Aug 21, 2019 at 04:43:35PM +0200, René van Dorst wrote:
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
+ if (state->interface != PHY_INTERFACE_MODE_2500BASEX) {
phyl
Hi Russell,
Quoting Russell King - ARM Linux admin :
On Wed, Aug 21, 2019 at 04:43:34PM +0200, René van Dorst wrote:
+static void mtk_mac_link_down(struct phylink_config *config,
unsigned int mode,
+ phy_interface_t interface)
+{
+ struct mtk_mac *mac
Hi Pablo,
I have a building warning when compiling for a mips32r2 device.
Using latest net-next tree.
net/netfilter/nf_tables_offload.c: In function 'nft_flow_rule_create':
net/netfilter/nf_tables_offload.c:73:1: warning: the frame size of
1168 bytes is larger than 1024 bytes [-Wframe-larger-t
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
v1->v2:
* Refactor "unsupported" phy_interface part in
mt7530_phylink_mac_validate() suggested by Russell King
* Report and return when phylink tries to use autoneg_inband in
mt7530_phylink_mac_config() suggested by
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
v1->v2:
* Adding extra note about RGMII2 and gpio use.
rfc->v1:
* No change
---
.../devicetree/bindings/net/dsa/mt75
with the 2nd GMAC of the SOC.
Signed-off-by: René van Dorst
v1->v2:
* Also report 1000base-x support for port 5 suggested by Russell King
* Reorder variable declaraiant in reverse christmas tree suggested by
Daved Miller
* Refactor phy-handle lookup for 2nd GMAC.
* Use of_mdio_parse_a
ter review.
rfc -> v1:
* Mostly phylink improvements after review.
* Drop phy isolation patches. Adds no value for now.
René van Dorst (3):
net: dsa: mt7530: Convert to PHYLINK API
dt-bindings: net: dsa: mt7530: Add support for port 5
net: dsa: mt7530: Add support for port 5
.../devi
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst
--
v1->v2:
* Also report 1000Base-X support suggested by Russell King
* Reverse christmas on many places suggested by David Miller
* Rebase too pickup the mt76x8 changes.
---
drivers/
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.
Signed-off-by: René van Dorst
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
--
v1->v2:
* S
speed = <2500>; is now valid with PHYLINK.
* Demagic SGMII register values
* Use phylink state to setup fixed-link mode
Signed-off-by: René van Dorst
--
v1->v2:
* SGMII port only support SGMII at 1Gbit, 1000BASE-X and 2500BASE-X.
Also SGMII mode only does auto-negotiation.
* Change
These patches converts mediatek driver to PHYLINK API.
v1->v2:
* Rebase for mt76x8 changes
* Phylink improvements and clean-ups after review
* SGMII port doesn't support 2.5Gbit in SGMII mode only in BASE-X mode.
Refactor the code.
René van Dorst (3):
net: ethernet: mediatek: A
Hi Stefan,
Quoting Stefan Roese :
Hi Rene,
On 14.08.19 11:26, René van Dorst wrote:
Great, Thanks for addressing this issue.
I hope we can collaborate to also support mt76x8 in my PHYLINK
patches [0][1].
I am close to posting V2 of the patches but I am currently waiting on some
fiber
Hi Stefan,
Quoting Stefan Roese :
Hi Rene,
On 17.07.19 14:53, René van Dorst wrote:
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -39,7 +39,8 @@
NETIF_F_SG | NETIF_F_TSO | \
NETIF_F_TSO6
Quoting Russell King - ARM Linux admin :
Hi,
Just a couple of minor points.
On Wed, Jul 24, 2019 at 09:25:47PM +0200, René van Dorst wrote:
+
+static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
+ unsigned long *supported
Quoting Russell King - ARM Linux admin :
On Wed, Jul 24, 2019 at 09:25:49PM +0200, René van Dorst wrote:
Adding support for port 5.
Port 5 can muxed/interface to:
- internal 5th GMAC of the switch; can be used as 2nd CPU port or as
extra port with an external phy for a 6th ethernet port
Quoting David Miller :
From: René van Dorst
Date: Wed, 24 Jul 2019 21:25:49 +0200
@@ -1167,6 +1236,10 @@ mt7530_setup(struct dsa_switch *ds)
u32 id, val;
struct device_node *dn;
struct mt7530_dummy_poll p;
+ phy_interface_t interface;
+ struct device_node
Quoting Florian Fainelli :
On 7/24/2019 9:25 PM, René van Dorst wrote:
Adding support for port 5.
Port 5 can muxed/interface to:
- internal 5th GMAC of the switch; can be used as 2nd CPU port or as
extra port with an external phy for a 6th ethernet port.
- internal PHY of port 0 or 4; Used
9525ae83959b ("phylink: add phylink infrastructure")
Signed-off-by: René van Dorst
---
drivers/net/phy/phylink.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 5d0af041b8f9..a6aebaa14338 100644
--- a/drivers/net/phy/phylink.c
+++
Quoting Andrew Lunn :
On Fri, Jul 26, 2019 at 07:19:56AM +, René van Dorst wrote:
Quoting Andrew Lunn :
>>+ gmac0: mac@0 {
>>+ compatible = "mediatek,eth-mac";
>>+ reg = <0>;
>>+ phy-mode = &
Quoting Andrew Lunn :
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "sgmii";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst
Tested-by: Frank Wunderlich
---
drivers/net/ethernet/mediatek/Kconfig | 2 +-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 404 +++-
drivers/net/ethernet/mediatek
nts after review.
* Drop phy isolation patches. Adds no value for now.
René van Dorst (3):
net: dsa: mt7530: Convert to PHYLINK API
dt-bindings: net: dsa: mt7530: Add support for port 5
net: dsa: mt7530: Add support for port 5
.../devicetree/bindings/net/dsa/mt7530.txt|
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
rfc->v1:
* Renamed P5_MODE_* to P5_INTF_SEL_*. fits the function more
* Convert if-statement for speed bits to a switch suggested by
Daniel Santos
* Refactor flow_control pause bits and don't use state-
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst
rfc->v1:
* No change
---
.../devicetree/bindings/net/dsa/mt7530.txt| 215 ++
1 file changed, 215 insertions(+)
diff --git a/Documentation/devicet
with the 2nd GMAC of the SOC.
Signed-off-by: René van Dorst
rfc->v1:
* Removed unnecessary info print suggested by Andrew Lunn
* Added support for MII mode for port 5
---
drivers/net/dsa/mt7530.c | 145 ---
drivers/net/dsa/mt7530.h | 28
2 fi
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.
Signed-off-by: René van Dorst
Tested-by: Frank Wunderlich
---
.../arm/mediatek/me
speed = <2500>; is now valid with PHYLINK.
* Demagic SGMII register values
* Use phylink state to setup fixed-link mode
Signed-off-by: René van Dorst
Tested-by: Frank Wunderlich
---
drivers/net/ethernet/mediatek/mtk_eth_path.c | 72 +-
drivers/net/ethernet/mediatek/mtk_eth
These patches converts mediatek driver to phylink api.
SGMII support is only tested with fixed speed of 2.5Gbit on a Bananapi R64.
Frank tested these patches on this Bananapi R64 (mt7622) and
Bananapi R2 (mt7623).
Tested on hardware: mt7621, mt7622 and mt7623.
René van Dorst (3):
net: ethernet
Quoting Matthew Wilcox :
On Tue, Jul 23, 2019 at 08:58:44AM +, René van Dorst wrote:
Hi Matthew,
I see the same issue for the mediatek/mtk_eth_soc driver.
Thanks, Rene. The root problem for both of these drivers is that neither
are built on x86 with CONFIG_COMPILE_TEST. Is it possible
Quoting René van Dorst :
Quoting Russell King - ARM Linux admin :
On Wed, Jul 17, 2019 at 09:31:11PM +, René van Dorst wrote:
Hi,
I am trying to enable flow control/pause on PHYLINK and fixed-link.
My setup SOC mac (mt7621) <-> RGMII <-> SWITCH mac (mt7530).
It seems t
Quoting Russell King - ARM Linux admin :
On Wed, Jul 17, 2019 at 09:31:11PM +, René van Dorst wrote:
Hi,
I am trying to enable flow control/pause on PHYLINK and fixed-link.
My setup SOC mac (mt7621) <-> RGMII <-> SWITCH mac (mt7530).
It seems that in fixed-link mode all the
Hi,
I am trying to enable flow control/pause on PHYLINK and fixed-link.
My setup SOC mac (mt7621) <-> RGMII <-> SWITCH mac (mt7530).
It seems that in fixed-link mode all the flow control/pause bits are
cleared in
phylink_parse_fixedlink(). If I read phylink_parse_fixedlink() [0] correctly,
I
: René van Dorst
Cc: Sean Wang
Cc: Felix Fietkau
Cc: John Crispin
---
.../devicetree/bindings/net/mediatek-net.txt | 1 +
drivers/net/ethernet/mediatek/mtk_eth_path.c | 4 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 490 ++
drivers/net/ethernet/mediatek/mtk_eth_soc.h
can store the
name and capability bit of the mux. Convert the code so it can walk thru
the mtk_eth_muxc array.
Fixes: 8efaa653a8a5 ("net: ethernet: mediatek: Add MT7621 TRGMII mode
support")
Signed-off-by: René van Dorst
v1->v2:
- Move all capability bits in one enum, suggested
Quoting René van Dorst :
I see that I also forgot to tag this patch for net-next.
Greats,
René
No reason to error out on a MT7621 device with DDR2 memory when non
TRGMII mode is selected.
Only MT7621 DDR2 clock setup is not supported for TRGMII mode.
But non TRGMII mode doesn't nee
Quoting Willem de Bruijn :
On Sat, Jun 29, 2019 at 8:24 AM René van Dorst wrote:
Both MTK_TRGMII_MT7621_CLK and MTK_PATH_BIT are defined as bit 10.
This causes issues on non-MT7621 devices which has the
MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_RGMII) capability set.
The wrong TRGMII setup code is
No reason to error out on a MT7621 device with DDR2 memory when non
TRGMII mode is selected.
Only MT7621 DDR2 clock setup is not supported for TRGMII mode.
But non TRGMII mode doesn't need any special clock setup.
Signed-off-by: René van Dorst
---
drivers/net/ethernet/mediatek/mtk_eth_soc.
t;net: ethernet: mediatek: Add MT7621 TRGMII mode
support")
Signed-off-by: René van Dorst
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
b/drivers/net/ethernet/mediatek/mtk_eth_s
Quoting Andrew Lunn :
Hi Andrew,
On Tue, Jun 25, 2019 at 02:27:55PM -0500, Daniel Santos wrote:
On 6/25/19 2:02 PM, Andrew Lunn wrote:
>> But will there still be a mechanism to ignore link partner's advertising
>> and force these parameters?
> >From man 1 ethtool:
>
>-a --show-pause
>
Quoting Daniel Santos :
Hi Daniel,
On 6/24/19 9:52 AM, René van Dorst wrote:
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 237 +--
drivers/net/dsa/mt7530.h | 9 ++
2 files changed, 187 insertions(+), 59
Quoting Russell King - ARM Linux admin :
Hi Russel,
Thanks for your review, see also my comments and questions below.
Hi,
On Mon, Jun 24, 2019 at 04:52:47PM +0200, René van Dorst wrote:
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 237
Quoting Florian Fainelli :
Hi Florian
On 6/24/19 7:52 AM, René van Dorst wrote:
On some platforum the external phy can only interface to the port 5 of the
switch because the RGMII TX and RX lines are swapped. But it still can be
useful to use the internal phy of the switch to act as a WAN
Quoting Andrew Lunn :
Hi Andrew,
+static int mt7530_isolate_ephy(struct dsa_switch *ds,
+ struct device_node *ephy_node)
+{
+ struct phy_device *phydev = of_phy_find_device(ephy_node);
+ int ret;
+
+ if (!phydev)
+ return 0;
+
+
with the 2nd GMAC of the SOC.
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 135 +--
drivers/net/dsa/mt7530.h | 28
2 files changed, 159 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 237 +--
drivers/net/dsa/mt7530.h | 9 ++
2 files changed, 187 insertions(+), 59 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index
. This increases the LAN and WAN routing.
By adding the optional property mediatek,ephy-handle, the external phy
is put in isolation mode when internal phy is connected to 2nd GMAC via
phy-handle property.
Signed-off-by: René van Dorst
---
.../devicetree/bindings/net/dsa/mt7530.txt| 116
LAN and WAN. Because LAN and WAN don't share the same interface
anymore.
By adding an optional property mediatek,ephy-handle, the external phy
is put in isolation mode when internal phy is linked with 2nd GMAC via
phy-handle property.
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst
CC: devicet...@vger.kernel.org
---
.../devicetree/bindings/net/dsa/mt7530.txt| 215 ++
1 file changed, 215 insertions(+)
diff --git a/Documentation
ork duo to the SGMII work and support hardware which
I don't have.
https://github.com/vDorst/linux-1/commit/54004b807cba0dcec1653c1c290c2e5aae5127c2
René van Dorst (5):
net: dsa: mt7530: Convert to PHYLINK API
dt-bindings: net: dsa: mt7530: Add support for port 5
net: dsa: mt7530: Add sup
https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/master/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L769
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 46 +++-
drivers/net/dsa/mt7530.h | 4
2 files changed, 40 insertions(+), 10 dele
MT7621 SOC also supports TRGMII.
TRGMII speed is 1200MBit.
Signed-off-by: René van Dorst
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers
Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
switch both supports TRGMII mode. MT7621 TRGMII speed is fix 1200MBit.
v1->v2:
- Fix breakage on non MT7621 SOC
- Support 25MHz and 40MHz XTAL as MT7530 clocksource
René van Dorst (2):
net: ethernet: mediatek: Add MT7
Quoting Florian Fainelli :
Hi Andrew and Florian,
On 6/17/2019 6:53 PM, Andrew Lunn wrote:
By adding some extra speed states in the code it seems to work.
+ if (state->speed == 1200)
+ mcr |= PMCR_FORCE_SPEED_1000;
Hi René
Is TRGMII always 1.2G? Or can y
Quoting Andrew Lunn :
Hi Andrew,
On Mon, Jun 17, 2019 at 09:33:12PM +, René van Dorst wrote:
Quoting Andrew Lunn :
>On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
>>Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
>>switch both
>>
Quoting Andrew Lunn :
On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
Like many other mediatek SOCs, the MT7621 SOC and the internal
MT7530 switch both
supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
Hi René
Hi Andrew,
Is TRGMII used only between the SoC and the
MT7621 internal MT7530 switch also supports TRGMII mode.
TRGMII speed is 1200MBit.
Signed-off-by: René van Dorst
---
drivers/net/dsa/mt7530.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index
Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530 switch
both
supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
René van Dorst (2):
net: ethernet: mediatek: Add MT7621 TRGMII mode support
net: dsa: mt7530: Add MT7621 TRGMII mode support
drivers/net/dsa/mt7530.c
MT7621 SOC also supports TRGMII.
TRGMII speed is 1200MBit.
Signed-off-by: René van Dorst
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers
Quoting René van Dorst :
Quoting Florian Fainelli :
On 1/23/19 1:20 PM, René van Dorst wrote:
Without this patch sfp code retries to read the full struct sfp_eeprom_id
id out of the SFP eeprom. Sizeof(id) is 96 bytes.
My i2c hardware, Mediatek mt7621, has a rx buffer of 64 bytes.
So sfp_read
Quoting Andrew Lunn :
>>+ /* Many i2c hw have limited rx buffers, split-up request when needed.
*/
>>+ while ((q->max_read_len) && (len > q->max_read_len)) {
>>+ ret = sfp->read(sfp, a2, addr, buf, q->max_read_len);
>
>Hi René
>
>I think you want to pass MIN(len, q->ma
Quoting Andrew Lunn :
On Wed, Jan 23, 2019 at 10:20:46PM +0100, René van Dorst wrote:
Without this patch sfp code retries to read the full struct sfp_eeprom_id
id out of the SFP eeprom. Sizeof(id) is 96 bytes.
My i2c hardware, Mediatek mt7621, has a rx buffer of 64 bytes.
So sfp_read gets
Quoting Florian Fainelli :
On 1/23/19 1:20 PM, René van Dorst wrote:
Without this patch sfp code retries to read the full struct sfp_eeprom_id
id out of the SFP eeprom. Sizeof(id) is 96 bytes.
My i2c hardware, Mediatek mt7621, has a rx buffer of 64 bytes.
So sfp_read gets -NOSUPPORTED back on
is 92 bytes.
By split-up the request in multiple smaller requests with a max size of i2c
max_read_len, we can readout the SFP module successfully.
Tested with MT7621 and two Fiberstore modules SFP-GB-GE-T and SFP-GE-BX.
Signed-off-by: René van Dorst
---
drivers/net/phy/sfp.c | 23
Quoting Greg Ungerer :
/* Reset whole chip through gpio pin or memory-mapped
registers for @@ -1326,9 +1335,17 @@ static const struct
dsa_switch_ops mt7530_switch_ops = {
.port_vlan_del = mt7530_port_vlan_del,
};
+static const struct of_device_id mt7530_of_match[] =
Quoting g...@kernel.org:
From: Greg Ungerer
Do not attempt to force a port phy auto-ngeotiation during the driver
init phase. It is not necessary and results in a warning at system
boot up:
mtk_soc_eth 1e10.ethernet: generated random MAC address be:e7:d4:9d:7d:b0
mtk_soc_eth 1e10.ethe
Quoting Bjørn Mork :
Greg Ungerer writes:
The following change helped alot, but I still get some problems under
sustained load and some types of port setups. Still trying to figure
out what exactly is going on.
--- a/linux/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/linux/drivers/net/et
Quoting g...@kernel.org:
I have been working towards supporting the MT7530 switch as used in the
MediaTek MT7621 SoC. Unlike the MediaTek MT7623 the MT7621 is built around
a dual core MIPS CPU architecture. But underneath it is what appears to
be the same 7530 switch.
The following 3 patches ar
mits/mt7621-dsa-trgmii
[4]
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/mediatek/mtk_eth_soc.c?h=v4.14.84#n1946
--
Met vriendelijke groet,
René van Dorst
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