> From: Jakub Kicinski
> Sent: Wednesday, January 27, 2021 3:26 AM
> > PHY polling mode. Since as per IEEE802.11 the criteria for link
> validity
>
> I think you meant 802.3, fixed that up and applied, thanks!
>
You are right, I got confused.
Thank you for your patience, I am only beginning t
> drivers/net/ethernet/freescale/fec_main.c: In function ‘fec_restart’:
> drivers/net/ethernet/freescale/fec_main.c:958:46: warning: suggest
> parentheses around ‘&&’ within ‘||’ [-Wparentheses]
> 958 | (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
> |
> From: Heiner Kallweit
> Sent: Friday, January 22, 2021 4:20 PM
> The (optional) software reset is done via soft_reset callback.
> So if the PHY in question needs special treatment after a soft reset,
> why not add it to the soft_reset callback?
Thank you very much for the fast reply. This mak
it next time.
>
> On 21-01-18 16:57, Badel, Laurent wrote:
> > Description:
> > External PHY reset from the FEC driver was introduced in commit [1]
> to
> > mitigate an issue with iMX SoCs and LAN87xx PHYs. The issue occurs
> > because the FEC driver turns off the refe
er.kernel.org;
> devicet...@vger.kernel.org; ma...@denx.de
> Subject: [EXTERNAL] Re: [PATCH v4 net-next 1/5] net: phy: Add
> PHY_RST_AFTER_PROBE flag
>
>
>
> On 1/18/2021 8:58 AM, Badel, Laurent wrote:
> > Add new flag PHY_RST_AFTER_PROBE for LAN8710/20/40. This flag is
> >
Remove unused PHY_RST_AFTER_CLK_EN flag.
Signed-off-by: Laurent Badel
---
drivers/net/phy/smsc.c | 2 +-
include/linux/phy.h| 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 5ee45c48efbb..17a48f58e71c 100644
--- a/d
Extraneous PHY reset is not needed if the PHY is kept in reset when the
REF_CLK is turned off, so remove phy_reset_after_clk_enable() which is not
used anymore.
Signed-off-by: Laurent Badel
---
drivers/net/phy/phy_device.c | 24
include/linux/phy.h | 1 -
2 fi
PHY reset from the FEC driver is not needed if the PHY is kept in reset
after PHY driver probe, so remove phy_reset_after_clk_enable() and related
code from fec_main.c.
Signed-off-by: Laurent Badel
---
drivers/net/ethernet/freescale/fec_main.c | 40 ---
1 file changed, 40 de
Assert PHY reset at the end of phy_probe(), for PHYs bearing the
PHY_RST_AFTER_PROBE flag. For FEC-based devices this ensures that PHYs are
always in reset or power-down whenever the REF_CLK is turned off.
Signed-off-by: Laurent Badel
---
drivers/net/phy/phy_device.c | 2 +-
1 file changed, 1 i
Add new flag PHY_RST_AFTER_PROBE for LAN8710/20/40. This flag is intended
for phy_probe() to assert hardware reset after probing the PHY.
Signed-off-by: Laurent Badel
---
drivers/net/phy/smsc.c | 4 ++--
include/linux/phy.h| 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git
Description:
External PHY reset from the FEC driver was introduced in commit [1] to
mitigate an issue with iMX SoCs and LAN87xx PHYs. The issue occurs
because the FEC driver turns off the reference clock for power saving
reasons [2], which doesn't work out well with LAN87xx PHYs which require
> W/o knowing the exact issue in detail: For the sake of bisectability,
> shouldn't patches 4 and a modified patch 3 be first? After patches 1
> and 2 we may be in trouble, right?
Thank you very much for the quick reply. You are right, this would be a better
way to split the changes.
I will do
Assert PHY reset at the end of phy_probe(), for PHYs bearing the
PHY_RST_AFTER_PROBE flag. For FEC-based devices this ensures that PHYs are
always in reset or power-down whenever the REF_CLK is turned off.
Signed-off-by: Laurent Badel
---
drivers/net/phy/phy_device.c | 2 +-
1 file changed, 1 i
Extraneous PHY reset is not needed if the PHY is kept in reset when the
REF_CLK is turned off, so remove phy_reset_after_clk_enable() which is not
needed anymore.
Signed-off-by: Laurent Badel
---
drivers/net/phy/phy_device.c | 24
include/linux/phy.h | 1 -
2
Rename unused PHY_RST_AFTER_CLK_EN flag to PHY_RST_AFTER_PROBE for
LAN8710/LAN8720 and LAN8740. This flag can be used by phy_probe() to
assert PHY hardware reset after probing the driver.
Signed-off-by: Laurent Badel
---
drivers/net/phy/smsc.c | 4 ++--
include/linux/phy.h| 2 +-
2 files ch
PHY reset from the FEC driver is not needed if PHY chip is kept in reset
after PHY driver probe, so remove phy_reset_after_clk_enable() and related
code from fec_main.c.
Signed-off-by: Laurent Badel
---
drivers/net/ethernet/freescale/fec_main.c | 40 ---
1 file changed, 40
Description:
External PHY reset from the FEC driver was introduced in commit [1] to
mitigate an issue with iMX SoCs and LAN87xx PHYs. The issue occurs
because the FEC driver turns off the reference clock for power saving
reasons [2], which doesn't work out well with LAN87xx PHYs which require
2 PM
> To: Badel, Laurent ; Rob Herring
>
> Cc: da...@davemloft.net; fugang.d...@nxp.com; and...@lunn.ch;
> lgirdw...@gmail.com; m.fel...@pengutronix.de; robh...@kernel.org;
> k...@kernel.org; li...@armlinux.org.uk; richard.leit...@skidata.com;
> netdev@vger.kernel.org; Quette, Arnaud
>
-
Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la
Longeraie 7, 1110, Morges, Switzerland
-
-Original Message-
> From: Andrew Lunn
> Sent: Wednesday, November 04, 2020 2:11 PM
&g
>
-
Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la
Longeraie 7, 1110, Morges, Switzerland
-
-Original Message-
> From: Rob Herring
> Sent: Friday, October 30, 2020 8:19 PM
> To: Ba
, Switzerland
-
-Original Message-
> From: Marco Felsch
> Sent: Thursday, October 29, 2020 9:16 AM
> To: Badel, Laurent
> Cc: da...@davemloft.net; fugang.d...@nxp.com; k...@kernel.org;
> and...@lunn.ch; Heiner Kallweit ;
> li...@armlinux.org.uk; p.za...@pengutronix.
t; To: Badel, Laurent
> Subject: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC
> LAN8720
>
> On Tue, 27 Oct 2020 23:25:01 + Badel, Laurent wrote:
> > Subject: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720
> >
> > Description:
>
Subject: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720
Description:
A recent patchset [1] added support in the SMSC PHY driver for managing
the ref clock and therefore removed the PHY_RST_AFTER_CLK_EN flag for the
LAN8720 chip. The ref clock is passed to the SMSC driver through a new
Subject: [PATCH net 1/4] net:phy:smsc: enable PHY_RST_AFTER_CLK_EN if ref
clock is not set
Description: for compatibility, restore PHY_RST_AFTER_CLK_EN flag for
LAN8720, but clear it if the driver successfully retrieves a reference to
the ref clk. This ensures compatibility for systems that rel
Subject: [PATCH 4/4] net:phy: fix phy_reset_after_clk_enable()
Description: Resetting PHY chip during operation has the effect of
reverting all configuration registers to default. Therefore,
fully re-configure the PHY after a reset.
Also, avoid resetting the PHY if the reset is already asserted,
Subject: [PATCH net 3/4] net:phy: add phy_device_reset_status() support
Description: add support to query the status of the reset line of an MDIO
device.
Signed-off-by: Laurent Badel
---
drivers/net/phy/mdio_device.c | 18 ++
include/linux/mdio.h | 1 +
include/linu
Subject: [PATCH net 2/4] net:phy:smsc: expand documentation of clocks property
Description: The ref clock is managed differently when added to the DT
entry for SMSC PHY. Thus, specify this more clearly in the documentation.
Signed-off-by: Laurent Badel
---
Documentation/devicetree/bindings/net
gt; Subject: RE: [EXTERNAL] Re: [PATCH 2/2] Reset PHY in phy_init_hw() before
> interrupt configuration
>
>
>
> On Thu, 30 Apr 2020, Badel, Laurent wrote:
>
> > -Original Message-
> >> From: Heiner Kallweit
> >> Sent: Wednesday, April 29,
NAL] Re: [PATCH 2/2] Reset PHY in phy_init_hw() before
> interrupt configuration
>
> On 29.04.2020 11:03, Badel, Laurent wrote:
> > Description: this patch adds a reset of the PHY in phy_init_hw()
> > for PHY drivers bearing the PHY_RST_AFTER_CLK_EN flag.
> >
> >
age-
> From: Andrew Lunn
> Sent: Wednesday, April 29, 2020 6:35 PM
> To: Badel, Laurent
> Cc: gre...@linuxfoundation.org; fugang.d...@nxp.com;
> netdev@vger.kernel.org; f.faine...@gmail.com; hkallwe...@gmail.com;
> li...@armlinux.org.uk; richard.leit...@skidata.com;
> da...@dav
ent: Wednesday, April 29, 2020 5:25 PM
> To: Badel, Laurent
> Cc: gre...@linuxfoundation.org; fugang.d...@nxp.com;
> netdev@vger.kernel.org; f.faine...@gmail.com; hkallwe...@gmail.com;
> li...@armlinux.org.uk; richard.leit...@skidata.com;
> da...@davemloft.net; alexander.le...@mic
0;
--
2.17.1
>
-
Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la
Longeraie 7, 1110, Morges, Switzerland
-
-Original Message-----
> From: Badel, Laurent
> Sent: Wednesday, April 29, 2020 11:04 AM
>
Route de la
Longeraie 7, 1110, Morges, Switzerland
-
-Original Message-
> From: gre...@linuxfoundation.org
> Sent: Wednesday, April 29, 2020 1:55 PM
> To: Badel, Laurent
> Cc: fugang.d...@nxp.com; netdev@vger.kernel.org; and...@lunn.ch;
mbH ~ Registered place of business: Route de la
Longeraie 7, 1110, Morges, Switzerland
-
-Original Message-
> From: gre...@linuxfoundation.org
> Sent: Wednesday, April 29, 2020 11:40 AM
> To: Badel, Laurent
> Cc: fugang.d...@nxp.com; netdev@vger.
Description: this patch adds a reset of the PHY in phy_init_hw()
for PHY drivers bearing the PHY_RST_AFTER_CLK_EN flag.
Rationale: due to the PHY reset reverting the interrupt mask to default,
it is necessary to either perform the reset before PHY configuration,
or re-configure the PHY after r
Description: This patch reverts commit 1b0a83ac04e3
("net: fec: add phy_reset_after_clk_enable() support")
which produces undesirable behavior when PHY interrupts are enabled.
Rationale: the SMSC LAN8720 (and possibly other chips) is known
to require a reset after the external clock is enabled.
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