Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_device.c | 19 +++
src/intel/vulkan/anv_image.c | 11 ---
src/intel/vulkan/anv_private.h | 1 +
3 files changed
Hi Anuj,
On Mon, Oct 02, 2017 at 04:07:57PM -0700, Anuj Phogat wrote:
> WaFlushHangWhenNonPipelineStateAndMarkerStalled goes along
> with WaSampleOffsetIZ. Both recommends the same.
>
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_cont
On Mon, Oct 02, 2017 at 07:39:04PM -0700, Jason Ekstrand wrote:
> On Mon, Oct 2, 2017 at 4:07 PM, Anuj Phogat wrote:
>
> WaFlushHangWhenNonPipelineStateAndMarkerStalled goes along
> with WaSampleOffsetIZ. Both recommends the same.
>
> Cc: mesa-sta...@lists.freedesktop.org
> Signe
a...@lists.freedesktop.org
> Cc: Jason Ekstrand
> Cc: Rafael Antognolli
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_context.h| 2 +
> src/mesa/drivers/dri/i965/brw_defines.h| 1 +
> src/mesa/drivers/dri/i965/brw_pipe_control.c
On Wed, Oct 04, 2017 at 09:25:57AM -0700, Rafael Antognolli wrote:
> Hi Anuj,
>
> On Mon, Oct 02, 2017 at 04:07:57PM -0700, Anuj Phogat wrote:
> > WaFlushHangWhenNonPipelineStateAndMarkerStalled goes along
> > with WaSampleOffsetIZ. Both recommends the same.
On Thu, Jan 05, 2017 at 11:22:51AM -0800, Kenneth Graunke wrote:
> On Tuesday, December 13, 2016 2:50:58 PM PST Rafael Antognolli wrote:
> > Enable the use of a transform feedback overflow query with
> > glBeginConditionalRender. The render commands will only execute if the
> &g
Ugh, will update the patch with these changes.
Thanks!
Rafael
On Thu, Jan 05, 2017 at 11:17:51AM -0800, Kenneth Graunke wrote:
> On Tuesday, December 13, 2016 2:50:57 PM PST Rafael Antognolli wrote:
> > Enable getting the results of a transform feedback overflow query with a
> >
On Thu, Jan 05, 2017 at 11:29:39AM -0800, Kenneth Graunke wrote:
> Predication needs cmd parser only on gen7. For newer platforms, it
> should be available without it.
>
> Signed-off-by: Rafael Antognolli
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i9
MI_MATH is not available.
The series is available on github here:
https://github.com/rantogno/mesa/tree/review/overflow_query-v04
There are also piglit tests available for it here:
https://github.com/rantogno/piglit/tree/review/overflow_query-v05
Regards,
Rafael
Rafael Antognolli (6):
mesa: Add
-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 2 +
src/mesa/drivers/dri/i965/gen6_queryobj.c | 73 +++
2 files changed, 75 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index
)
- fallback to software conditional rendering when MI_MATH is not
available (Kenneth)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 73 --
1 file changed, 55 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri
Add some basic types and storage for the queries of this extension.
v2:
- update date of extension (Kenneth)
Signed-off-by: Rafael Antognolli
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 5 +
2 files changed, 6 insertions(+)
diff --git a/src/mesa/main
Also update checks on conditional rendering.
Signed-off-by: Rafael Antognolli
---
src/mesa/main/condrender.c | 4 +++-
src/mesa/main/queryobj.c| 21 +
src/mesa/state_tracker/st_cb_queryobj.c | 6 ++
3 files changed, 30 insertions(+), 1
This extension adds new query types which can be used to detect overflow
of transform feedback buffers. The new query types are also accepted by
conditional rendering commands.
v3:
- s/gen7+/gen6+/ in the relnotes (Jordan Justen)
Signed-off-by: Rafael Antognolli
---
docs/features.txt
On Fri, Jan 20, 2017 at 09:53:27AM -0800, Rafael Antognolli wrote:
> This extension adds new query types which can be used to detect overflow
> of transform feedback buffers. The new query types are also accepted by
> conditional rendering commands.
>
> v3:
> - s/gen7+/gen6
load_overflow_data_to_cs_gprs (Kenneth)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +
src/mesa/drivers/dri/i965/hsw_queryobj.c | 112 +++
2 files changed, 115 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src
I have tested this series with the branches that you mentioned, and with
piglit with the patches from my own branch:
https://github.com/rantogno/piglit/tree/review/fences-v02
Everything seems to work fine. You can add:
Tested-by: Rafael Antognolli
I also have gone through these patches
On Thu, Jan 26, 2017 at 07:18:24PM -0800, Ben Widawsky wrote:
> On 17-01-23 15:32:32, Chad Versace wrote:
> > On Fri 20 Jan 2017, Rafael Antognolli wrote:
> > > I have tested this series with the branches that you mentioned, and with
> > > piglit with the
6 and gen7 we set length to 0, since it only contains
BLEND_STATE_ENTRY's, and no other data.
With this change, we also change the code for blorp and anv to emit only
the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on
gen6-7 and 17 dwords on gen8+.
Signed-off-by: Ra
If the 'dwords' dict is empty, max(dwords.keys()) throws an exception.
This case could happen when we have an instruction that is only an array
of other structs, with variable length.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 2 +-
1 file changed, 1
gt; > >
> > > Reviewed-by: Lionel Landwerlin
> > >
> > > On 07/04/17 17:52, Rafael Antognolli wrote:
> > > > We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers
> > > > dwords (on gen8+), but the BLEND_STATE struct
On Wed, Apr 12, 2017 at 10:45:58AM -0700, Jason Ekstrand wrote:
> On Fri, Apr 7, 2017 at 9:52 AM, Rafael Antognolli
>
> wrote:
>
> We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers
> dwords (on gen8+), but the BLEND_STATE struct length is always 17. B
oup
(count="0") and store the offset of the last entry added to the struct
when reading the xml. When finally reading the aubdump file, we check
the size of the group and whether we have variable number of elements,
and in that case, reuse the last field to add the remaining elements
Use designated initializers on blorp and remove 0 from
initialization (Jason)
- Default entries to disabled on Vulkan (Jason)
- Rebase code.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 37 --
src/intel/genxml/gen6.xml | 4 +-
src/intel/
ength to 0 if dwords is empty, and do not declare dw
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b/src/intel/genxml/gen_pack_header.py
ind
'start' parameter from Group.emit_pack_function() is useless.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b/src/intel/genxml/gen_pack_header.py
ind
Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen7_te_state.c | 67 +
src/mesa/drivers/dri
The original brw_emit_vertices code is left intact for now, as it is
still used by gen4-5. We are bringing all the code to
genX_state_upload.c, and gen4-5 state emitting code is left on a
separate file.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1
The following states are ported on this patch:
- gen6_gs_push_constants
- gen6_vs_push_constants
- gen6_wm_push_constants
- gen7_tes_push_constants
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 4 +-
src/mesa/drivers/dri/i965/brw_state.h
- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
- "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
- "BackFace" -> "Backface"
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exe
Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen6_clip_state.c | 139 +--
src/mesa/drivers/dri/i965
Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 87
Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 3 +-
src/mesa/drivers/dri/i965/gen6_cc.c | 216
Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 3 +-
src/mesa/drivers/dri/i965/brw_util.h | 25 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 190
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen6_cc.c | 90 +
src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
4 files
- Normalize "Anti-Aliasing Enable"
- Add "Multisample Rasterization Mode" constants
- Rename "Use Point Width on Vertex" to "Vertex"
- Rename "Use Point Width from State" to "State"
Signed-off-by: Rafael Antognolli
---
src/intel/gen
From: Kenneth Graunke
Both GS and SOL have these fields. Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
Signed-off-by: Kenneth Graunke
---
src/intel/genxml/gen6.xml| 5 -
src/intel/genxml/gen7.xml| 5 -
src/intel/
oup
(count="0") and store the offset of the last entry added to the struct
when reading the xml. When finally reading the aubdump file, we check
the size of the group and whether we have variable number of elements,
and in that case, reuse the last field to add the remaining elements
From: Kenneth Graunke
Build libi965_gen[4,5].la too, since they contain the declaration for
gen[4,5]_init_atoms.
Remove gen4 and 5 init_atoms from genX_state_upload.
Signed-off-by: Kenneth Graunke
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.am | 8
Use designated initializers on blorp and remove 0 from
initialization (Jason)
- Default entries to disabled on Vulkan (Jason)
- Rebase code.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 37 --
src/intel/genxml/gen6.xml | 4 +-
src/intel/
Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 137 +---
src/mesa/drivers/dri/i965
There are two variants:
- Clip Enable
- CLIP Enable (on gen6)
Rename everything to Clip Enable.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index
From: Kenneth Graunke
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 15 ++-
src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
2 files changed, 119 insertions(+), 5 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/genX_state
Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 10 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c
'start' parameter from Group.emit_pack_function() is useless.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b/src/intel/genxml/gen_pack_header.py
ind
Ported in this patch:
- 3DSTATE_DS
- 3DSTATE_GS
- 3DSTATE_HS
- 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 6 +-
src/mesa/drivers/dri/i965/brw_state.h | 18 +-
src/mesa/drivers/dri/i965
From: Kenneth Graunke
This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.
Signed-off-by: Kenneth Graunke
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src
This function now lives inside genX_state_upload.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 8 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 265 +--
3 files changed, 274
Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src/mesa/drivers/dri/i965/brw_state.h | 3 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 113
Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 6 +-
src/mesa/drivers/dri/i965/gen7_sol_state.c| 307
ength to 0 if dwords is empty, and do not declare dw
Signed-off-by: Rafael Antognolli
Reviewed-by: Dylan Baker
---
src/intel/genxml/gen_pack_header.py | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b/src/in
Emit 3DSTATE_SBE on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen7_sf_state.c | 109
Use an alias, so we can set the same value as the #define's.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen8.xml | 1 +
src/intel/genxml/gen9.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 4985342..f4bde85 1
Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 14 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 219
Name the options to "Pixel Location":
- PIXLOC_CENTER -> CENTER
- PIXLOC_UL_CORNER -> UL_CORNER
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 4 +---
src/intel/genxml/gen6.xml | 4 ++--
src/intel/genxml/gen7.xml | 4 ++--
src/in
wip/brwxml
Feedback is welcome.
Kenneth Graunke (4):
i965: Add genxml related plumbing in a new genX_state_upload.c file.
i965: Get real per-gen atom lists.
i965: Port Gen6+ DEPTH_STENCIL state to genxml.
genxml: Make "Reorder Mode" fields consistent.
Rafael Antognolli (31):
intel/
This makes genxml create the right struct types, and generate the right
batch commands.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a12e22c
On this patch, we port:
- brw_polygon_stipple
- brw_polygon_stipple_offset
- brw_line_stipple
- brw_drawing_rect
The original code is still left behind because it is being used by
gen4-5.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 1
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml| 2 +-
src/intel/genxml/gen8.xml | 2 +-
src/intel/genxml/gen9.xml | 2 +-
src
Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
src/mesa/drivers/dri/i965/genX_state_upload.c
Rename that field name on genxml for:
- 3DSTATE_GS - gen6+
- 3DSTATE_DS - gen7+
- 3DSTATE_HS - gen7+
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml| 2 +-
src/intel/genxml/gen7.xml| 6 +++---
src/intel/genxml/gen75.xml | 6 +++---
src/intel/genxml
Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h| 9 +-
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen6_multisample_state.c | 6 +-
src/mesa/drivers/dri/i965
getopt_long flag parameter is an int pointer, so if we use bool to store
those values, when getopt_long writes to one of them, it might end up
overwriting the next one.
---
src/intel/tools/aubinator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/aubinator
On Tue, Jun 12, 2018 at 12:23:17PM -0700, Rafael Antognolli wrote:
> getopt_long flag parameter is an int pointer, so if we use bool to store
> those values, when getopt_long writes to one of them, it might end up
> overwriting the next one.
I forgot to mention in the commit message tha
component of the nir_intrinsic_load_ubo instruction (which apparently
supports multiple components). So yeah, this makes sense to me.
Take this review with a grain of salt (assuming what I wrote above is
correct), but this looks simple enough. So it is
Reviewed-by: Rafael Antognolli
>
On Tue, Jun 12, 2018 at 01:38:03PM -0700, Rafael Antognolli wrote:
> On Mon, Jun 11, 2018 at 02:01:49PM -0700, Kenneth Graunke wrote:
> > The UBO push analysis pass incorrectly assumed that all values would fit
> > within a 32B chunk, and only recorded a bit for the 32B chunk con
There's a lot of logic on the function that builds the push constants
packets. It reads both the push constants and the UBOs, and tries to
account for some hardware workarounds.
This patch splits the logic to gather the buffers into a function, and
the code to emit the packet to another one, where
Copying from the i965 change:
There's a lot of logic on the function that builds the push constants
packets. It reads both the push constants and the UBOs, and tries to
account for some hardware workarounds.
This patch splits the logic to gather the buffers into a function, and
the code to emit t
---
src/intel/genxml/gen10.xml | 4
src/intel/genxml/gen11.xml | 4
src/intel/genxml/gen6.xml | 5 +
src/intel/genxml/gen7.xml | 5 +
src/intel/genxml/gen75.xml | 5 +
src/intel/genxml/gen8.xml | 5 +
src/intel/genxml/gen9.xml | 4
7 files changed, 32 insertions(
If we are on gen8+ and have context isolation support, just make that
constant buffer address be absolute, so we can use it for push UBOs too.
---
src/intel/vulkan/anv_device.c | 5 -
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/genX_state.c | 27 +++
3 fi
---
src/intel/vulkan/anv_device.c | 3 +++
src/intel/vulkan/anv_private.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 63d5876edb1..d1637f097e8 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device
On Fri, Jun 15, 2018 at 01:21:17PM -0700, Jason Ekstrand wrote:
> On Fri, Jun 15, 2018 at 1:12 PM, Rafael Antognolli
> > wrote:
>
> If we are on gen8+ and have context isolation support, just make that
> constant buffer address be absolute, so we can use it
If we are on gen8+ and have context isolation support, just make that
constant buffer address be absolute, so we can use it for push UBOs too.
v2: Do not duplicate constant_buffer_0_is_relative flag (Jason)
---
src/intel/vulkan/anv_device.c | 3 ++-
src/intel/vulkan/genX_state.c | 27 +++
Hi Lionel,
I've been going through the patch and I think the content so far is
mostly fine. However, it has a lot of things going on for a single patch
IMHO. I see changes for the execution list submission port, ppgtt, using
the RB tree for ggtt too, etc...
It definitely make it more painful to r
Patches 4-7 are:
Reviewed-by: Rafael Antognolli
On Thu, Jun 14, 2018 at 06:11:43PM +0100, Lionel Landwerlin wrote:
> The Masking is only needed for entry matching.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aubinator.c | 4 ++--
> 1 file changed,
Reviewed-by: Rafael Antognolli
On Tue, Jun 19, 2018 at 02:45:16PM +0100, Lionel Landwerlin wrote:
> These memory offsets are stored in the gen_batch_decode_ctx.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aubinator.c | 5 -
> 1 file changed, 5 deletions(
On Tue, Jun 19, 2018 at 02:45:17PM +0100, Lionel Landwerlin wrote:
> Now that we rely on mmap of the data to parse, we can't process the
> standard input anymore.
Didn't we rely on mmap of the data since forever?
> This isn't much of a big deal because we have in-process batch decoder
> (run with
For some reason I always have trouble finding the docs about this.
Still, it looks correct according to the docs, and it also seems to be
matching what I see in aubdump since "tools/intel_aubdump: Simulate
"enhanced execlist" submission for gen11+".
Reviewed-by: Rafael Antogno
On Tue, Jun 19, 2018 at 11:40:30AM -0700, Rafael Antognolli wrote:
> On Tue, Jun 19, 2018 at 02:45:17PM +0100, Lionel Landwerlin wrote:
> > Now that we rely on mmap of the data to parse, we can't process the
> > standard input anymore.
>
> Didn't we rely on mmap of
Patch is
Reviewed-by: Rafael Antognolli
On Tue, Jun 19, 2018 at 02:45:19PM +0100, Lionel Landwerlin wrote:
> Now that we're softpinning the address of our BOs in anv & i965, the
> addresses selected start at the top of the addressing space. This is a
> problem for the current
On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips
>
> v2: by Lionel
> Fix memfd_create compilation issue
> Fix pml4 address stored on 32 instead of 64bits
> Return no buffer if first ppgtt page is not mapped
>
> Signed-off-by: Lionel Landwerl
On Tue, Jun 19, 2018 at 02:45:21PM +0100, Lionel Landwerlin wrote:
> We use memfd to store physical pages as they get read/written to and
> the GGTT entries translating virtual address to physical pages.
>
> Based on a commit by Scott Phillips.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/i
On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> On 20/06/18 01:00, Rafael Antognolli wrote:
> > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > > From: Scott D Phillips
> > >
> > > v2: by Lionel
> > >
On Wed, Jun 20, 2018 at 12:01:28PM -0700, Rafael Antognolli wrote:
> On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> > On 20/06/18 01:00, Rafael Antognolli wrote:
> > > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > &g
E_DWORD(2 << 16)
> +
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK0xf000
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO(0 << 28)
> +
> +/* DW3 */
> +
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK 0xf000
> +#define AUB_MEM_TRACE_M
diff -u --ignore-all-space shows that this and the original file are
roughly the same, except for some macros, some includes and how we check
for hardware gen.
Acked-by: Rafael Antognolli
On Tue, Jun 19, 2018 at 02:45:27PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwer
On Tue, Jun 19, 2018 at 02:45:28PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips
>
> For gen8+, write out PPGTT tables in aub files so that full 48-bit
> addresses can be serialized.
>
> v2: Fix handling of `end` index in map_ppgtt
>
> Signed-off-by: Scott D Phillips
> Signed-off-by
This patch is
Reviewed-by: Rafael Antognolli
On Thu, Jun 21, 2018 at 05:29:05PM +0100, Lionel Landwerlin wrote:
> We use memfd to store physical pages as they get read/written to and
> the GGTT entries translating virtual address to physical pages.
>
> Based on a commit by Sc
o we could add to help explain this patch. Assuming
those comments make sense and are correct, this patch is
Reviewed-by: Rafael Antognolli
>
> v2: Fix handling of `end` index in map_ppgtt
>
> v3: Correctly mark GGTT entry as present (Rafael)
>
> Signed-off-by: Scott D Phill
Patches 14-16 are
Reviewed-by: Rafael Antognolli
On Thu, Jun 21, 2018 at 05:29:13PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/dev/gen_device_info.c | 47 ++---
> src/intel/dev/gen_device_info.h | 5
>
Patches 1 and 2 are
Reviewed-by: Rafael Antognolli
On Wed, Apr 11, 2018 at 01:42:19PM -0700, Nanley Chery wrote:
> We're going to combine ::mcs_buf and ::hiz_buf in later commits. Once
> that happens, this function no longer make sense.
> ---
> src/mesa/drivers/dri/i965/in
struct intel_miptree_aux_buffer *aux_buf =
> intel_miptree_get_aux_buffer(mt);
> + if (aux_buf) {
> + intel_miptree_aux_buffer_free(aux_buf);
>mt->mcs_buf = NULL;
> -
> - /* Any pending MCS/CCS operations are no longer needed. Trying to
> - * execute any
hiz = false;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 8fe5c4add67..643de962d31 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -2
Looks like this is the last patch in the series that is only cleaning up
the mess I left behind by adding the clear color bo. Thanks for that.
Reviewed-by: Rafael Antognolli
On Wed, Apr 11, 2018 at 01:42:22PM -0700, Nanley Chery wrote:
> We want to add and use a getter that turns off
On Wed, Apr 11, 2018 at 01:42:24PM -0700, Nanley Chery wrote:
> This getter allows CNL to sample from fast-cleared sRGB textures correctly.
I think it might be worth mentioning in the commit message that the
helper both returns the clear color for inline use, and updates the
pointer to the indirec
t_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> +}
Just trying to bring attention to this piece of code. Jason suggested
that these PIPE_CONTROL's might not be sufficient, and that we need
tests that clear and texture from the surface repeatedly (I didn't look
at
On Fri, Apr 20, 2018 at 03:01:44PM -0700, Nanley Chery wrote:
> On Fri, Apr 20, 2018 at 01:35:39PM -0700, Rafael Antognolli wrote:
> > On Wed, Apr 11, 2018 at 01:42:24PM -0700, Nanley Chery wrote:
> > > This getter allows CNL to sample from fast-cleared sRGB textures
> >
On Fri, Apr 20, 2018 at 02:38:37PM -0700, Nanley Chery wrote:
> On Fri, Apr 20, 2018 at 09:58:38AM -0700, Rafael Antognolli wrote:
> > Nice, I was planning to do something like this later but didn't want to
> > include many more changes on my ongoing series. This looks grea
On Thu, Apr 19, 2018 at 05:44:06PM +0300, Topi Pohjolainen wrote:
> This didn't actually help the failing tests I'm looking at
> but hopefully has teeth elsewhere.
>
> CC: Jason Ekstrand
> CC: Jordan Justen
> CC: Anuj Phogat
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/
On Mon, Apr 23, 2018 at 03:05:27PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> Signed-off-by: Matt Atwood
> ---
> include/pci_ids/i965_pci_ids.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
> index
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