/gen8: Use intel_miptree_aux_buffer for auxiliary buffer - which didn't
need
to be separate in my opinion.
v3: rebase on master (Lionel)
Signed-off-by: Jordan Justen (v1)
Reviewed-by: Topi Pohjolainen (v1)
Signed-off-by: Ben Widawsky a (v2)
Signed-off-by: Lionel Landwerlin (v3)
---
ionel)
Signed-off-by: Ben Widawsky (v1)
Signed-off-by: Lionel Landwerlin (v2)
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
s most of the actual
programming (Lionel)
Signed-off-by: Ben Widawsky (v1)
Signed-off-by: Lionel Landwerlin (v2)
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface
From: Jordan Justen
Currently it indicates that this is never supported, but soon it will
be supported for gen8+^w gen9+
v2 by Ben:
- Explicitly disable aux_hiz for gen < 9 (with comment)
- squashed in next patch to avoid unused and useless functions
i965: Support sampling with hiz during re
num_samples <= 1. (Lionel)
Allow sampling from HiZ only if all LOD are available from the HiZ
buffer. (Lionel)
Signed-off-by: Jordan Justen (v1)
Signed-off-by: Ben Widawsky (v2)
Signed-off-by: Lionel Landwerlin (v3)
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 ++
On 07/11/16 10:07, Pohjolainen, Topi wrote:
On Thu, Nov 03, 2016 at 10:39:39AM +, Lionel Landwerlin wrote:
From: Ben Widawsky
libdrm may round up the allocation requested by mesa. As a result, accesses
through the gtt may end up accessing memory which does not belong to mesa. The
problem
On 07/11/16 10:18, Pohjolainen, Topi wrote:
On Thu, Nov 03, 2016 at 10:39:40AM +, Lionel Landwerlin wrote:
From: Ben Widawsky
This seems counter to the goal of consolidating hiz, mcs, and later ccs buffers.
Unfortunately, hiz on gen6 is a thing the code supports, and this wart will be
If the mcs buffer allocation fails we might get a NULL pointer. This
was reported by Coverity and should only happen if we run out of
memory.
CID: 1394290
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
If the mcs buffer allocation fails we might get a NULL pointer. This
was reported by Coverity and should only happen if we run out of
memory.
v2: return failure at the point of allocation (Chris)
CID: 1394290
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98480
---
src/compiler/glsl/glsl_parser.yy | 5 +--
src/compiler/glsl/glsl_parser_extras.cpp | 58
src/compiler/glsl/glsl_parser_extras.h | 4 +++
src/mesa/main
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98480
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index
piglit test is available here :
https://patchwork.freedesktop.org/series/15173/
Cheers,
Lionel Landwerlin (2):
mesa: add NV_image_formats extension support
i965: enable NV_image_formats support
src/compiler/glsl/glsl_parser.yy | 5 ++-
src/compiler/glsl/glsl_parser_extras.cpp
On 11/11/16 18:39, Ilia Mirkin wrote:
On Fri, Nov 11, 2016 at 10:40 AM, Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98480
---
src/compiler/glsl/glsl_parser.yy | 5 +--
src/compiler/glsl/glsl_parser_extras.cpp
Thanks for Spotting this.
Reviewed-by: Lionel Landwerlin
On 14/11/16 13:23, Iago Toral Quiroga wrote:
According to the spec for vkGetPhysicalDeviceImageFormatProperties:
"If format is not a supported image format, or if the combination of format,
type, tiling, usage, and flags i
Sounds good too.
Reviewed-by: Lionel Landwerlin
On 14/11/16 13:23, Iago Toral Quiroga wrote:
Fixes dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
---
src/intel/vulkan/anv_formats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan
A commit from the CTS suite on the 1.0-dev branch started using
VK_REMAINING_MIP_LEVELS, we're not dealing with it properly for clears.
Fixes:
dEQP-VK.api.image_clearing.clear_color_image.*
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_blorp.c | 4 ++--
1 file chang
v2: Replace helper function by qualifier struct field (Ilia)
Enable NV_image_formats using ARB_shader_image_load_store (Ilia)
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98480
Cc: Ilia Mirkin
---
src/compiler/glsl/glsl_parser.yy | 86
Reviewed-by: Lionel Landwerlin
On 16/11/16 01:35, Ben Widawsky wrote:
From: Ben Widawsky
When 1 BO is used for aux data, it needs to point to the correct offset,
which will not be the BOs offset but instead an offset from the BOs
offset. Since today there are always multiple BOs for aux
On 16/11/16 01:35, Jordan Justen wrote:
On 2016-11-15 16:21:27, Matt Turner wrote:
Jordan,
In
commit 0041169cacb300a882b4dc38cd341f98bf2a7c38
Author: Jordan Justen
Date: Fri Oct 21 12:56:49 2016 +0100
This date is not correct. In my branch it was:
Date: Mon Jun 30 00:50:56 2014 +
Y
Thanks!
Reviewed-by: Lionel Landwerlin
On 20/11/16 07:07, Mun Gwan-gyeong wrote:
This fixes resource leak in gen_spec_load_from_path XML_ParserCreate
failure path
CID 1373564
Signed-off-by: Mun Gwan-gyeong
---
src/intel/tools/decoder.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
This additional buffer will store workaround border colors for integer
formats on Gen7.5.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_descriptor_set.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan
about the
texture format last bound to a sampler into a UBO. When a shader tries to
access a sampler with integer format, do some bounds checking and load the
border color from the UBO if needed.
Thanks,
Lionel Landwerlin (7):
anv: Fix border colors with normalized formats on gen7/gen75
anv
This additional buffer will store workaround border colors for integer
formats on Gen7.5.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_descriptor_set.c | 42 +++
src/intel/vulkan/anv_private.h| 9
2 files changed, 51 insertions
*
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/Makefile.sources | 1 +
src/intel/vulkan/anv_nir.h | 3 +
src/intel/vulkan/anv_nir_gen7_border_color_wa.c | 208
src/intel/vulkan/anv_pipeline.c | 3 +
4 files
.*.format.*_unorm.address_modes.all_mode_clamp_to_border_*
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_cmd_buffer.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index fff0ba0..69c1ce9 100644
--- a/src
This additional buffer stores workaround border colors & mask based of the
format's number of channels for integer formats on Gen7.5.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_descriptor_set.c | 16
src/intel/vulkan/anv_private.h| 13 +++
---
src/intel/vulkan/anv_private.h | 4 +++-
src/intel/vulkan/genX_state.c | 21 +
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 7d7380a..8231f6b 100644
--- a/src/intel/vulkan/anv_private.h
When writing texture or sampler information into descriptor sets, also store
the related information for border color workaround on Gen7.5.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_descriptor_set.c | 60 ++-
1 file changed, 59 insertions(+), 1
On 22/11/16 02:58, Jason Ekstrand wrote:
---
src/intel/tools/decoder.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/decoder.c b/src/intel/tools/decoder.c
index 6bd02bf..55488eb 100644
--- a/src/intel/tools/decoder.c
+++ b/src/intel/tools/decoder.c
@@
ve the same assert(result ==
VK_ERROR_OUT_OF_DEVICE_MEMORY); here?
Anyhow,
Reviewed-by: Lionel Landwerlin
+ result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
+ assert(result == VK_SUCCESS);
+
+ /* Re-emit state base addresses so we get the new surface state base
+ *
Reviewed-by: Lionel Landwerlin
On 22/11/16 04:26, Jason Ekstrand wrote:
This can happen even if the binding table isn't changed. For instance, you
could have dynamic offsets with your descriptor set. This fixes the new
stress.lots-of-surface-state.cs.dynamic cricible test.
Cc: "
Reviewed-by: Lionel Landwerlin
On 22/11/16 04:26, Jason Ekstrand wrote:
Cc: "13.0"
Cc: Jordan Justen
---
src/intel/vulkan/genX_cmd_buffer.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/in
Sounds good to me, thanks!
Reviewed-by: Lionel Landwerlin
On 17/11/16 08:36, Iago Toral Quiroga wrote:
Besides the logical operation involved, these also require that we test if the
operands are ordered / unordered.
For ordered operations, both operands must be ordered (and they must pass
This series is :
Reviewed-by: Lionel Landwerlin
On 24/11/16 04:27, Jason Ekstrand wrote:
We were reading from the "comment size" dword and incrementing by that
amount. This never caused a problem because that field was always zero.
However, experimenting with actual aub fil
Hi Iago,
Looking at the history, before ed4fe3e9ba9018e68afe6fdd4f267218a537fdaa
we seem to set min/mag filter to MAPFILTER_ANISOTROPIC if maxAnisotropy
> 1. It seems your patch makes sense in using MAPFILTER_ANISOTROPIC in
the NEAREST case, but I wonder whether we should also check for
maxAn
Reviewed-by: Lionel Landwerlin
On 24/11/16 12:36, Juan A. Suarez Romero wrote:
Fixes warning.
---
src/intel/vulkan/genX_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index cb164ad..ada7985
Reviewed-by: Lionel Landwerlin
On 24/11/16 12:36, Juan A. Suarez Romero wrote:
Fixes defined but not used warning.
---
src/intel/vulkan/genX_pipeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index ada7985
Thanks for the explanation, feel free to wait for Jason's rb otherwise
:
Reviewed-by: Lionel Landwerlin
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Reviewed-by: Lionel Landwerlin
On 27/11/16 22:45, Ilia Mirkin wrote:
Remove duplicate .alphaToOne, add missing .shaderResourceMinLod, and
reorder a few entries to match their vulkan.h order. All the sparse
features are still left out entirely.
Signed-off-by: Ilia Mirkin
---
Wasn't 100%
Reviewed-by: Lionel Landwerlin
On 27/11/16 19:41, Ilia Mirkin wrote:
This appears to be fully supported already.
Signed-off-by: Ilia Mirkin
---
On a SKL:
./deqp-vk --deqp-visibility=hidden --deqp-case='*cube_array*'
Test run totals:
Passed:3255/4196 (77.6%)
Failed
On 22/11/16 21:53, Plamena Manolova wrote:
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.
Signed-off-by: Plamena Manolova
---
src/compiler/glsl/ast.h | 5 ++
Also forgot that (like Ilia suggested for NV_image_formats) you can
update docs/relnotes/ to list the new feature.
Cheers,
-
Lionel
On 30/11/16 13:33, Ilia Mirkin wrote:
On Nov 30, 2016 7:17 AM, "Lionel Landwerlin"
mailto:lionel.g.landwer...@intel.com>>
wrote:
>
On 01/12/16 04:02, Chris Forbes wrote:
A couple of notes on existing weirdness here:
- Naming of GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT is bizarre (not
your fault)
- Is BRW_PSICMS_INNER really the right thing for the normal mode? Why
not BRW_PSICMS_NORMAL? Perhaps whoever added this stuff c
Signed-off-by: Lionel Landwerlin
---
src/compiler/glsl/ast.h | 5
src/compiler/glsl/ast_to_hir.cpp | 5
src/compiler/glsl/ast_type.cpp | 16 +++-
src/compiler/glsl/glsl_parser.yy | 34 ++
src/compiler/glsl
Hi,
Here are a couple of patches to add support for the
INTEL_conservative_rasterization extension.
This is available on Gen9+ platforms.
You can find associated piglit tests here :
https://patchwork.freedesktop.org/series/16230/
Cheers,
Lionel Landwerlin (2):
mesa: add support for
Signed-off-by: Lionel Landwerlin
---
docs/relnotes/13.1.0.html| 1 +
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/gen8_ps_state.c
Forgot to mentioned that this is based on top of Plamena's work (in case
you want to test) :
https://patchwork.freedesktop.org/series/15512/
On 01/12/16 15:56, Lionel Landwerlin wrote:
Hi,
Here are a couple of patches to add support for the
INTEL_conservative_rasterization extension.
This is the size selected by the i965 driver.
Signed-off-by: Lionel Landwerlin
Cc: Kenneth Graunke
---
src/intel/vulkan/anv_private.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 1f03b68..ce4eb4d
.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_image.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index e60373a..9ef0760 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
pitch
> makes so sense for us. On sky lake and above it should be exactly
> the same as array pitch. One thing we should do is not report array
> pitch for 3D and maybe report a depth pitch of zero on broadwell and
> earlier.
>
> On Dec 3, 2016 7:51 AM, "Lionel Landwerlin&q
On 3 Dec 2016 4:40 pm, "Jason Ekstrand" wrote:
On Dec 3, 2016 8:27 AM, "Lionel Landwerlin" wrote:
That's on Haswell.
I'm not sure whether a 3d image with multiple layers makes sense, but
if it does, it should probably return different depth/layer pitch
values?
Seeing gtk+ application lockup when they query the buffer age of a surface.
Since we update the buffer age field only when creating buffers & swaping
them on the client side, there shouldn't be any need for requesting a new
back buffer if there is already one available.
Signed-off-b
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.isl.am | 10 +-
src/intel/isl/isl.c| 25 +++
src/intel/isl/isl.h| 8 +
src/intel/isl/tests/.gitignore | 1 +
.../tests
the newly introduce isl function to query the depth.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_image.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index e60373a151..af5e3c4974
On 06/12/16 11:36, Eric Engestrom wrote:
On Saturday, 2016-12-03 22:47:17 +, Lionel Landwerlin wrote:
Seeing gtk+ application lockup when they query the buffer age of a surface.
Since we update the buffer age field only when creating buffers & swaping
them on the client side, t
On 07/12/16 10:55, Eric Engestrom wrote:
On Tuesday, 2016-12-06 12:13:32 +, Lionel Landwerlin wrote:
On 06/12/16 11:36, Eric Engestrom wrote:
On Saturday, 2016-12-03 22:47:17 +, Lionel Landwerlin wrote:
Seeing gtk+ application lockup when they query the buffer age of a surface.
Since
We usually set that value up when creating the buffer (NULL to non-NULL
transition). It doesn't hurt to set that value to 0 up front when we destroy
the buffer (non-NULL to NULL transition).
Signed-off-by: Lionel Landwerlin
---
src/egl/drivers/dri2/platform_wayland.c | 2 ++
1 file chang
ends on a previous commit settings the age value of buffers
to 0 on buffer destruction, so we're sure to always have an up to date
value.
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84016
---
src/egl/drivers/dri2/platform_wayland.c | 2 +-
1 f
On 07/12/16 14:55, Ilia Mirkin wrote:
On Thu, Dec 1, 2016 at 10:56 AM, Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
---
src/compiler/glsl/ast.h | 5
src/compiler/glsl/ast_to_hir.cpp | 5
src/compiler/glsl/ast_type.cpp | 16
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mesa/main/enable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index 8440c62..2267e31 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -440,7
/16230/
Cheers,
Lionel Landwerlin (3):
mesa: main: use _NEW_MULTISAMPLE for conservative rasterization state
mesa: main: don't error when enabling conservative rasterization on
gles
main: extensions: update INTEL_conservative_rasterization dependencies
src/mesa/drivers/dri/i965
Suggested by Ilia.
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mesa/drivers/dri/i965/gen8_ps_state.c | 5 ++---
src/mesa/drivers/dri/i965/gen8_sf_state.c | 2 +-
src/mesa/main/enable.c| 2 +-
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src
Suggested by Ilia.
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mesa/main/extensions_table.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 9c3b776..2de3c59 100644
--- a/src/mesa/main
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mesa/main/get_hash_params.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index bc80d94..e79037e 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mapi/glapi/gen/INTEL_conservative_rasterization.xml | 10 ++
src/mapi/glapi/gen/gl_API.xml | 1 +
2 files changed, 11 insertions(+)
create mode 100644 src/mapi/glapi/gen
Signed-off-by: Lionel Landwerlin
---
docs/relnotes/13.1.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html
index 5b8b016..4dce843 100644
--- a/docs/relnotes/13.1.0.html
+++ b/docs/relnotes/13.1.0.html
@@ -45,6 +45,7 @@ Note: some of
the newly introduce isl function to query the depth.
v2: pass mipLevel
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_image.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index
v2: add lod level argument (Jason)
return 0 for any lod level > 0 (Jason)
return 0 for any surface not 3D (Jason)
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.isl.am | 10 +-
src/intel/isl/isl.c| 28 +++
src/intel/
Also, for such
smaller exts, we tend to just stick them into gl_API.xml directly.
Lastly if you do want to keep it in a separate file, make sure to add
it to the list in Makefile.am.
Oops...
On Thu, Dec 8, 2016 at 7:11 AM, Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
Cc: Ilia M
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
Rather than emit the instructions directions, make use of the helpers
brw_store_register_mem32() and brw_load_register_mem()
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/hsw_sol.c | 27
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
My ulterior motive is to kill intel_batchbuffer.[ch] and moving
discrete pieces of functionality into their own files is a small step
towards that goal.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
Rename brw_load_register_reg to include the width (32bits) similar to
all the other register routines.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 2 +-
src/mesa/drivers/dri/i965
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
There are a few open coded setting of single registers using
MI_LOAD_REGISTER_IMM, replace those with a call to
brw_load_register_imm32().
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c | 6
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
Reorder the parameters to brw_store_register_mem32 and
brw_store_register_mem64 so that the offset into the buffer and its
identifier are paired. This brings the interface into line wth
brw_load_register_mem.
Signed-off-by
Some I915_GEM_DOMAIN_VERTEX are changed to I915_GEM_DOMAIN_INSTRUCTION,
which are treated the same way in the kernel. So I guess it doesn't matter.
Reviewed-by: Lionel Landwerlin
On 09/12/16 10:54, Chris Wilson wrote:
The domains used are immaterial, and we should never be marking the
On 08/12/16 19:19, Jason Ekstrand wrote:
On Dec 8, 2016 8:48 AM, "Lionel Landwerlin" <mailto:llandwer...@gmail.com>> wrote:
v2: add lod level argument (Jason)
return 0 for any lod level > 0 (Jason)
return 0 for any surface not 3D (Jason)
I'd r
v2: put enum directly in gl_API.xml (Ilia)
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
---
src/mapi/glapi/gen/gl_API.xml | 4
1 file changed, 4 insertions(+)
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 00c9bb795c..6e00363b6f 100644
--- a/src/mapi
Suggested by Marek.
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
Cc: Marek Olšák
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
src/mesa/drivers/dri/i965/gen8_ps_state.c| 8
src/mesa/drivers/dri/i965
Suggested by Marek.
v2: Use new driver flag (Marek)
v3: Fix i965 comments (Lionel)
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
Cc: Marek Olšák
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
src/mesa/drivers/dri/i965
Hi Marek,
Can I have your r-b with this patch?
Cheers,
-
Lionel
On 12/12/16 12:30, Lionel Landwerlin wrote:
Suggested by Marek.
v2: Use new driver flag (Marek)
v3: Fix i965 comments (Lionel)
Signed-off-by: Lionel Landwerlin
Cc: Ilia Mirkin
Cc: Marek Olšák
---
src/mesa/drivers/dri
Reviewed-by: Lionel Landwerlin
On 14/12/16 09:41, Kenneth Graunke wrote:
This makes Gen7/7.5 match Gen8-9.
Signed-off-by: Kenneth Graunke
---
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel
Reviewed-by: Lionel Landwerlin
On 14/12/16 09:41, Kenneth Graunke wrote:
This will let us avoid ifdefs.
Signed-off-by: Kenneth Graunke
---
src/intel/genxml/gen8.xml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8
Hi,
Up to now, load_push_constant intrinsics generated by the spirv
compiler were hardcoded to have an offset of 0 and a range of 128.
This series adds a function compute those offset & range.
Cheers,
Lionel
Lionel Landwerlin (2):
spirv: move block_size() definition
spirv: compute
Signed-off-by: Lionel Landwerlin
---
src/compiler/spirv/vtn_variables.c | 85 +++--
src/intel/vulkan/anv_nir_lower_push_constants.c | 1 -
2 files changed, 66 insertions(+), 20 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv
Signed-off-by: Lionel Landwerlin
---
src/compiler/spirv/vtn_variables.c | 96 +++---
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index be64dd9550..f27d75cbec 100644
--- a
-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_pipeline.c | 26 --
1 file changed, 8 insertions(+), 18 deletions(-)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index
-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
v2: C is hard let's go shopping (Lionel)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_pipeline.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/genX_pipelin
-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
v2: C is hard let's go shopping (Lionel)
v3: Remove unnecessary condition in for loops (Lionel)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_pipeline.c | 20
1 file changed, 8 insertions(+), 12 dele
-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
v2: C is hard let's go shopping (Lionel)
v3: Remove unnecessary condition in for loops (Lionel)
v4: Document why we return on first failure (Eduardo)
Move i declaration inside for() (Eduardo)
Signed-off-by: Lionel Landwerlin
---
.
Leaving the previous VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT as this might be
expected even if the swapchain is created without any flag.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_wsi_wayland.c | 10 +++---
src/intel/vulkan/anv_wsi_x11.c | 3 ++-
2 files changed, 9
From: Lionel Landwerlin
The image usage specified by the caller of vkCreateSwapchainKHR should be
passed onto the internal image creation. Otherwise the driver might later
crash when the user tries to use the image as a combined sampler even though
the creation was explicitly created with
Tested-by: Lionel Landwerlin
On 23/07/16 00:28, Jason Ekstrand wrote:
Signed-off-by: Jason Ekstrand
Cc: "12.0"
---
src/intel/vulkan/genX_pipeline_util.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline_util.h
b/src/intel/vulkan/genX_pipel
We let the user believe we support some transfer formats which we don't.
This can lead to crashes when actually trying to use those formats.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_formats.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/
ments.
Signed-off-by: Lionel Landwerlin
Cc: Jason Ekstrand
---
src/intel/vulkan/anv_formats.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index b26e48a..1a3b19d 100644
--- a/src/intel/vulkan/anv_form
On 03/08/16 16:01, Jason Ekstrand wrote:
On Aug 3, 2016 5:53 AM, "Lionel Landwerlin"
mailto:lionel.g.landwer...@intel.com>>
wrote:
>
> We let the user believe we support some transfer destination formats
> which we don't. This can lead to crashes when actually
Fixes 6 failures from dEQP-VK.api.copy_and_blit.resolve_image.*
Tested on IVB/HSW
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/gen7_pipeline.c | 46 ++--
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/src/intel/vulkan
It doesn't seem like we have any support for 32bits of something + 8bits of
something else. This fixes
dEQP-VK.api.copy_and_blit.blit_image.all_formats.scaling_partial_d32_sfloat_s8_uint_d32_sfloat_s8_uint_nearest
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_formats.c | 2
Fixes 6 failures from dEQP-VK.api.copy_and_blit.resolve_image.*
Tested on IVB/HSW
v2: Program multisample dispatch mode correctly
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/gen7_pipeline.c | 46 ++--
1 file changed, 30 insertions(+), 16 deletions
On 05/08/16 18:08, Jason Ekstrand wrote:
On Aug 5, 2016 9:49 AM, "Lionel Landwerlin"
mailto:lionel.g.landwer...@intel.com>>
wrote:
>
> It doesn't seem like we have any support for 32bits of something +
8bits of
> something else.
Not quite. Depth-stencil
Signed-off-by: Lionel Landwerlin
Cc: anuj.pho...@gmail.com
---
src/intel/vulkan/gen7_pipeline.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 6acdd85..c2a38ac 100644
--- a/src/intel
201 - 300 of 1915 matches
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