At this point, the only thing it's used for is the opcode.
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs.h | 27 --
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 6 +--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 55 +++---
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs.h | 12 -
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 6 ++---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 37 +++-
3 files changed, 29 insertions(+), 26 deletions(-)
diff --git a
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 3f27364..2233621 100644
This lets us call dump_instructions() after register allocation without
failing an assertion.
This interacts trivially with my previous patch.
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa
On Fri, Aug 8, 2014 at 4:55 PM, Matt Turner wrote:
> Reviewed-by: Matt Turner
>
> I'll commit both of these tonight. (Does the vec4 backend have the
> same problem?)
AFAICT, it has the same problem that this patch fixes but not the last
patch. I would fix send another patch, but I'm not as famil
On Wed, Aug 6, 2014 at 6:29 PM, Marek Olšák wrote:
> What IR? A flatland GLSL IR? A replacement for Mesa IR? Something else?
It's a flatland IR, similar to TGSI/Direct3D style with enough GLSL
IR-like stuff to get existing things working now and enable us to
eventually do linking in it (so we can
On Mon, Aug 11, 2014 at 4:32 PM, Eric Anholt wrote:
> Connor Abbott writes:
>
>> On Wed, Aug 6, 2014 at 6:29 PM, Marek Olšák wrote:
>>> What IR? A flatland GLSL IR? A replacement for Mesa IR? Something else?
>>
>> It's a flatland IR, similar to TGSI/Dire
On Mon, Aug 11, 2014 at 11:22 AM, Matt Turner wrote:
> Comparing ~0u with a packed enum (i.e., 1 byte) always evaluates to
> false. Shouldn't gcc warn about this?
>
> Reported-by: Connor Abbott
> ---
> src/mesa/drivers/dri/i965/brw_eu.c | 2 +-
>
ts.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Whoops... I don't know much bash scripting so I'm glad you fixed up
what I wrote. I can't review this properly for the same reason, but it
at least it gets an
Acked-by: Connor Abbott
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
b/src/mesa/drivers/dri/i965/brw_fs.h
> index e7a82c4..d30b0b8 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -339,6 +339,7 @@ public:
> bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
> exec_list *acp);
>
On Tue, Jul 29, 2014 at 2:36 AM, Petri Latvala wrote:
> Add an optimization pass that drops min/max expression operands that
> can be proven to not contribute to the final result. The algorithm is
> similar to alpha-beta pruning on a minmax search, from the field of
> AI.
>
> This optimization pas
On Wed, Aug 13, 2014 at 9:04 PM, Matt Turner wrote:
> ---
> I'd squash this in at minimum. The changes are
>
> - Whitespace
> - Removal of unnecessary destructor
> - Renaming "one" and "two" to "a" and "b" (one->value.u[c0] <
> two->value.u[c0]...)
> - continue -> break
> - assert(!...) -> u
Signed-off-by: Connor Abbott
---
src/glsl/list.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/glsl/list.h b/src/glsl/list.h
index 3ee6cda..c402f48 100644
--- a/src/glsl/list.h
+++ b/src/glsl/list.h
@@ -644,6 +644,12 @@ inline void exec_node::insert_before(exec_list *before
7;s useful for codepaths that want to distinguish between
intrinsics and non-intrinsics without using strcmp.
Signed-off-by: Connor Abbott
---
src/glsl/link_functions.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/link_functions.cpp b/src/glsl/link_functions.cpp
index 2ce960
This includes all the instructions, ifs, loops, functions, etc. This is
similar to the information in ir.h.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources |2 +
src/glsl/nir/nir.h| 1150 +
src/glsl/nir/nir_intrinsics.c
eatures
(atomics and some system values):
https://github.com/cwabbott0/mesa/tree/nir-i965-fs
NIR has been what I've worked on for my entire summer internship at
Intel, and before I go off to my freshman year at college, I'd like to
thank the other Intel folks for the knowledge they'v
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources| 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_lower_atomics.c | 127 +++
3 files changed, 130 insertions(+)
create mode 100644 src/glsl/nir/nir_lower_atomics.c
diff --git
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 3 +-
src/glsl/nir/nir.h | 5 ++
src/glsl/nir/nir_lower_samplers.cpp | 170
3 files changed, 177 insertions(+), 1 deletion(-)
create mode 100644 src/glsl/nir
After we lower variables, we want to delete them in order to free up
some memory.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources| 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_remove_dead_variables.c | 138
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir.c| 4
src/glsl/nir/nir.h| 6 ++
src/glsl/nir/nir_lower_variables_scalar.c | 10 ++
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/glsl/nir/nir.c b/src/glsl
Signed-off-by: Connor Abbott
---
src/glsl/nir/README | 118
1 file changed, 118 insertions(+)
create mode 100644 src/glsl/nir/README
diff --git a/src/glsl/nir/README b/src/glsl/nir/README
new file mode 100644
index 000..2c81db9
--- /dev
After linking and inlining, this allows us to convert these registers
into SSA values and optimise more code.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_opt_global_to_local.c | 103
These include functions for adding and removing various bits of IR and
helpers for iterating over all the sources and destinations of an
instruction. This is similar to ir.cpp.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources |1 +
src/glsl/nir/nir.c| 1713
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 6 +-
src/glsl/nir/nir_types.cpp | 155 +
src/glsl/nir/nir_types.h | 78 +++
3 files changed, 238 insertions(+), 1 deletion(-)
create mode 100644 src/glsl/nir
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources|3 +-
src/glsl/nir/glsl_to_nir.cpp | 1759 ++
src/glsl/nir/glsl_to_nir.h | 40 +
3 files changed, 1801 insertions(+), 1 deletion(-)
create mode 100644 src/glsl/nir/glsl_to_nir.cpp
This is similar to ir_print_visitor.cpp.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h| 2 +
src/glsl/nir/nir_print.c | 916 ++
3 files changed, 919 insertions(+)
create mode 100644 src/glsl/nir
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources |1 +
src/glsl/nir/nir.h|4 +
src/glsl/nir/nir_lower_variables_scalar.c | 1241 +
3 files changed, 1246 insertions(+)
create mode 100644 src/glsl/nir
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_lower_system_values.c | 106 +
3 files changed, 109 insertions(+)
create mode 100644 src/glsl/nir
This is similar to ir_validate.cpp.
Signed-off-by: Connor Abbott
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_validate.c | 798
3 files changed, 801 insertions(+)
create mode 100644 src/glsl/nir
On Mon, Aug 18, 2014 at 9:26 AM, Petri Latvala wrote:
> On 08/14/2014 11:00 AM, Connor Abbott wrote:
>>
>>
>>
>> Another thing I'd like to see is to change minmax_range to call things
>> "low" and "high" instead of "range[0]" and
On Mon, Aug 18, 2014 at 8:44 AM, Roland Scheidegger wrote:
> Am 16.08.2014 02:12, schrieb Connor Abbott:
>> I know what you might be thinking right now. "Wait, *another* IR? Don't
>> we already have like 5 of those, not counting all the driver-specific
>> ones? Isn&
On Mon, Aug 18, 2014 at 11:47 AM, Jose Fonseca wrote:
> On 18/08/14 14:21, Marek Olšák wrote:
>>
>> On Mon, Aug 18, 2014 at 2:44 PM, Roland Scheidegger
>> wrote:
>>>
>>> Am 16.08.2014 02:12, schrieb Connor Abbott:
>>>>
>>>> I know w
On Mon, Aug 18, 2014 at 4:32 AM, Michel Dänzer wrote:
> On 16.08.2014 09:12, Connor Abbott wrote:
>> I know what you might be thinking right now. "Wait, *another* IR? Don't
>> we already have like 5 of those, not counting all the driver-specific
>> ones? Isn&
On Mon, Aug 18, 2014 at 12:38 PM, Ilia Mirkin wrote:
> On Mon, Aug 18, 2014 at 12:25 PM, Connor Abbott wrote:
>> On Mon, Aug 18, 2014 at 11:47 AM, Jose Fonseca wrote:
>>> On 18/08/14 14:21, Marek Olšák wrote:
>>> Once these are in place, all development effor
IR.
That would be cool. Once this stuff gets actually implemented, there's
probably going to be a lot of low-hanging fruit when it comes to
optimizations, especially since writing optimizations in SSA is so
easy!
Connor
>
> Regards,
> Thomas
>
> 2014-08-16 2:12 GMT+02:00 Conn
On Mon, Aug 18, 2014 at 8:52 PM, Michel Dänzer wrote:
> On 19.08.2014 01:28, Connor Abbott wrote:
>> On Mon, Aug 18, 2014 at 4:32 AM, Michel Dänzer wrote:
>>> On 16.08.2014 09:12, Connor Abbott wrote:
>>>> I know what you might be thinking right now. "Wait,
On Mon, Aug 18, 2014 at 1:38 PM, Roland Scheidegger wrote:
> Am 18.08.2014 19:05, schrieb Connor Abbott:
>> On Mon, Aug 18, 2014 at 12:38 PM, Ilia Mirkin wrote:
>>> On Mon, Aug 18, 2014 at 12:25 PM, Connor Abbott wrote:
>>>> On Mon, Aug 18, 2014 at 11:47 AM, Jose
On Tue, Aug 19, 2014 at 11:40 AM, Francisco Jerez wrote:
> Tom Stellard writes:
>
>> On Tue, Aug 19, 2014 at 11:04:59AM -0400, Connor Abbott wrote:
>>> On Mon, Aug 18, 2014 at 8:52 PM, Michel Dänzer wrote:
>>> > On 19.08.2014 01:28, Connor Abbott wrote:
>&
On Tue, Aug 19, 2014 at 3:57 PM, Tom Stellard wrote:
> On Tue, Aug 19, 2014 at 01:37:56PM -0700, Connor Abbott wrote:
>> On Tue, Aug 19, 2014 at 11:40 AM, Francisco Jerez
>> wrote:
>> > Tom Stellard writes:
>> >
>> >> On Tue, Aug 19, 2014 at 11:04:5
On Tue, Aug 19, 2014 at 11:33 PM, Francisco Jerez wrote:
> Connor Abbott writes:
>
>> On Tue, Aug 19, 2014 at 11:40 AM, Francisco Jerez
>> wrote:
>>> Tom Stellard writes:
>>>
>>>> On Tue, Aug 19, 2014 at 11:04:59AM -0400, Connor Abbott wrot
On Wed, Aug 20, 2014 at 2:41 AM, Michel Dänzer wrote:
> On 20.08.2014 00:04, Connor Abbott wrote:
>> On Mon, Aug 18, 2014 at 8:52 PM, Michel Dänzer wrote:
>>> On 19.08.2014 01:28, Connor Abbott wrote:
>>>> On Mon, Aug 18, 2014 at 4:32 AM, Michel Dänzer wrote:
>
nt, but you shouldn't try
> to handle backend specific swizzle operations and vectorizing restrictions
> in the IR. Just looking at the swizzle restrictions of R600 for example and
> I really can't imagine that you want to represent this in a common IR
> between all different d
On Wed, Aug 20, 2014 at 5:57 AM, Christian König
wrote:
> Am 20.08.2014 um 14:33 schrieb Connor Abbott:
>
>> On Tue, Aug 19, 2014 at 11:57 PM, Christian König
>> wrote:
>>>
>>> I think we can fix this by introducing new structured variants of the
>>
On Wed, Aug 20, 2014 at 7:01 AM, Francisco Jerez wrote:
> Connor Abbott writes:
>
>> On Tue, Aug 19, 2014 at 11:33 PM, Francisco Jerez
>> wrote:
>>> Connor Abbott writes:
>>>
>>>> On Tue, Aug 19, 2014 at 11:40 AM, Francisco Jerez
>>>
On Wed, Aug 20, 2014 at 12:11 PM, Francisco Jerez wrote:
> Connor Abbott writes:
>
>> On Wed, Aug 20, 2014 at 7:01 AM, Francisco Jerez
>> wrote:
>>> Connor Abbott writes:
>>>
>>>> On Tue, Aug 19, 2014 at 11:33 PM, Francisco Jerez
>>>
On Wed, Aug 20, 2014 at 12:17 PM, Tom Stellard wrote:
> On Tue, Aug 19, 2014 at 05:19:15PM -0700, Connor Abbott wrote:
>> On Tue, Aug 19, 2014 at 3:57 PM, Tom Stellard wrote:
>> > On Tue, Aug 19, 2014 at 01:37:56PM -0700, Connor Abbott wrote:
>> >> On Tue, Aug 1
On Thu, Aug 21, 2014 at 11:08 PM, Dave Airlie wrote:
> On 22 August 2014 12:46, Jason Ekstrand wrote:
>> On Thu, Aug 21, 2014 at 7:36 PM, Dave Airlie wrote:
>>>
>>> On 21 August 2014 19:10, Henri Verbeet wrote:
>>> > On 21 August 2014 04:56, Michel Dänzer wrote:
>>> >> On 21.08.2014 04:29, Hen
On Fri, Aug 22, 2014 at 11:27 AM, Christian König
wrote:
> Am 22.08.2014 um 17:13 schrieb Connor Abbott:
>
>> On Thu, Aug 21, 2014 at 11:08 PM, Dave Airlie wrote:
>>>
>>> On 22 August 2014 12:46, Jason Ekstrand wrote:
>>>>
>>>> On Thu, Aug 2
On Fri, Aug 22, 2014 at 11:27 AM, Christian König
wrote:
> Am 22.08.2014 um 17:13 schrieb Connor Abbott:
>
>> On Thu, Aug 21, 2014 at 11:08 PM, Dave Airlie wrote:
>>>
>>> On 22 August 2014 12:46, Jason Ekstrand wrote:
>>>>
>>>> On Thu, Aug 2
On Sat, Aug 23, 2014 at 5:14 AM, Christian König
wrote:
> Am 22.08.2014 um 18:01 schrieb Connor Abbott:
>
>> On Fri, Aug 22, 2014 at 11:27 AM, Christian König
>> wrote:
>>>
>>> Am 22.08.2014 um 17:13 schrieb Connor Abbott:
>>>
>>>
On Tue, Aug 26, 2014 at 4:34 PM, Thomas Helland
wrote:
> While I haven't heard about those projects, there's also GlassyMesa.
> Greg from LunarG (CC'd) posted about this to the mailing list. [1]
> However it looks like the github activity has stopped,
> and there's no new info on the projects webs
On Thu, Aug 28, 2014 at 5:07 AM, Christian König
wrote:
>> At least with the other components on which Mesa relies (e.g., libdrm,
>> 2D drivers, etc.) it's largely the same group of people with the same
>> set of goals.
>
>
> This was only true until Tom Stellard started to manage LLVM point relea
xes: https://bugs.freedesktop.org/show_bug.cgi?id=82828
CC: "10.3"
Signed-off-by: Connor Abbott
---
I think we could get rid of the node_classes array if we call
ra_alloc_interference_graph() earlier, but I don't know much about this
code so I just did the minimum amoun
As noted in the previous commit, this was introduced in
567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q test more
efficient"), but I forgot to mention it.
Signed-off-by: Connor Abbott
---
src/mesa/program/register_allocate.h | 5 -
1 file changed, 4 insertions(+),
q_total should never go below 0 (which is why it's defined as unsigned),
and if it does, then something is seriously wrong.
Signed-off-by: Connor Abbott
---
src/mesa/program/register_allocate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/program/register_allocate.c
b/src
On Sat, Sep 6, 2014 at 3:23 AM, Kenneth Graunke wrote:
> On Friday, September 05, 2014 08:59:32 PM Connor Abbott wrote:
>> q_total should never go below 0 (which is why it's defined as unsigned),
>> and if it does, then something is seriously wrong.
>>
>&
On Wed, Sep 10, 2014 at 8:45 AM, Emil Velikov wrote:
> Hello all,
>
> The original plan from Ian was to have four release candidates prior to the
> final release. From what I can see there has been no serious amount of patches
> nominated for 10.3-rc4, so I'm planning to keep with the plan and rel
On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24
> ++-
> src/mesa/drivers/dri/i965/intel_screen.h | 5 +
> 2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dr
On Sat, Sep 20, 2014 at 4:56 PM, Jason Ekstrand wrote:
>
>
> On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott wrote:
>>
>> On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand
>> wrote:
>> > ---
>> > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2
On Sat, Sep 20, 2014 at 5:58 PM, Jason Ekstrand wrote:
>
> On Sep 20, 2014 2:52 PM, "Connor Abbott" wrote:
>>
>> On Sat, Sep 20, 2014 at 4:56 PM, Jason Ekstrand
>> wrote:
>> >
>> >
>> > On Sat, Sep 20, 2014 at 12:44 PM, Connor Ab
.8735)
Signed-off-by: Connor Abbott
---
src/intel/compiler/brw_fs_validate.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_validate.cpp
b/src/intel/compiler/brw_fs_validate.cpp
index 676942c..cdccf0f 100644
--- a/src/intel/compiler/brw_fs_validate.cpp
+++ b/src/
On Sun, May 21, 2017 at 11:46 PM, Connor Abbott wrote:
> Surprisingly, profiling shows that this takes quite a lot of time. So
> turn it off when building in release mode, just like all the other
> validation passes we do.
>
> Difference at 95.0% confidence
>
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_opt_gcm.c | 72 ++
1 file changed, 23 insertions(+), 49 deletions(-)
diff --git a/src/compiler/nir/nir_opt_gcm.c b/src/compiler/nir/nir_opt_gcm.c
index 879a77a..0fdf587 100644
--- a/src/compiler/nir
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_intrinsics.h | 14 ++
src/compiler/nir/nir_opcodes.py | 18 --
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index 21e7d90
start handling a lot more instructions with similar constraints,
so we want to add a more formal model of what the optimizer can and
cannot do.
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir.h| 88 ++-
src/compiler/nir/nir_opcodes.py
These optimizations happened to work with derivatives, but they won't
with upcoming shader_ballot and group_vote instructions.
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_instr_set.c | 12
src/compiler/nir/nir_opt_peephole_select.c | 11 +++
2
Whoops, wrong address... let's try that again.
-- Forwarded message --
From: Connor Abbott
Date: Mon, Jun 5, 2017 at 12:22 PM
Subject: [PATCH 0/4] Core NIR support for ARB_shader_group_vote and
ARB_shader_ballot
To: mesa-de...@lists.freedesktop.org
Cc: Connor Abbott
things you'd want to do
on these instructions anyways. Maybe something like not(any(not(foo)))
-> all(foo) and vice-versa?
>
> On Mon, Jun 5, 2017 at 12:22 PM, Connor Abbott wrote:
>>
>> Signed-off-by: Connor Abbott
>> ---
>> src/compiler/
2017 at 1:50 PM, Connor Abbott wrote:
>>
>> On Mon, Jun 5, 2017 at 1:37 PM, Jason Ekstrand
>> wrote:
>> > I'm not sure how I feel about having these as ALU operations. ALU
>> > operations are generally pure functions (with the exception derivative)
>
On Tue, Jun 6, 2017 at 1:45 PM, Jason Ekstrand wrote:
>
>
> On Mon, Jun 5, 2017 at 9:52 PM, Jason Ekstrand wrote:
>>
>> On Mon, Jun 5, 2017 at 6:37 PM, Connor Abbott wrote:
>>>
>>> I pushed a v2 at
>>> https://cgit.freedesktop.org/~cwabbott0/mesa
On Tue, Jun 6, 2017 at 1:48 PM, Connor Abbott wrote:
> On Tue, Jun 6, 2017 at 1:45 PM, Jason Ekstrand wrote:
>>
>>
>> On Mon, Jun 5, 2017 at 9:52 PM, Jason Ekstrand wrote:
>>>
>>> On Mon, Jun 5, 2017 at 6:37 PM, Connor Abbott wrote:
>>>>
>
From: Dave Airlie
I'm not 100% sure this is all wired up but it looks like it is.
v2: actually enable extension.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 2 +-
src/amd/vulkan/radv_pipeline.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vu
From: Connor Abbott
We implement the split opcodes, and tell NIR to lower the original ones.
The lowering to LLVM is a little more complicated, but NIR can optimize
the split ones a little better, and some NIR lowering passes that we
might want to use (particularly for doubles) emit the split
From: Connor Abbott
This series fixes a few things I noticed while adding support for the
shader ballot extension to radv. In order to convert from the GLSL
semantics to the SPIR-V semantics for ballotARB(), glslang inserts a
call to unpackUint2x32, which maps to OpBitcast in SPIR-V which we
From: Connor Abbott
Before, we were just implementing it with a move, which is incorrect
when the source and destination have different bitsizes. To implement
it properly, we need to use the 64-bit pack/unpack opcodes. Since
glslang uses OpBitcast to implement packInt2x32 and unpackInt2x32, this
From: Connor Abbott
This series adds tests for the bugs fixed in "Fixes for 64-bit support
on radv and anv". It also adds some stuff that will be useful for
testing the shader ballot and shader group vote extensions. Apparently
the Vulkan CTS will be getting better int64 support soon,
From: Connor Abbott
Right now, if you try to put something like:
in a shader, the C preprocessor will try to interpret that line and
barf. Now glsl_scraper.py will strip out ///, so you can do something
like:
///#extension GL_foo : enable
and it'll be ignored when compiling the file i
From: Connor Abbott
This helper creates and submits a pipeline with a very simple vertex
shader and two triangles that cover the viewport. The user gives a
fragment shader and optionally some push constants. The idea is to avoid
boilerplate for tests that specifically test shader-only
From: Connor Abbott
For whatever reason, glslang requires GLSL 4.50 for enabling
GL_ARB_shader_ballot, even though it doesn't have any version
requirement. And GL_ARB_gpu_shader_int64 does officially require GLSL
4.00, which means that int64 tests will need to use at least that
version. Bu
From: Connor Abbott
(un)packUint2x32() was broken on anv, and all four functions were
broken on radv.
Signed-off-by: Connor Abbott
---
Makefile.am | 2 +
src/tests/func/shader/pack_unpack.c | 172
2 files changed, 174 insertions
(forgot to Cc Jason)
On Thu, Jun 8, 2017 at 3:05 PM, Connor Abbott wrote:
> From: Connor Abbott
>
> Before, we were just implementing it with a move, which is incorrect
> when the source and destination have different bitsizes. To implement
> it properly, we need to use the 64-
Reviewed-by: Connor Abbott
On Tue, Jun 6, 2017 at 4:25 PM, Grazvydas Ignotas wrote:
> This will allow to constify other things.
>
> Signed-off-by: Grazvydas Ignotas
> ---
> src/compiler/nir/nir.h | 25 +
> src/compiler/nir/nir_lower_io.c
From: Connor Abbott
v2: make every instruction an intrinsic, add missing subgroup_size,
also add system value translation stuff
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir.c| 28
src/compiler/nir/nir_intrinsics.h | 30
From: Connor Abbott
This series adds all the bits to enable EXT_shader_subgroup_vote and
EXT_shader_subgroup_ballot for radv. It's based on my previous series to
fix some 64-bit bugs in radv and anv, since nothing would work without
them.
Patches 1-4 are a resend of my previous series t
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_opt_gcm.c | 72 ++
1 file changed, 23 insertions(+), 49 deletions(-)
diff --git a/src/compiler/nir/nir_opt_gcm.c b/src/compiler/nir/nir_opt_gcm.c
index 879a77a..0fdf587 100644
From: Connor Abbott
These optimizations happened to work with derivatives, but they won't
with upcoming shader_ballot and group_vote instructions.
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_instr_set.c | 22 ++
src/compile
From: Connor Abbott
These are properties of the instruction that must be respected when
moving it around, in addition to the usual SSA dominance guarantee.
Previously, we only had special handling for fddx and fddy, in a very
ad-hoc way. But with arb_shader_ballot and arb_shader_group_vote
From: Connor Abbott
Lower them to the GL version.
Signed-off-by: Connor Abbott
---
src/compiler/nir/nir_lower_system_values.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/compiler/spirv/nir_spirv.h | 2 +
src/compiler/spirv/spirv_to_nir.c | 80 ++
src/compiler/spirv/vtn_variables.c | 28 +
3 files changed, 110 insertions(+)
diff --git a/src/compiler
From: Connor Abbott
For SPIR-V, Khronos decided to make the SubGroup*Mask system values
consist of 4 32-bit components rather than one 64-bit component.
Although we'll lower away the difference in nir_lower_system_values so
drivers won't have to deal with them, adding these system va
From: Connor Abbott
We're about to bump the number of system values above 32. The
system_values_read bitfield itself is 64 bits, but some users weren't
taking that into account. Fix the ones I could find by grepping for
"system_values_read". This prevents regressions at lea
From: Connor Abbott
To match si_shader_context.
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 2 ++
src/amd/common/ac_llvm_build.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 237e929..c411880
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 1 +
src/amd/common/ac_llvm_build.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index c4cf7ce..472a1b8 100644
--- a/src/amd/common
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 26 ++
src/amd/common/ac_llvm_build.h | 4
src/gallium/drivers/radeonsi/si_shader.c | 38 +---
3 files changed, 36 insertions(+), 32
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 43 ++
src/amd/common/ac_llvm_build.h | 2 ++
src/gallium/drivers/radeonsi/si_shader.c | 45 ++--
3 files changed, 47 insertions
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 1 +
src/amd/common/ac_llvm_build.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 8145bcb..efbeb65 100644
--- a/src/amd/common
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 24 +++
src/amd/common/ac_llvm_build.h | 2 ++
src/gallium/drivers/radeonsi/si_shader.c | 41 +++-
3 files changed, 34 insertions(+), 33
From: Connor Abbott
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 30 ++
src/amd/common/ac_llvm_build.h | 6 ++
src/gallium/drivers/radeonsi/si_shader.c | 24 +++-
3 files changed, 39 insertions(+), 21
From: Connor Abbott
Ported from radeonsi. Needed for emitting optimization barriers, which
contain inline asm.
Signed-off-by: Connor Abbott
---
src/amd/common/ac_llvm_util.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
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