Signed-off-by: Connor Abbott <connor.abb...@intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 ++++++++--------
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index f62c6a1..482b92f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -381,7 +381,7 @@ public:
fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
fs_reg sample_index, bool has_offset,
fs_reg offset, fs_reg mcs, int sampler);
- fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
+ fs_reg emit_mcs_fetch(fs_reg coordinate, int components, int sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index e5d29ae..84e83b9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -406,7 +406,7 @@ fs_visitor::emit_fragment_program_code()
fs_reg coordinate = src[0];
fs_reg shadow_c;
fs_reg sample_index;
- fs_reg offset;
+ fs_reg offset_reg;
switch (fpi->Opcode) {
case OPCODE_TEX:
@@ -490,7 +490,7 @@ fs_visitor::emit_fragment_program_code()
fs_inst *inst;
if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, false, offset, fs_reg(0u), fpi->TexSrcUnit);
+ inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, false, offset_reg, fs_reg(0u), fpi->TexSrcUnit);
} else if (brw->gen >= 5) {
inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy,
sample_index, false);
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 6e54e70..adbdf42 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1721,27 +1721,26 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg
coordinate,
/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
-fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler)
+fs_visitor::emit_mcs_fetch(fs_reg coordinate, int components, int sampler)
{
int reg_width = dispatch_width / 8;
- int length = ir->coordinate->type->vector_elements;
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(length),
+ fs_reg payload = fs_reg(GRF, virtual_grf_alloc(components),
BRW_REGISTER_TYPE_F);
fs_reg dest = fs_reg(this, glsl_type::uvec4_type);
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, length);
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, components);
/* parameters are: u, v, r; missing parameters are treated as zero */
- for (int i = 0; i < length; i++) {
+ for (int i = 0; i < components; i++) {
sources[i] = fs_reg(this, glsl_type::float_type);
emit(MOV(retype(sources[i], BRW_REGISTER_TYPE_D), coordinate));
coordinate.reg_offset++;
}
- emit(LOAD_PAYLOAD(payload, sources, length));
+ emit(LOAD_PAYLOAD(payload, sources, components));
fs_inst *inst = emit(SHADER_OPCODE_TXF_MCS, dest, payload);
inst->base_mrf = -1;
- inst->mlen = length * reg_width;
+ inst->mlen = components * reg_width;
inst->header_present = false;
inst->regs_written = 4; /* we only care about one reg of response,
* but the sampler always writes 4/8
@@ -1838,7 +1837,8 @@ fs_visitor::visit(ir_texture *ir)
sample_index = this->result;
if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask &
(1<<sampler))
- mcs = emit_mcs_fetch(ir, coordinate, sampler);
+ mcs = emit_mcs_fetch(coordinate,
+ ir->coordinate->type->vector_elements, sampler);
else
mcs = fs_reg(0u);
break;
--
1.9.3
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