On Wed, Feb 10, 2016 at 10:27:46AM +0200, Pohjolainen, Topi wrote:
> On Tue, Feb 09, 2016 at 12:05:52PM -0800, Ben Widawsky wrote:
> > On Mon, Feb 08, 2016 at 06:51:21PM +0200, Topi Pohjolainen wrote:
> > > Signed-off-by: Topi Pohjolainen
> > > ---
>
On Wed, Feb 10, 2016 at 02:13:27PM +0200, Pohjolainen, Topi wrote:
> On Tue, Feb 09, 2016 at 05:34:53PM -0800, Ben Widawsky wrote:
> > On Mon, Feb 08, 2016 at 06:51:20PM +0200, Topi Pohjolainen wrote:
> > > This series enables compression for single sampled color surfaces,
>
On Thu, Feb 11, 2016 at 07:03:56PM +1300, Chris Forbes wrote:
> Signed-off-by: Chris Forbes
After offline discussion with Chris:
Reviewed-by: Ben Widawsky
Though in fairness, I don't use this as much as others, so it might be nice to
have someone chime in who is absolutely depe
This allows ls, and scripts to get the file names in the correct order of
optimization.
Cc: Chris Forbes
Cc: Matt Turner
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions
On Thu, Feb 11, 2016 at 08:33:54PM +0200, Topi Pohjolainen wrote:
> This makes the logic a little more explicit and helps to keep
> subsequent patches easier to read.
>
> Suggested-by: Ben Widawsky
> Signed-off-by: Topi Pohjolainen
Reviewed-by: Ben W
BO_ALLOC_FOR_RENDER : 0;
>perf_debug("%dx%d miptree larger than aperture; falling back to
> X-tiled\n",
> mt->total_width, mt->total_height);
I still dislike this code, but it's a big improvement. I primarily
On Thu, Feb 11, 2016 at 08:33:56PM +0200, Topi Pohjolainen wrote:
> In addition to simply calling miptree_create() the higher level
> call intel_miptree_create() also considers if the buffer should
> be associated with an auxiliary buffer based on the given format.
>
> Here we are allocating an au
is more direct path available lets start using it
> instead and stop even checking for such (im)possibility.
>
> v2 (Ben): Do not signal msaa layout with explicit argument but
> using layout_flags instead.
>
> Signed-off-by: Topi Pohjolainen
> Reviewed-by: Ben Widawsky
On Thu, Feb 11, 2016 at 08:33:58PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 ++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4
> 2 files changed, 30 insertions(+)
>
> diff --git
ry Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
> HALIGN
> - * 16 must be used."
> - */
> - if (brw->gen >= 9 || mt->num_samples == 1)
> - assert(mt->halign == 16);
> - }
> + struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
pretty sure you could const this too if you wanted. It shouldn't be changing
after this point.
> + const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
>
> uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
>
I'd like to see surf_type removed unless you have plans for it. Otherwise:
Reviewed-by: Ben Widawsky
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> fixing state restore mechanism in i965-meta operations.
>
> v2 (Ben): Use combination of msaa_layout and number of samples
>instead of introducing explicit type for lossless
>compression.
>
Other than the comments I left,
patch 6, 7, 9, 10 are:
Revie
On Fri, Feb 12, 2016 at 09:24:42AM +0200, Pohjolainen, Topi wrote:
> On Thu, Feb 11, 2016 at 01:41:47PM -0800, Ben Widawsky wrote:
> > On Thu, Feb 11, 2016 at 08:33:56PM +0200, Topi Pohjolainen wrote:
> > > In addition to simply calling miptree_create() the highe
no longer applies on Gen8+.
>
> Signed-off-by: Kenneth Graunke
Reviewed-by: Ben Widawsky
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
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Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 8c687b3..1efcca2 100644
--- a/src
Now that the check is restricted to gen8+, we should always get back a non-zero
positive value for the EU and subslice counts.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 35 +++-
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index c6eb50a..8c687b3 100644
--- a
On Fri, Apr 08, 2016 at 01:57:44PM -0700, Kenneth Graunke wrote:
> We just never bothered to decode this.
>
> Signed-off-by: Kenneth Graunke
Series is:
Reviewed-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_disasm.c | 5 +
> 1 file changed, 5 insertions(+)
>
the kernel returns
ENODEV when it shouldn't be. I will investigate this separately.
Reported-by: Chris Forbes
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_
On Tue, Apr 12, 2016 at 10:10:35AM +0200, Alejandro Piñeiro wrote:
>
>
> On 11/04/16 18:49, Ben Widawsky wrote:
> > This will fix the spurious error message: "Failed to query GPU properties."
> > that was unintentionally added in cc01b63d730.
> >
> > T
rmance on Skylake GT3e by about 50%
> by letting it use repclears instead of slow clears.
>
> Cc: Ben Widawsky
> Cc: Topi Pohjolainen
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Kenneth Graunke
Reviewed-by: Ben Widawsky
_
From: Ben Widawsky
Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.
Note that the buffer allocation done for
On Fri, May 01, 2015 at 04:54:36PM +0100, Neil Roberts wrote:
> Sorry for the really long delay in replying! This patch is still needed
> in order to fix a number of Piglit tests so it would be good to get it
> landed.
>
> Ben Widawsky writes:
>
> > Sorry for the d
On Fri, Apr 24, 2015 at 08:47:41PM +0300, Pohjolainen, Topi wrote:
> On Thu, Apr 23, 2015 at 04:50:00PM -0700, Ben Widawsky wrote:
> > AFAICT, none of the old data was wrong (the gen7 decoder), but it wa
> > smissing a
> > bunch of stuff.
> >
> > Adds a tick (
On Thu, Apr 23, 2015 at 09:35:23PM -0700, Matt Turner wrote:
> On Thu, Apr 23, 2015 at 4:50 PM, Ben Widawsky
> wrote:
> > AFAICT, none of the old data was wrong (the gen7 decoder), but it wa
> > smissing a
> > bunch of stuff.
> >
> > Adds a tick (') to
On Fri, May 15, 2015 at 07:49:44PM -0700, Ben Widawsky wrote:
> On Thu, Apr 23, 2015 at 09:35:23PM -0700, Matt Turner wrote:
> > On Thu, Apr 23, 2015 at 4:50 PM, Ben Widawsky
> > wrote:
> > > AFAICT, none of the old data was wrong (the gen7 decoder), but it wa
> &g
On Fri, Apr 24, 2015 at 09:05:44PM +0300, Pohjolainen, Topi wrote:
> On Thu, Apr 23, 2015 at 04:50:02PM -0700, Ben Widawsky wrote:
> > Gen9 surface state is very similar to the previous generation. The important
> > changes here are aux mode, and the way clear colors work.
> >
On Fri, May 15, 2015 at 08:22:29PM -0700, Ben Widawsky wrote:
> On Fri, Apr 24, 2015 at 09:05:44PM +0300, Pohjolainen, Topi wrote:
> > On Thu, Apr 23, 2015 at 04:50:02PM -0700, Ben Widawsky wrote:
> > > Gen9 surface state is very similar to the previous generation. Th
Recommended-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 436
1 file changed, 219 insertions(+), 217 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965
factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
v2: Line length fixes, and const usage (Topi)
Safer initialization of name string (Topi)
Signed-off-by: Ben Widawsky
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri
: Ben Widawsky
Cc: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_defines.h| 2 ++
src/mesa/drivers/dri/i965/brw_state_dump.c | 44 --
2 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers
round some of the gen8
surface setup code.
v3: Use ralloc_asprintf instead of asprintf to be more friendly to non-GNU
platforms.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.h| 1 +
src/mesa/drivers/dri/i965/brw_state.h | 13 -
src/mesa/dr
is makes some of
the sample output in subsequent commits slightly incorrect.
v3: Use the name from the table (Ken). This requires declaring the surface
format array as extern, and declaring the struct in the .h file.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.h
ff-by: Ben Widawsky
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index aa63c15..ca5a622 100644
07980:BIND0: surface state address
0x7924: 0x7940:BIND1: surface state address
v2: Style cleanups (Matt)
Fix aux mode dword 7->6 (Topi)
Use exp2 instead of pow (Matt)
Add dwords 8-12 to the dump
Signed-off-by: Ben Widawsky
Cc: Matt Turner
Reviewed-by: Topi Pohjolainen
---
sr
|CLAMP|WRAP
v2: Move GET_BITS macro to here (with paren protection) Ben/Topi
Add const to the sampler pointer (Topi)
Signed-off-by: Ben Widawsky
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_state_dump.c | 71
On Mon, May 18, 2015 at 11:02:32AM +0300, Pohjolainen, Topi wrote:
> On Fri, May 15, 2015 at 10:06:22PM -0700, Ben Widawsky wrote:
> > Gen9 surface state is very similar to the previous generation. The important
> > changes here are aux mode, and the way clear colors work.
> >
On Mon, May 18, 2015 at 11:26:47AM +0300, Pohjolainen, Topi wrote:
> On Fri, May 15, 2015 at 10:06:23PM -0700, Ben Widawsky wrote:
> > This patch is optional in the series. It does make the output much cleaner,
> > but
> > there is some risk.
>
> What is the risk, I co
d of the now useless helper in the state_dump.c
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
Reviewed-by: Topi Pohjolainen (v3)
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_dump.c | 18 +++---
src/mesa/drivers/
rray applies as a cube surface.
It's not well understood why this is needed, but it seems like it is. No
changes in piglit (the g45 results are invalid).
http://otc-gfxtest-01.jf.intel.com/view/dev/job/bwidawsk/118/
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layo
somewhat surprised that it seems to
have no impact on BDW as the restriction is needed there as well.
Cc: mesa-sta...@lists.freedesktop.org
Cc: Anuj Phogat
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
Reviewed-by: Neil Roberts
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 12
TEXT_BYTE_PACKED (1 << 16)
>
> @@ -95,11 +97,42 @@
> #define XY_BLT_WRITE_RGB (1 << 20)
> #define XY_SRC_TILED (1 << 15)
> #define XY_DST_TILED (1 << 11)
> +#define XY_SRC_TILED_X (1 << 20)
> +#define
mination of
the TILING would be better off in choose (and making the verb choose correct in
the process).
if ((brw->gen >= 9 && !for_bo && false /* disable Yf/Ys */) {
if (intel_miptree_choose_tr_mode(brw, format...))
return;
}
> +
> + if (!mt)
> + r
the right thing to do. But, It helps
> move things forward at the moment.
I don't understand them either, but I think your code is fine. Maybe add an
assert that max level is < 15?
So with some explanation in the commit message that this disables mip tails,
this is:
Reviewed-by: Ben Wida
On Thu, May 21, 2015 at 05:46:48PM -0700, Anuj Phogat wrote:
> On Thu, May 21, 2015 at 12:26 PM, Ben Widawsky wrote:
SNIP
> > As I mentioned above wrt the CL alignment, I think it's safe to do for both
> > modes. Something like:
> >
> > /* Check both are at l
== MESA_FORMAT_S_UINT8)
>return 8;
>
> + if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
> + uint32_t align = tr_mode_horizontal_texture_alignment(brw, mt);
> + /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */
> + return align < 32 ? 32 : align;
> + }
> +
> if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
>return 8;
>
Seems a bit weird to me to split up HALIGN/VALIGN into separate patches, but
it's up to you.
Reviewed-by: Ben Widawsky
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On Fri, Apr 17, 2015 at 04:51:29PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_te
On Wed, May 27, 2015 at 11:56:24AM -0700, Ben Widawsky wrote:
> On Fri, Apr 17, 2015 at 04:51:28PM -0700, Anuj Phogat wrote:
> > Signed-off-by: Anuj Phogat
> > ---
> > src/mesa/drivers/dri/i965/brw_tex_layout.c | 80
> > ++
> &g
t; + if (brw->gen >= 9 && (mt->target == GL_TEXTURE_1D ||
> + mt->target == GL_TEXTURE_1D_ARRAY))
> + return 1;
I think this hunk can go away with Neil's patches since then.
> +
> + if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
> + uint32_t align =
to it and I will review it).
Cc: Matt Turner
Cc: Neil Roberts
Cc: Mark Janes
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compac
I forgot to mention that the predecessor to this patch fixed around 70 BSW
failures on Jenkins. Note that our current Jenkins baseline for BSW is probably
not fully baked atm.
On Wed, May 27, 2015 at 10:16:04PM -0700, Ben Widawsky wrote:
> AFAICT, there is no real way to make sure a send mess
On Thu, May 28, 2015 at 07:00:38AM -0700, Matt Turner wrote:
> On Thu, May 28, 2015 at 3:31 AM, Neil Roberts wrote:
> > Ben Widawsky writes:
> >
> >> AFAICT, there is no real way to make sure a send message with EOT is
> >> properly ignored from compact, nor c
On Thu, May 28, 2015 at 11:31:40AM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > AFAICT, there is no real way to make sure a send message with EOT is
> > properly ignored from compact, nor can I see a way to actually encode
> > EOT while compacting. Before the
Just like the previous patch, but for the GEN9 constraints.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
This helped find the incorrect HALIGN values from the previous patches.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965
rface.
When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
be used.
With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.
Cc: Anuj Phogat
Cc: Neil Roberts
Signed-off-by: Ben Widawsky
---
s
to be known all the way at the
lowest levels of the create/allocation, disable_aux_buffers is currently one
such example. There will be another example coming up in a few patches.
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_fbo.c | 5 +-
src/mesa/dr
SKL
(https://bugs.freedesktop.org/show_bug.cgi?id=90561). I don't remember seeing
any fixes on BDW, but I do know reverting Anuj's original implementation does
nothing to piglit either.
Cc: Anuj Phogat
Cc: Jordan Justen
Ben Widawsky (6):
i965: Consolidate certain miptree params to flags
i
#x27;t actually do anything since SKL doesn't yet use fast
clears, and that's the only case we can get to this function (by way of
intel_update_winsys_renderbuffer_miptree)
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
1 file changed, 2 insertions(
the miptree. I am torn as to whether or not it was a good
idea to remove "non_msrt" since it's a really nice thing for grep.
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37 +++
src/mesa/drivers/dri/i965/in
On Thu, May 28, 2015 at 04:58:23PM -0700, Matt Turner wrote:
> On Wed, May 27, 2015 at 10:16 PM, Ben Widawsky
> wrote:
> > AFAICT, there is no real way to make sure a send message with EOT is
> > properly
> > ignored from compact, nor can I see a way to actually encode
addr, brw_imm_ud(base_binding_table_index));
> + if (base_binding_table_index)
> + brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
>brw_AND(p, addr, addr, brw_imm_ud(0xfff));
>
>brw_pop_insn_state(p);
Both are:
Acked-by: Ben Widawsky
While here, you've probably seen this before, but I just noticed for SIMD8 GS on
BDW:
"Not valid for objects with more than 6 vertices per object."
Probably we don't care, but SPF might be effected by this patch, broken, or
fixed by this - I can't quite tell which.
This s
GEN7_GS_DISPATCH_MODE) |
> ((brw->gs.prog_data->invocations - 1) <<
>GEN7_GS_INSTANCE_CONTROL_SHIFT) |
>GEN6_GS_STATISTICS_ENABLE |
> diff --git a/src/mesa/drivers/dri/i965/gen8_vs_
rw->gs.base, &brw->gs.prog_data->base.base, false);
> + &brw->gs.base, &prog_data->base, dword_pitch);
> }
>
> const struct brw_tracked_state brw_gs_ubo_surfaces = {
See comment in the previous patch... but as you like:
Reviewed-by: Ben Wida
lly do anything behaviorally.
NOTE: gen8+ should have no change at all since MOCS was always 0 anyway.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/m
On Tue, 02 Jun 2015 20:32:13 -0700
Kenneth Graunke wrote:
> On Tuesday, June 02, 2015 08:07:50 PM Ben Widawsky wrote:
> > I'm very confused here. It seems pretty clear that since the
> > command has been introduced with support for MOCS, MOCS lives at
> > bit 8 o
On Wed, Jun 03, 2015 at 12:20:09AM -0700, Kenneth Graunke wrote:
> On Tuesday, June 02, 2015 11:41:56 PM Ben Widawsky wrote:
> > On Tue, 02 Jun 2015 20:32:13 -0700
> > Kenneth Graunke wrote:
> >
> > > On Tuesday, June 02, 2015 08:07:50 PM Ben Widawsky wrote:
>
On Wed, Jun 03, 2015 at 01:09:50PM +0100, Neil Roberts wrote:
> Looks good to me. Thanks for fixing this. I guess I still have more to
> learn about the ISA.
>
> However, should we not also fix the vec4 version? With that,
>
> Reviewed-by: Neil Roberts
>
> If we wanted to play safe and avoid th
On Wed, Jun 03, 2015 at 12:45:12PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 03, 2015 at 10:05:25AM +0300, Abdiel Janulgue wrote:
> >
> > On 06/02/2015 08:28 PM, Kenneth Graunke wrote:
> > > On Tuesday, June 02, 2015 03:23:35 PM Abdiel Janulgue wrote:
> > >>
> > >> On 06/02/2015 09:31 AM, Kenneth
On Wed, Jun 03, 2015 at 12:05:34PM -0700, Kenneth Graunke wrote:
> On Wednesday, June 03, 2015 09:44:21 AM Ben Widawsky wrote:
> > On Wed, Jun 03, 2015 at 12:45:12PM +0300, Ville Syrjälä wrote:
> > > On Wed, Jun 03, 2015 at 10:05:25AM +0300, Abdiel Janulgue wrote:
> > >
On Wed, Jun 03, 2015 at 12:34:56PM -0700, Ben Widawsky wrote:
> On Wed, Jun 03, 2015 at 12:05:34PM -0700, Kenneth Graunke wrote:
> > On Wednesday, June 03, 2015 09:44:21 AM Ben Widawsky wrote:
> > > On Wed, Jun 03, 2015 at 12:45:12PM +0300, Ville Syrjälä wrote:
> > > &
nt requirements.
> Make can_fast_copy_blit() helper.
> Use ffs(), is_power_of_two()
> Move overlap computation inside intel_miptree_blit().
> Use XY_FAST prefix for the macros.
>
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa
On Tue, Jun 02, 2015 at 04:04:08PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> Patch can be squashed with 17/22. I kept it separate for easy review.
This part is:
Reviewed-by: Ben Widawsky
I don't mind keeping i
hoose_tr_mode() actually choose TRMODE. (Ben)
> Few cosmetic changes.
>
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
>
> ---
> I think we need some benchmarking to come up with conditions to
> choose Ys (64 KB) over Yf (4 KB). Any thoughts on minimum texture
> size
totally optional. I'd be willing to just always use buffer #2 on
gen8+. Pre-HSW this wasn't allowed, but it looks like it's okay for GEN8 too.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state.h | 6 +--
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
s
n I can revisit this.
Anuj ran this on his SKL and said there were no fixes on regressions. There is
some hope it fixes BXT issues.
Cc: Imre Deak
Cc: Neil Roberts
Cc: Anuj Phogat
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen7_vs_state.c | 48 ++-
1 f
Here is the diff compared to v1, with the r-b tags I got. I've only compile
tested this, but I'll send it through jenkins before push.
Thanks for the comments.
Cc: "Pohjolainen, Topi"
Reviewed-by: Chad Versace
Reviewed-by: Anuj Phogat
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/
On Fri, May 29, 2015 at 12:07:36PM -0700, Chad Versace wrote:
> On Fri 29 May 2015, Pohjolainen, Topi wrote:
> > On Fri, May 29, 2015 at 09:32:53AM +0300, Pohjolainen, Topi wrote:
> > > On Thu, May 28, 2015 at 10:21:29AM -0700, Ben Widawsky wrote:
> > > > I think pr
On Fri, May 29, 2015 at 12:27:17PM -0700, Chad Versace wrote:
> On Thu 28 May 2015, Ben Widawsky wrote:
> > There are several constraints when determining if one can fast clear a
> > surface.
> > Some of these are alignment, pixel density, tiling formats, and others
On Fri, May 29, 2015 at 05:21:14PM -0700, Chad Versace wrote:
> On Fri 29 May 2015, Chad Versace wrote:
> > On Thu 28 May 2015, Ben Widawsky wrote:
> > > This restriction was attempted in this commit:
> > > commit 47053464630888f819ef8cc44278f1a1220159b9
> >
On Fri, May 29, 2015 at 05:06:09PM -0700, Chad Versace wrote:
> On Thu 28 May 2015, Ben Widawsky wrote:
> > Just like the previous patch, but for the GEN9 constraints.
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c
On Wed, Jun 03, 2015 at 05:42:10PM -0700, Matt Turner wrote:
> On Wed, Jun 3, 2015 at 5:29 PM, Kenneth Graunke wrote:
> > On Wednesday, June 03, 2015 11:35:43 PM Bish, Jim wrote:
> >> For BDW and newer hardware, vertex shaders can be dispatched
> >> using simd8 scalars, but when spills occur perfo
On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
> On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
> > Shader programs are cached per stage (FS, VS, GS) using the
> > corresponding shader source identifier and compile time choices
> > as key. However, one not onl
On Wed, Mar 11, 2015 at 10:01:24AM +0100, Eduardo Lima Mitev wrote:
> Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1,
> and page 88 of the OpenGL 4.5 specs state:
>
> "An INVALID_VALUE error is generated if count or length is negative.
> An INVALID_ENUM error is genera
On Wed, Mar 11, 2015 at 10:01:25AM +0100, Eduardo Lima Mitev wrote:
> Section '8.6 Alternate Texture Image Specification Commands', page 161 of the
> OpenGL ES 3.1 spec, and page 207 of the same section in the OpenGL 4.5 spec
> state in relation to CopyTexImage2D method:
>
> "An INVALID_ENUM e
sible 5%
performance win if avoided.
Recommended-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_clear.c | 5 +++--
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 6 --
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/dr
gnore it.
Example:
Multi-LOD fast clear - giving up (256x128x8).
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 4
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src
patch series I never landed which touches some of the same code
for similar purposes.
http://lists.freedesktop.org/archives/mesa-dev/2015-March/079001.html
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
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igned-off-by: Ben Widawsky
Reviewed-by: Chad Versace
Reviewed-by: Anuj Phogat
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/dr
Just like the previous patch, but for the GEN9 constraints.
v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.
Signed-off-by: Ben Widawsky
Cc: Chad Versace
Reviewed-by: Anuj
or grep.
v2:
Reword some comments (Chad)
intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad)
Make full if ladder for for gens in above function (Chad)
Signed-off-by: Ben Widawsky
Cc: Chad Versace
Cc: Topi Pohjolainen
Reviewed-by: Jordan Justen
Reviewed-by: Anuj Phogat
---
src/mes
rface.
When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
be used.
With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.
v2:
bugfix: Don't set HALIGN16 for gens before 8 (Chad)
Signed-off-
#x27;t actually do anything since SKL doesn't yet use fast
clears, and that's the only case we can get to this function (by way of
intel_update_winsys_renderbuffer_miptree)
Signed-off-by: Ben Widawsky
Reviewed-by: Chad Versace
Reviewed-by: Jordan Justen
Reviewed-by: Anuj Phogat
---
x27; instead of !!X (everyone except Chad)
Signed-off-by: Ben Widawsky
Cc: "Pohjolainen, Topi"
Reviewed-by: Chad Versace
Reviewed-by: Anuj Phogat
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_fbo.c | 5 +-
src/mesa/drivers/dri/i965/
Previously the number needed to be divided by 4 to get the proper results. Now
the hardware does the right thing. Through experimentation it seems Braswell
(CHV) does also need this.
Fixes piglit test:
arb_pipeline_statistics_query-frag
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
On Mon, Jun 08, 2015 at 03:50:19PM -0700, Ben Widawsky wrote:
> Previously the number needed to be divided by 4 to get the proper results. Now
> the hardware does the right thing. Through experimentation it seems Braswell
> (CHV) does also need this.
I need to reword this, which I'v
AFAICT the number of threads is 80, not 70. I am not sure if Ken knows
something I do not.
Signed-off-by: Ben Widawsky
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
in rows between array slices. */
> +
> + struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
> +};
> +
Doesn't the needs resolve flag belong here too?
> struct intel_mipmap_tree
> {
> /** Buffer object containing the pixel data. */
> @@ -362,15 +3
just for
the pedant:
brw_emit_depth_stencil_hiz()
gen6_blorp_emit_depth_stencil_config()
gen6_emit_depth_stencil_hiz()
If it was intentional, maybe adjust the commit message?
I see nothing that would break as a result here though.
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Center
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bo,
>I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> - OUT_BATCH(depth_mt->hiz_buf->mt->qpitch >> 2);
> + OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
>ADVANCE_BATCH();
> }
>
> --
I would have just combined
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