From: Ben Widawsky
This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.
Primarily this patch is split out for review, it can be squashed in
later if preferred.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
From: Ben Widawsky
Modifiers will be obtains or guessed by the client and passed in during
image creation/import.
This requires bumping the DRIimage version.
Signed-off-by: Ben Widawsky
---
include/GL/internal/dri_interface.h | 28 +++-
src/gallium/state_trackers
From: Ben Widawsky
The idea behind modifiers like this is that the user of GBM will have
some mechanism to query what properties the hardware supports for its BO
or surface. This information is directly passed in (and stored) so that
the DRI implementation can create an image with the
From: Ben Widawsky
This will be used by clients that need to know the number of planes
allocated for them on behalf of the GL or other API. The best current
example of this is when an extra "plane" is allocated to store
compression data for the primary plane.
Cc: Daniel Stone
Sig
From: Ben Widawsky
v2: Use stored modifiers from create instead of queryImage
Discussion with Kristian yielded that there is no need for per plane
modifiers.
Signed-off-by: Ben Widawsky
---
src/gbm/backends/dri/gbm_dri.c | 32
src/gbm/gbm-symbols
From: Ben Widawsky
This patch series ultimately adds support within the i965 driver for
Renderbuffer Decompression with GBM. In short, this feature reduces memory
bandwidth by allowing the GPU to work with losslessly compressed data and having
that compression scheme understood by the display
From: Ben Widawsky
This provides a common function or creating miptrees when there is an
existing DRIimage to use. That provides an easy way to add CCS
allocation.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_fbo.c | 17 -
src/mesa/drivers/dri/i965
From: Ben Widawsky
Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).
This is a bit ugly, but I think it's the best one can do.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/gbm/main/gbm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gbm/main/gbm.h b/src/gbm/main/gbm.h
index 59daaa1..efb329e 100644
--- a/src/gbm/main/gbm.h
+++ b/src/gbm/main/gbm.h
@@ -294,10 +294,10 @@ gbm_bo_map
From: Ben Widawsky
This will be used so we can query information per plane.
Signed-off-by: Ben Widawsky
---
src/gbm/backends/dri/gbm_dri.c | 7 +++
src/gbm/main/gbm.c | 2 +-
src/gbm/main/gbmint.h | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a
From: Ben Widawsky
In the foreseeable future it doesn't seem to make sense to have multiple
resolve flags. What does make sense is to have the caller give an
indication to the lower layers what it things should be done for
resolve. The enum change distinguishes this binary selection.
Signe
From: Ben Widawsky
Cc: Topi Pohjolainen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++-
src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa
From: Ben Widawsky
Upper layers of the code will have the need to specify full or partial
resolves (more on this in the next patch). This code simply adds the new
enums and plumbs it in as minimally as necessary.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_blorp.c
From: Ben Widawsky
Since the code doesn't support modifiers yet, this patch should do
nothing other than prepare for more patches.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 73 ++--
1 file changed, 60 insertions(+), 13 dele
From: Ben Widawsky
Cc: Ville Syrjälä
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 37
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 0f19a6e
From: Ben Widawsky
commit 6a0d036483caf87d43ebe2edd1905873446c9589
Author: Ben Widawsky
Date: Thu Apr 21 20:14:58 2016 -0700
i965: Always use Y-tiled buffers on SKL+
Aside from the benchmark gains that were initially posted, I was able to
collect memory bandwidth data running kmscube
From: Ben Widawsky
On Gen9 hardware, the display engine is able to scanout a compressed
framebuffer by providing an offset to auxiliary compression information.
Unfortunately, the hardware is incapable of doing the same thing for the
fast clear color.
To mitigate this, the hardware introduced a
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/gbm/backends/dri/gbm_dri.c | 26 +-
src/gbm/gbm-symbols-check | 1 +
src/gbm/main/gbm.c | 15 ++-
src/gbm/main/gbm.h | 3 +++
4 files changed, 43 insertions(+), 2 deletions
From: Ben Widawsky
There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.c | 14 --
src/mesa/drivers
From: Ben Widawsky
FINISHME: Use the kernel's final choice for the fb modifier
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $)
~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
Write bandwidth: 615.28 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modi
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 91eb7ec..f40761a
From: Ben Widawsky
This doesn't actually enable Y-tiling, it simply parses it and moves on.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_image.h | 1 +
src/mesa/drivers/dri/i965/intel_screen.c | 36 +---
2 files changed, 29 insertions(
On 16-12-01 14:41:20, Kenneth Graunke wrote:
On Thursday, December 1, 2016 2:09:55 PM PST Ben Widawsky wrote:
From: Ben Widawsky
Previously our aux buffers (MCS, and HiZ) never had an offset because
they were in their own buffer object. When using the CCS lossless
compression feature, it&#
On 16-12-02 18:07:22, Daniel Stone wrote:
Hi,
On 2 December 2016 at 17:56, Eric Engestrom wrote:
On Thursday, 2016-12-01 14:09:43 -0800, Ben Widawsky wrote:
--- a/src/gbm/main/gbm.h
+++ b/src/gbm/main/gbm.h
@@ -294,10 +294,10 @@ gbm_bo_map(struct gbm_bo *bo,
void
gbm_bo_unmap(struct gbm_bo
using blorp. Blorp doesn't trash
global gl state but only the internal driver state.
Signed-off-by: Topi Pohjolainen
CC: Kenneth Graunke
CC: Jason Ekstrand
CC: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_compute.c | 1 +
src/mesa/drivers/dri/i965/brw_context.c | 4
src/mesa/drivers/dri
t;gen].rb_mocs,
> false,
> + surface_state_infos[brw->gen].tex_mocs,
> false,
> surf_offset, surf_index,
> I915_GEM_DOMAIN_SAMPLER,
> access == GL_READ_ONLY ?
AFAICT, it's never been used.
It was briefly nudged in the right direction here:
commit 10e5ffd4961055ebba5be4d85a93cc66cdd5a635
Author: Emil Velikov
Date: Sat Jan 25 17:19:10 2014 +
gbm: do not export _gbm_mesa_get_device
Cc: Kristian Høgsberg
Cc: Emil Velikov
Signed-off-by
Missed here:
commit a43d286ef7ff65087b1f051d071b829ca7b02073
Author: Kristian Høgsberg
Date: Fri Mar 28 10:17:11 2014 -0700
gbm: Add import from fd
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/gbm/main/gbm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Thu, Sep 26, 2013 at 01:28:47PM -0700, Chad Versace wrote:
> On 09/22/2013 10:37 AM, Ben Widawsky wrote:
> >After the last patch, we can replace the region allocated in the miptree
> >creation with a more straightforward (and hopefully smaller resulting)
> >buffer
gion. This allows an upcoming
patch to simply allocate the region, and not the whole miptree.
v2: Don't use intel_region. Instead use bo + stride. We actually do
store the stride in libdrm, but it is inaccessible in the current
libdrm version.
CC: Chad Versace
Signed-off-by: Ben Widawsky
62e+08 42099587
CC: Chad Versace
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 194 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
2 files changed, 176 insertions(+),
tps://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 161 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
2 files changed, 143 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drive
On Mon, Sep 30, 2013 at 07:24:08PM -0700, Ian Romanick wrote:
> On 09/30/2013 12:35 PM, Ben Widawsky wrote:
> > Starting with Ivybridge, the hierarchical had relaxed requirements for
> > its allocation. Following a "simple" formula in the bspec was all you
> > ne
On Mon, Sep 30, 2013 at 07:22:54PM -0700, Ian Romanick wrote:
> On 09/30/2013 05:45 PM, Ben Widawsky wrote:
> > After the last patch, we can replace the region allocated in the miptree
> > creation with a more straightforward (and hopefully smaller resulting)
> > buffer
On Tue, Oct 01, 2013 at 01:06:02PM -0700, Chad Versace wrote:
> On 09/30/2013 12:35 PM, Ben Widawsky wrote:
> >Starting with Ivybridge, the hierarchical had relaxed requirements for
> >its allocation. Following a "simple" formula in the bspec was all you
> >ne
On Tue, Oct 01, 2013 at 03:46:14PM -0700, Matt Turner wrote:
> On Mon, Sep 30, 2013 at 12:35 PM, Ben Widawsky
> wrote:
> > Starting with Ivybridge, the hierarchical had relaxed requirements for
> > its allocation.
>
> This reads badly. How about
>
> The HiZ buffer&
On Tue, Oct 01, 2013 at 01:06:02PM -0700, Chad Versace wrote:
> On 09/30/2013 12:35 PM, Ben Widawsky wrote:
> >Starting with Ivybridge, the hierarchical had relaxed requirements for
> >its allocation. Following a "simple" formula in the bspec was all you
> >ne
Width and Height to the slice's
> logical dimensions. We should do the same for 3DSTATE_DEPTH_BUFFER,
> because the hw docs say so.
>
> No Piglit regressions (-x glx) on Ivybridge with Wayland.
>
> CC: Paul Berry
> CC: Jordan Justen
> CC: Ben Widawsky
> Signed-
say so.
> >>
> >> No Piglit regressions (-x glx) on Ivybridge with Wayland.
>
> HSW too?
>
My tested-by was on HSW.
> >> CC: Paul Berry
> >> CC: Jordan Justen
> >> CC: Ben Widawsky
> >> Signed-off-by: Chad Versace
> >&
er.stride instead of hiz_region.pitch
Kill temporary depth_mt variable.
memset the temporary region variable (Chad)
CC: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_misc_state.c| 11 +---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 21 ++--
ad)
Use mt->logical_depth0 instead of mt->level[i].depth (Chad)
Kill TODO about compressed depth textures (Chad)
Use target_to_target (Chad)
Add missing GL_TEXTURE_1D, and GL_TEXTURE_CUBE_MAP cases
Remove X tiled fallback (Chad)
CC: Chad Versace
Bugzilla: https://bugs.freedesktop.org/sho
ation is actually a
lot more complicated than this, but this is sufficient. It would seem
though that this covers all cases. (Also, you don't need it for a
resolve AFAICT, only a clear).
Reviewed-by: Ben Widawsky
> +static void
> +align_rectangle_primitive(uint32_t *width,
sults confirmed. Excellent work, Ken!
Tested-by: Ben Widawsky
--
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lize I do not quite see even all the
gen7 restrictions, so I am not qualified to determine if you accounted
for gen8.
In particular, stride of src, and dest must be the same, and
"Regioning must ensure Src.Vstride = Src.Width * Src.Hstride"
The rest of the series is:
Reviewed-by: Ben Widaw
Just to verify the code does what we want...
---
src/mesa/drivers/dri/i965/gen8_viewport_state.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_viewport_state.c
b/src/mesa/drivers/dri/i965/gen8_viewport_state.c
index 2bf5fbb..cfbcb12 100644
--- a/src/mesa/d
Viewport extents are a 3rd rectangle that defines which pixels get
discarded as part of the rasterization process. This can potentially
improve performance by reducing cache usage, and freeing up PS cycles.
This will get hit if one's viewport is smaller than the full
renderbuffer, and scissoring is
Reviewed-by: Ben Widawsky
On Thu, Jul 03, 2014 at 02:47:14PM -0700, Kenneth Graunke wrote:
> Originally, we didn't have direct accessors for all of the GLSL types,
> so the only way to get at them was to use the symbol table. Now, we
> can just get at them directly, which is simp
On Thu, Jul 24, 2014 at 10:29:11AM +0300, Pohjolainen, Topi wrote:
> On Thu, Jul 03, 2014 at 11:23:13AM -0700, Ben Widawsky wrote:
> > Viewport extents are a 3rd rectangle that defines which pixels get
> > discarded as part of the rasterization process. This can potentially
> >
Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
> Cc: Jason Ekstrand
> Cc: "10.2"
I was hoping I would have a chance to fix this one :-(
Tested-by: Ben Widawsky
> ---
> On a gen6 piglit quick run:
> 15: crash => pass
> 1: crash => fai
patch 7. I always go back and forth on whether to combine these
things. And given the amount of churn in the HW between gen7, and gen8,
I am a bit hesitant. What was the reason Ken dropped that one?
I didn't spot anything obviously wrong in any of the patches.
Run the piglits I say
--
Ben
gion. This allows an upcoming
patch to simply allocate the region, and not the whole miptree.
CC: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_misc_state.c| 8 +++---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp
otivation.
CC: Chad Versace
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 149 +++---
1 file changed, 133 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/int
motivation.
v2: copy-paste fix where I used I915_TILING_Y where I meant _Y. (Topi)
CC: Chad Versace
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 149 +++---
1 file changed, 133 insertio
On Thu, Sep 26, 2013 at 11:16:52AM -0700, Chad Versace wrote:
> On 09/26/2013 10:37 AM, Chad Versace wrote:
> >On 09/22/2013 10:37 AM, Ben Widawsky wrote:
> >>Starting with Ivybridge, the hierarchical had relaxed requirements for
> >
context idea is valid. Needs mesa
eyes.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
configure.ac| 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 9 -
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index
; Reviewed-by: Eric Anholt
>
> Maybe some day we'll do a symbol-versioned fork of the code without all
> the compatibility insanity, and with other 4G limits fixed. I don't
> think we have any instances of sharing drm_intel_bos across build-system
> boundaries. Anyone wan
ion
> ordering.
>
> This may fix hangs on Gen6+ when using the media pipeline.
>
> Cc: "10.0 10.1"
> Cc: Ben Widawsky
> Signed-off-by: Kenneth Graunke
Doesn't this potentially fix issues going back further than g
Or should I hack the
kernel?
Yang Rong
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- End forwarded message -
--
Ben Widawsky, Intel Open Source Technology Center
On Fri, Jul 12, 2013 at 07:16:37PM +0200, Daniel Vetter wrote:
> On Fri, Jul 12, 2013 at 7:12 PM, Ben Widawsky
> wrote:
> > FWD'd from our internal list now that we have more insight.
> > - Forwarded message from Ben Widawsky
> > -
> >
> > Date:
On Fri, Jul 12, 2013 at 10:12:39AM -0700, Ben Widawsky wrote:
> FWD'd from our internal list now that we have more insight.
> - Forwarded message from Ben Widawsky -
>
> Date: Thu, 11 Jul 2013 10:32:03 -0700
> From: Ben Widawsky
> To: linux-...@linux.intel.com
&
FWD'd from our internal list now that we have more insight.
- Forwarded message from Ben Widawsky -
Date: Thu, 11 Jul 2013 10:32:03 -0700
From: Ben Widawsky
To: linux-...@linux.intel.com
Subject: intel_gpu_top broken for HSW. Ideas needed
Message-ID: <20130711173202.gb8...@i
On Thu, Jan 02, 2014 at 07:50:35PM -1000, Ben Widawsky wrote:
> Will full PPGTT support it can be assumed that every file descriptor
> gets its own hardware context. As such, there is no need to allocate
> anew context in order to use the features provided by hardware contexts.
> Elim
An easy one :D
Reviewed-by: Ben Widawsky
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On Mon, Dec 01, 2014 at 05:37:27PM -0800, Eric Anholt wrote:
> Neil Roberts writes:
>
> > When submitting the vertex buffers the i965 driver will try to recognise
> > when
> > multiple attributes are using the same buffer so that it can submit a single
> > relocation for it and set a different o
gt; valid.
Given that a half byte (apparently this part of the docs aren't fond of the word
nibble) isn't a real datatype, I doubt 32 will ever be valid.
>
> [1] http://damien.lespiau.name/intel/gen_regions.html
>
> With that removed (or justified),
On Tue, Dec 02, 2014 at 04:17:35PM +, Neil Roberts wrote:
> Ok, I've written a somewhat contrived test case here:
>
> https://github.com/bpeel/glthing/tree/time-attribs
>
> (Make sure to use the time-attribs branch)
>
> The example draws a 1000 single-pixel points each with a separate draw
>
o a new XML doc instead of using the main GL4x.xml (Ilia)
- Add a fallthrough comment (Ilia)
- Only divide PS invocations by 4 on HSW+ (Ben)
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
---
.../glapi/gen/ARB_pipeline_statistics_query.xml| 24
src/mesa/drivers/dri/i965/gen6_queryob
On Tue, Dec 02, 2014 at 10:47:37PM -0500, Ilia Mirkin wrote:
> On Tue, Dec 2, 2014 at 9:33 PM, Ben Widawsky
> wrote:
> > This patch implements ARB_pipeline_statistics_query. This addition to GL
> > does
> > not add a new API. Instead, it adds new tokens to the exist
SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide by 2
thing.
Only compile test.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_gs_state.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions
On Wed, Dec 03, 2014 at 04:47:18PM -0800, Matt Turner wrote:
> ---
> The number of times I've wondered why piglit/gbm wasn't working...
>
> src/egl/drivers/dri2/egl_dri2.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
>
On Wed, Dec 03, 2014 at 11:27:55PM -0800, Ben Widawsky wrote:
> On Wed, Dec 03, 2014 at 04:47:18PM -0800, Matt Turner wrote:
> > ---
> > The number of times I've wondered why piglit/gbm wasn't working...
> >
> > src/egl/drivers/dri2/egl_dri2.c |
piglit tests on BSW.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes)
Cc: "10.4"
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 5 -
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 3 ++-
2 files changed, 6 inser
On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
> On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
> wrote:
> > The GS has an interesting use for mul. It's essentially used as a fancy mov
> > (in
> > fact, I am not sure why a mov isn't used). The docu
On Thu, Dec 04, 2014 at 05:17:05PM -0800, Kenneth Graunke wrote:
> On Thursday, December 04, 2014 03:37:17 PM Ben Widawsky wrote:
> > The GS has an interesting use for mul. It's essentially used as a fancy mov
> > (in
> > fact, I am not sure why a mov isn't
On Thu, Dec 04, 2014 at 07:48:06PM -0800, Ben Widawsky wrote:
> On Thu, Dec 04, 2014 at 05:08:21PM -0800, Matt Turner wrote:
> > On Thu, Dec 4, 2014 at 3:37 PM, Ben Widawsky
> > wrote:
> > > The GS has an interesting use for mul. It's essentially used as a fancy
&
On Thu, Dec 04, 2014 at 10:02:24PM -0800, Kristian Høgsberg wrote:
> fs_generator no longer knows what stage it's generating code for, so
> we have to set the debug name of the shader from the call site.
>
> Signed-off-by: Kristian Høgsberg
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
On Fri, Dec 05, 2014 at 01:36:52PM -0800, Matt Turner wrote:
> On Fri, Dec 5, 2014 at 1:34 PM, Ben Widawsky wrote:
> > I do wonder the original motivation for the debug_flag member. Seems totally
> > superfluous.
>
> Because brw_fs_generator is used by the fs and b
(1 << 26)
> #define DEBUG_OPTIMIZER (1 << 27)
> -#define DEBUG_NO_ANNOTATION (1 << 28)
> +#define DEBUG_ANNOTATION (1 << 28)
> #define DEBUG_NO8 (1 << 29)
>
> #ifdef HAVE_ANDROID_PLATFORM
I never had an opinion, but I completely agree. With or without my suggestion
above:
Reviewed-by: Ben Widawsky
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also don't really see the need to have 2-4 as separate patches, but as you
like).
1-4:
Reviewed-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs.cpp| 2 +-
> src/mesa/drivers/dri/i965/brw_fs.h
On Fri, Dec 05, 2014 at 06:56:27PM -0800, Matt Turner wrote:
> On Fri, Dec 5, 2014 at 6:18 PM, Vinson Lee wrote:
> > This patch fixes this build error with GCC <= 4.6.
> >
> > CXXtest_vf_float_conversions.o
> > test_vf_float_conversions.cpp: In function ‘unsigned int f2u(float)’:
> > test_vf
On Fri, Dec 05, 2014 at 08:57:27PM -0800, Ian Romanick wrote:
> On 12/05/2014 05:23 PM, Ben Widawsky wrote:
> > On Fri, Dec 05, 2014 at 05:08:40PM -0800, Matt Turner wrote:
> >> ---
> >> Eric was against making this the default when I first suggested a flag.
> >&
On Tue, Dec 02, 2014 at 11:07:34PM -0800, Ian Romanick wrote:
> Since there will be a v3 anyway, nits below...
>
> On 12/02/2014 06:33 PM, Ben Widawsky wrote:
> > This patch implements ARB_pipeline_statistics_query. This addition to GL
> > does
> > not add a new API.
makes the workaround more understandable, and more future-proof.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
ind
Let's assume that this IVB specific feature exists on BYT too, since it's very
much like IVB
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tre
As far as I can tell, this restriction is always needed.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index efe63b5..25bf37b 10064
bpp formats on Sandybridge.
The above commit has a mailing list discussion about this where Ken said the
issue was reintroduced on later GENs. I can't find the evidence to support this
anymore, so let's turn it on and hope for the best.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
On Tue, Dec 09, 2014 at 04:14:14PM -0800, Matt Turner wrote:
> On Tue, Dec 9, 2014 at 4:02 PM, Ben Widawsky
> wrote:
> > Let's assume that this IVB specific feature exists on BYT too, since it's
> > very
> > much like IVB
>
> To clarify, the featu
On Tue, Dec 09, 2014 at 04:03:00PM -0800, Ben Widawsky wrote:
> Quoting the workaround already there:
> "This field must be set to VALIGN_4 for all tiled Y Render Target surfaces."
>
> This patch simply asserts we return Y tiled, instead of X or Y. It has no
> effect
>
The odds of having this patch make a difference on Gen8+ are probably very low.
Only compile tested.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b
We support MOCS on both gen8 and gen9, so the message seems meaningless. Remove
it to avoid confusion.
Trivial.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_misc_state.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
be you can take a look and make sure as
well.
Also, I notice an extraneous flush in this path, but I think you address it in a
later patch.
Assuming that's verified (and perhaps commit message updated to explain), this
is
Reviewed-by: Ben Widawsky
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->bo)) {
> - perf_debug("Stalling on the GPU waiting for a query object.\n");
> - }
> - }
> -
> - drm_intel_bo_map(query->bo, false);
> + brw_bo_map(brw, query->bo, false, "query object");
> uint64_t *results = query->bo-&
void gen6_check_query(struct gl_context *ctx,
> struct gl_query_object *q)
> * not ready yet on the first time it is queried. This ensures that
> * the async query will return true in finite time.
> */
> - if (drm_intel_bo_references(brw->batch.b
On Mon, Dec 15, 2014 at 01:28:52PM -0800, Ian Romanick wrote:
> On 12/14/2014 04:39 PM, Ben Widawsky wrote:
> > On Fri, Dec 12, 2014 at 11:15:42PM -0800, Kenneth Graunke wrote:
> >> Chris Wilson noted that repeated calls to CheckQuery() would call
> >> drm_intel_bo_refe
oot yourself in the foot if you change the module parameter in
a running system, and then it's
Reviewed-by: Ben Widawsky
>
> Checking introduces a synchronization point between the CPU and GPU:
> even though we submit very few GPU commands, the GPU might be busy doing
> other
20 new failures that match other
generations), I see no change. I am however optimistic that the series will
prevent future failures.
(BDW does add 1 new pass, but I am not sure if it's real):
spec/ARB_texture_multisample/texelFetch fs sampler2DMSArray 4
98x1x9-98x129x9:fail pass
Ben Widaws
As it turns out, I have other uses for this tiny convenience function. Simple
extraction for use by others. Matt was right for not liking the macro in the
initial patch.
While doing this, add it to a few easy to spot users of this functionality.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers
ll minimize the impact on GEN8 as
well.
Cc: Kenneth Graunke
Cc: Matt Turner
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw
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