FWDing to mesa-dev, since they should have the same issue. ----- Forwarded message from "Yang, Rong R" <rong.r.y...@intel.com> -----
Date: Tue, 6 May 2014 08:26:15 +0000 From: "Yang, Rong R" <rong.r.y...@intel.com> To: "intel-...@lists.freedesktop.org" <intel-...@lists.freedesktop.org> Subject: [Intel-gfx] How user space applications load registers on HSW? Message-ID: <7597c9376c272a4ab2d29e91550b7b0901354...@shsmsx102.ccr.corp.intel.com> Hi, I am developing the HSW’s OCL driver in the linux. I encounter a LRI problem on HSW. Some gpgpu's applications, which use the shared local memory, must load the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in the L3 cache. So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_regs to pass the cmds parse when exec buffer. But it still don’t work. I notice that, on HSW, the commands that load the register, such as MI_LOAD_REGISTER_IMM, will be converted to NOOP by the GPU if the batch buffer's MI_BATCH_NON_SECURE_HSW bit is set. And after parse cmd, the MI_BATCH_NON_SECURE_HSW still set in the kernel. So HSW don’t accept LRI commands. Can I load these registers in the user space? Or should I hack the kernel? Yang Rong _______________________________________________ Intel-gfx mailing list intel-...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ----- End forwarded message ----- -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
