Always false.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 2 --
src/amd/vulkan/radv_nir_to_llvm.c | 15 ++-
src/amd/vulkan/radv_shader.h | 1 -
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd
Instead of using this useless array_params_mask variable.
This should set these two attributes to streamout buffers too.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/r
Unnecesary to check the current stages if desc_set_used_mask
is used.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 102 ++
1 file changed, 34 insertions(+), 68 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/rad
On Thu, 2019-01-24 at 11:45 -0800, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Wed, 2019-01-23 at 06:03 -0800, Francisco Jerez wrote:
> > > Iago Toral Quiroga writes:
> > >
> > > > Commit c84ec70b3a72 implemented execution type promotion to 32-
> > > > bit
> > > > for
> > > > conversio
On Thu, 2019-01-24 at 10:22 -0800, Matt Turner wrote:
> On Wed, Jan 23, 2019 at 4:18 AM Iago Toral Quiroga > wrote:
> >
> > Commit c84ec70b3a72 implemented execution type promotion to 32-bit
> > for
> > conversions involving half-float registers, which empirical testing
> > suggested
> > was requ
On Thu, 2019-01-24 at 12:16 -0800, Francisco Jerez wrote:
> Matt Turner writes:
>
> > ---
> > src/intel/compiler/brw_eu_validate.c | 14 +-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/compiler/brw_eu_validate.c
> > b/src/intel/compiler/brw_eu_v
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jan 23, 2019 at 10:26 AM Samuel Pitoiset
wrote:
>
> Streamout buffers are emitted like push constants.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_nir_to_llvm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/amd/vulkan/
The musl libc library does not have any support for the
"initial-exec" TLS model and is unlikely to ever implement it.
Thus, TLS support in GLX has been turned off in musl-based
distributions to work around problems when dlopen'ing drivers.
While this is easily possible using the autoconf build sys
Am Donnerstag, den 24.01.2019, 22:25 -0800 schrieb Stéphane Marchesin:
>
> Yes, it's for running virgl on top of GLES. To emulate fp64 in GL on
> the guest side, we need fp64 on the host...
BTW: we could also get it emulated from the guest side. When Elie (in
CC) initially proposed the fp64 emul
Acked-by: Jose Maria Casanova Crespo
Matt, I'll include in my TODO list creating tests for sends using grf127
as destination restriction and the one about byte_raw_moves and
execution size and stride once I receive your feedback.
Chema
El 24/1/19 a las 20:53, Matt Turner escribió:
> ---
> src/
https://bugs.freedesktop.org/show_bug.cgi?id=109183
--- Comment #3 from Alexander ---
I can't confirm that it's mesa who is doing this and can only provide spongy
info about it, but this only happens in online mode and just anyway proton has
a hard time with the online mode.
--
You are receivin
Build mesa 9849 failed
Commit 540939ecee by Tapani Pälli on 1/25/2019 7:51 AM:
android: fix build issues with libmesa_anv_gen* libraries\n\nWe need this include path to find nir/nir_xfb_info.h.\n\nSigned-off-by: Tapani Pälli \nReviewed-by: Eric Engestrom
On Thu, Jan 24, 2019 at 7:21 PM Eric Anholt wrote:
>
> Rob Herring writes:
>
> > Enable using etnaviv for KMS renderonly. This still needs KMS driver
> > name mapping to kmsro to be used automatically.
> >
> > Signed-off-by: Rob Herring
>
> > diff --git a/src/gallium/winsys/kmsro/drm/kmsro_drm_w
I just noticed these patches, because Appveyor build is broken, and to
my surprise, on Cygwin.
There are several problems with these patches:
- First of all, there were commited with no reviewed by. Not by me (a
quick `git log appveyor.yml` would tell you I pretty much wrote and
maitain it).
Build mesa 9850 completed
Commit 65b8d723fd by Jose Fonseca on 1/25/2019 2:07 PM:
appveyor: Revert commits adding Cygwin support.\n\nThis reverts commits 00ad77b9f683e561b1ac45fbb89eb2bafe45c8c6 and\n5334dafee265d78abdfcf30e2c693e0791bfecf5.\n\nThis avoids Appv
ir3 compiler has an integer multiply-add instruction (IMAD_S24)
that is used for different offset calculations in the backend.
Since we intend to move some of these calculations to NIR, we need
a new ALU op that can represent it.
---
src/compiler/nir/nir_opcodes.py | 1 +
1 file changed, 1 inserti
This pass moves to NIR some offset calculations that are currently
implemented on the backend compiler, to allow NIR to possibly
optimize them.
For now, only coordinate byte-offset calculations for imageStore
and image atomic operations are implemented.
---
src/freedreno/Makefile.sources
This is an internal intrinsic intended to be injected by a
(freedreno-specific) 'lower_sampler_io' pass that will be introduced
later in this series; and consumed by ir3_compiler_nir.
The intrinsic will load in SSA values for various constants
for images (image_dims), namely the format's bytes-per
This effectively removes all offset calculations in
ir3_compiler_nir::get_image_offset().
No regressions observed on affected tests from Khronos CTS and piglit
suites, compared to master.
Collecting useful stats on helps/hurts caused by this pass is WIP. Very
few shaders in shader-db data-base ex
There are a bunch of instructions emitted on ir3_compiler_nir related to
offset computations for IO opcodes (ssbo, image, etc). This small series
explores the possibility of moving these instructions to NIR, where we
have higher chances of optimizing them.
The series introduces a new, freedreno sp
IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
had this, and I think maxwell+ has a variant of this implemented by
XMAD):
(src0 * src1) & 0xff + src2
Cheers,
-ilia
On Fri, Jan 25, 2019 at 10:49
On Fri, Jan 25, 2019 at 10:58 AM Ilia Mirkin wrote:
>
> IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
> imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
> had this, and I think maxwell+ has a variant of this implemented by
> XMAD):
>
> (src0 * src1) &
Hi Christian,
Am Montag, den 21.01.2019, 07:50 +0100 schrieb Christian Gmeiner:
> If the GPU supports linear sampling, linear addressing mode
> will be used as default.
>
> > Signed-off-by: Christian Gmeiner
> ---
> src/gallium/drivers/etnaviv/etnaviv_resource.c | 10 +++---
> src/gallium/d
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.h | 1 +
src/amd/vulkan/radv_shader_info.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 0f049f9a528..09bc5c2d4a9 100644
--- a/src/amd/vulkan/radv_shader.h
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b655e2c2e2c..11417c5991b 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/ra
This is needed in order to inline some push constants when possible.
This also adds a new helper for initializing the pass.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 ++
src/amd/vulkan/radv_private.h | 2 ++
src/amd/vulkan/radv_shader.h | 4
src/am
This removes some scalar loads from shaders, but it increases
the number of SET_SH_REG packets. This is currently basic but
it could be improved if needed. Inlining dynamic offsets might
also help.
Original idea from Dave Airlie.
29164 shaders in 15096 tests
Totals:
SGPRS: 1336072 -> 1365241 (2.1
From: Emil Velikov
Earlier commit aimed to remove unneeded function declarations. Namely
OpenGL entrypoints which are not applicable for OpenGLES*
Although it did not consider the shared glapi which needs all,
including hidden ones. Resulting in warning/errors like the following
../build/src/ma
When stitching two blocks A and B, where A's last instruction is a jump,
it is not required that B is empty; it can be plainly removed.
This can happen in a situation like this:
vec1 1 ssa_1 = load_const (true)
vec1 1 ssa_2 = load_const (false)
block block_1:
[...]
loop {
vec1 ssa_3 = phi block
Eduardo Lima Mitev writes:
> This is an internal intrinsic intended to be injected by a
> (freedreno-specific) 'lower_sampler_io' pass that will be introduced
> later in this series; and consumed by ir3_compiler_nir.
>
> The intrinsic will load in SSA values for various constants
> for images (im
Eduardo Lima Mitev writes:
> ir3 compiler has an integer multiply-add instruction (IMAD_S24)
> that is used for different offset calculations in the backend.
> Since we intend to move some of these calculations to NIR, we need
> a new ALU op that can represent it.
> ---
> src/compiler/nir/nir_op
On Fri, Oct 12, 2018 at 01:46:32PM -0500, Jason Ekstrand wrote:
> Reviewed-by: Topi Pohjolainen
> ---
> src/intel/blorp/blorp_clear.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
Patches 1 and 2 are:
Reviewed-by: Nanley Chery
> diff --git a/src/intel/blorp/blorp_clear.c
On Fri, Jan 25, 2019 at 2:25 AM Gert Wollny wrote:
>
> Am Donnerstag, den 24.01.2019, 22:25 -0800 schrieb Stéphane Marchesin:
> >
> > Yes, it's for running virgl on top of GLES. To emulate fp64 in GL on
> > the guest side, we need fp64 on the host...
>
> BTW: we could also get it emulated from the
On Fri, Jan 25, 2019 at 1:53 PM Stéphane Marchesin <
stephane.marche...@gmail.com> wrote:
> On Fri, Jan 25, 2019 at 2:25 AM Gert Wollny wrote:
> >
> > Am Donnerstag, den 24.01.2019, 22:25 -0800 schrieb Stéphane Marchesin:
> > >
> > > Yes, it's for running virgl on top of GLES. To emulate fp64 in
Compilation of user-specified shaders with software fp64 works by
compiling on demand an "fp64-funcs" shader implementing various fp64
operations and then linking it into the "user shader".
In
commit 64b8c86d37ebb1e1d286c69d642d52b7bcf051d3
Author: Timothy Arceri
Date: Thu Jan 17 17:1
Iago Toral writes:
> On Thu, 2019-01-24 at 11:45 -0800, Francisco Jerez wrote:
>> Iago Toral writes:
>>
>> > On Wed, 2019-01-23 at 06:03 -0800, Francisco Jerez wrote:
>> > > Iago Toral Quiroga writes:
>> > >
>> > > > Commit c84ec70b3a72 implemented execution type promotion to 32-
>> > > > bit
Emil Velikov writes:
> From: Emil Velikov
>
> Earlier commit aimed to remove unneeded function declarations. Namely
> OpenGL entrypoints which are not applicable for OpenGLES*
>
> Although it did not consider the shared glapi which needs all,
> including hidden ones. Resulting in warning/errors
Patrick Steinhardt writes:
> The musl libc library does not have any support for the
> "initial-exec" TLS model and is unlikely to ever implement it.
> Thus, TLS support in GLX has been turned off in musl-based
> distributions to work around problems when dlopen'ing drivers.
> While this is easil
Rob Clark writes:
> I guess as discovered with
> https://gitlab.freedesktop.org/mesa/mesa/merge_requests/47 maybe we
> should wait to turn on merging MRs via web until we have at least some
> basic build-test CI wired up.. the downside is slower 'maintainer'
> response (if I am working on some lo
Nick Kreeger writes:
> The OES_texture* extensions for float and half-float are valid when
> GLES2 is present w/ the matching
> OES_texture_float/OES_texture_half_float extensions. This fix ensures
> that these formats are valid for this configuration.
I don't see OES_texture_float.txt specifyin
There are piles of fields that it doesn't check so using it is a lie.
The only reason why it's not causing problem is because it has exactly
one user which only uses it for MOV instructions (which aren't very
interesting) and only on Sandy Bridge and earlier hardware. Just get
rid of it and inline
There are piles of fields that it doesn't check so using it is a lie.
The only reason why it's not causing problem is because it has exactly
one user which only uses it for MOV instructions (which aren't very
interesting) and only on Sandy Bridge and earlier hardware. Just get
rid of it and inline
From: Marek Olšák
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 34e2a032548..7f16c3070fe 100644
--- a/meson.build
+++ b/meson.build
@@ -1389,21 +1389,21
On Fri, Jan 25, 2019 at 4:26 PM Eric Anholt wrote:
>
> Rob Clark writes:
>
> > I guess as discovered with
> > https://gitlab.freedesktop.org/mesa/mesa/merge_requests/47 maybe we
> > should wait to turn on merging MRs via web until we have at least some
> > basic build-test CI wired up.. the downs
On Fri, Jan 25, 2019 at 10:48 AM Eduardo Lima Mitev wrote:
>
> There are a bunch of instructions emitted on ir3_compiler_nir related to
> offset computations for IO opcodes (ssbo, image, etc). This small series
> explores the possibility of moving these instructions to NIR, where we
> have higher
Timothy, can you please test the attached fix?
Thanks,
Marek
On Wed, Jan 2, 2019 at 10:58 PM Timothy Arceri
wrote:
> This commit seems to cause bad stuttering in the Batman Arkham City
> benchmark.
>
> On 7/12/18 1:00 am, Nicolai Hähnle wrote:
> > From: Nicolai Hähnle
> >
> > This is a move to
From: Marek Olšák
Fixes: e0f0d3675d4 "radeonsi: factor si_query_buffer logic out of si_query_hw"
---
src/gallium/drivers/radeonsi/si_query.c | 20
src/gallium/drivers/radeonsi/si_query.h | 1 +
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/gallium/driv
Reviewed-by: Marek Olšák
Marek
On Tue, Jan 22, 2019 at 10:59 PM Timothy Arceri
wrote:
> Fixes the following piglit test on my VEGA and matches the behaviour in the
> tgsi backend.
>
>
> tests/spec/glsl-1.10/execution/samplers/glsl-fs-shadow2D-clamp-z.shader_test
>
> Fixes: 625dcbbc4566 ("amd/c
Move the pln emul code to the fs_visitor, so we get some optimizations
that don't happen at the fs_generator level, mainly better scheduling.
One big caveat of this change is that we don't use NF types and the
accumulator anymore, but apparently we don't need the extra precision.
https://gitlab.f
Reviewed-by: Marek Olšák
Marek
On Wed, Jan 23, 2019 at 8:14 PM Timothy Arceri
wrote:
> The semantic was removed in e6d93893662d.
> ---
> src/gallium/docs/source/tgsi.rst | 18 --
> 1 file changed, 18 deletions(-)
>
> diff --git a/src/gallium/docs/source/tgsi.rst
> b/src/galliu
From: Marek Olšák
Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into
si_perfcounter.c"
---
src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
b/src/gallium/drivers/radeon
Thanks Rob, I'm OK with this kmsro approach.
But I have to point out that this will break XServer AIGLX:
1. modesetting DDX will report the display drm driver name like meson
as DRI2 driver name
2. libglx.so used by xserver will look after meson_dri.so for dlopen
3. then dlsym __driDriverGetExte
../src/gallium/drivers/freedreno/freedreno_resource.c: In function
‘fd_resource_create_with_modifiers’:
../src/gallium/drivers/freedreno/freedreno_resource.c:884:30: error:
‘DRM_FORMAT_MOD_QCOM_COMPRESSED’ undeclared (first use in this function)
allow_ubwc = find_modifier(DRM_FORMAT_MOD_QCOM_C
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