[Mesa-dev] [PATCH v4] anv: implement VK_EXT_global_priority extension

v2: add ANV_CONTEXT_REALTIME_PRIORITY (Chris) use unreachable with unknown priority (Samuel) v3: add stubs in gem_stubs.c (Emil) use priority defines from gen_defines.h v4: cleanup, add anv_gem_set_context_param (Jason) Signed-off-by: Tapani Pälli Reviewed-by: Samuel Iglesias Gonsálvez

Re: [Mesa-dev] [PATCH] anv: fix maxResourceSize for pre-gen9

On 26/02/18 17:02, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 12:58 AM, Samuel Iglesias Gonsálvez > mailto:sigles...@igalia.com>> wrote: > > Signed-off-by: Samuel Iglesias Gonsálvez > > --- >  src/intel/vulkan/anv_formats.c | 6 +- >  1 fi

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

Quoting Kenneth Graunke (2018-02-27 00:05:46) > +static bool > +gem_supports_48b_addresses(int fd) > +{ > + struct drm_i915_gem_exec_object2 obj = { > + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, > + }; > + > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = (uintptr_

Re: [Mesa-dev] [PATCH] radv: remove device pointer from buffer.

Reviewed-by: Bas Nieuwenhuizen On Tue, Feb 27, 2018 at 5:31 AM, Dave Airlie wrote: > From: Dave Airlie > > This is never used. > > Signed-off-by: Dave Airlie > --- > src/amd/vulkan/radv_private.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/amd/vulkan/radv_private.h b/src/amd/v

Re: [Mesa-dev] [PATCH] ac/shader: fix vertex input with components.

Reviewed-by: Bas Nieuwenhuizen On Tue, Feb 27, 2018 at 3:36 AM, Dave Airlie wrote: > From: Dave Airlie > > This fixes: > dEQP-VK.glsl.440.linkage.varying.component.* > > Fixes: 1c57a6da5e3 (ac/shader: scan vertex inputs usage mask) > Signed-off-by: Dave Airlie > --- > src/amd/common/ac_shader

[Mesa-dev] [PATCH 1/2] ac: implement nir_op_ldexp

--- src/amd/common/ac_nir_to_llvm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index c25ae121e2..fc0a01ade8 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -1907,6 +1907,13 @@ st

[Mesa-dev] [PATCH 2/2] nir: add lower_ldexp to nir compiler options

--- src/broadcom/compiler/nir_to_vir.c | 1 + src/compiler/nir/nir.h | 2 ++ src/compiler/nir/nir_opt_algebraic.py | 4 ++-- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 + src/gallium/drivers/vc4/vc4_program.c | 1 + src/intel/compiler/brw_compiler.c

[Mesa-dev] [Bug 105105] Suffixless KHR_robustness functions aren't exposed in ES 3.2

https://bugs.freedesktop.org/show_bug.cgi?id=105105 Tapani Pälli changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@lis

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #8 from Samuel Pitoiset --- Wait, gun shooting is also fixed for you? Which LLVM version are you using? Because for me it's not the same issue. -- You are receiving this mail because: You are the assignee for the bug. You are the Q

Re: [Mesa-dev] [PATCH] radv: remove device pointer from buffer.

Reviewed-by: Samuel Pitoiset On 02/27/2018 05:31 AM, Dave Airlie wrote: From: Dave Airlie This is never used. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_private.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h inde

[Mesa-dev] [PATCH v3 7/7] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 + src/mesa/drivers/dri/i965/intel_tex_image.c | 16 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa

[Mesa-dev] [PATCH v3 5/7] i965: use ASTC5x5 workaround in brw_prepare_drawing()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 34f4de3..f891e91 100644 --- a/src/mesa/drivers/dri/i965/brw_draw

[Mesa-dev] [PATCH v3 4/7] i965: prevent using auxilary buffers when an astc5x5 texture is present

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 20 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +-- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b

[Mesa-dev] [PATCH v3 1/7] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Gen9 GPU's suffer from a HW bug where the GPU will hang if the GPU accesses a texture with a an auxilary buffer and an ASTC5x5 texture without having a pipeline cs stall (and texture cache flush) between such accesses. This patch creates the infrastucture to track such potenti

[Mesa-dev] [PATCH v3 0/7] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate and command stream

[Mesa-dev] [PATCH v3 2/7] i965: restore diable_aux argument to intel_miptree_prepare_texture()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 9 ++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/m

[Mesa-dev] [PATCH v3 6/7] i965: use ASTC5x5 workaround in brw_dispatch_compute_common()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_compute.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index 5ce899b..ec96687 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH v3 3/7] i965: set ASTC5x5 workaround texture type tracking on texture validate

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index eaa60ba..2bf6c65 100644

Re: [Mesa-dev] [PATCH 2/2] radeonsi/nir: disable vertex_id_zero_based lowering

On 02/27/2018 03:10 AM, Timothy Arceri wrote: The lowering is incompatable with how the radeonsi backend works. incompatible For the series: Reviewed-by: Samuel Pitoiset Fixes piglit test: ./bin/arb_shader_draw_parameters-basevertex vertexid-zerobased -auto --- src/gallium/drivers/rad

Re: [Mesa-dev] [PATCH 1/2] radeonsi: create get_base_vertex() helper

On 02/26/2018 12:29 PM, Timothy Arceri wrote: --- src/gallium/drivers/radeonsi/si_shader.c | 34 +++- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 7af0bdb

Re: [Mesa-dev] [PATCH] ac/shader: fix vertex input with components.

Reviewed-by: Samuel Pitoiset On 02/27/2018 03:36 AM, Dave Airlie wrote: From: Dave Airlie This fixes: dEQP-VK.glsl.440.linkage.varying.component.* Fixes: 1c57a6da5e3 (ac/shader: scan vertex inputs usage mask) Signed-off-by: Dave Airlie --- src/amd/common/ac_shader_info.c | 2 +- 1 file c

Re: [Mesa-dev] [PATCH 1/2] i965: Add debugging code to dump the validation list.

Quoting Kenneth Graunke (2018-02-26 23:54:59) > When anything goes wrong with this code, dumping the validation list > is a useful way to figure out what's happening. > --- > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 > 1 file changed, 20 insertions(+) > > I've now u

Re: [Mesa-dev] [PATCH 2/2] i965: Shorten the name of the workaround BO.

Quoting Kenneth Graunke (2018-02-26 23:55:00) > This makes the name shorter in debug printouts. If "workaround_bo" > is good enough for the code, it's probably good enough for debugging. brw->wa_bo and "w/a"? :) -Chris ___ mesa-dev mailing list mesa-dev

[Mesa-dev] [PATCH] meson: Add default DRI drivers for ARM/AArch64

On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as 'aarch64'), only build swrast for DRI drivers. The only classic drivers which could be used are r200 and NV20 cards, which seems unlikely enough that it shouldn't be the default. Signed-off-by: Daniel Stone Reported-by: Javier

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Mon, Feb 26, 2018 at 11:14:05AM -0800, Matt Turner wrote: > On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding > wrote: > > From: Thierry Reding > > > > The disk cache implementation uses 64-bit atomic operations. For some > > architectures, such as 32-bit ARM, GCC will not be able to translate >

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Mon, Feb 26, 2018 at 12:05:51PM -0800, Dylan Baker wrote: > Quoting Thierry Reding (2018-02-23 05:18:28) > > From: Thierry Reding > > > > The disk cache implementation uses 64-bit atomic operations. For some > > architectures, such as 32-bit ARM, GCC will not be able to translate > > these ope

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Mon, Feb 26, 2018 at 11:28:23PM +, Mike Lothian wrote: > On Fri, 23 Feb 2018 at 13:18 Thierry Reding > wrote: > > > From: Thierry Reding > > > > The disk cache implementation uses 64-bit atomic operations. For some > > architectures, such as 32-bit ARM, GCC will not be able to translate >

[Mesa-dev] [PATCH v2] anv: set maxResourceSize to the respective value for each generation

v2: - Add the proper values to gen9+ (Jason) Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_formats.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c index 9c52ad5acbd..cbc3d3579

Re: [Mesa-dev] [PATCH v2 2/9] intel/blorp: Add indirect clear color support to mcs_partial_resolve

Acked-by: Samuel Iglesias Gonsálvez Sam On 24/02/18 07:22, Jason Ekstrand wrote: > This is a bit complicated because we have to get the indirect clear > color in there somehow. In order to not do any more work in the shader > than needed, we set it up as it's own vertex binding which points > d

Re: [Mesa-dev] [PATCH] glsl/linker: fix bug when checking precision qualifier

Still unreviewed. Sam On 12/02/18 09:10, Samuel Iglesias Gonsálvez wrote: > This patch is still unreviewed. > > Sam > > > On 30/01/18 08:50, Samuel Iglesias Gonsálvez wrote: >> According to GLSL ES 3.2 spec, see table in 9.2.1 "Linked Shaders" >> section, the precision qualifier should match for

Re: [Mesa-dev] [PATCH] meson: Add default DRI drivers for ARM/AArch64

On Tuesday, 2018-02-27 10:08:29 +, Daniel Stone wrote: > On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as > 'aarch64'), only build swrast for DRI drivers. The only classic drivers > which could be used are r200 and NV20 cards, which seems unlikely enough > that it shouldn'

Re: [Mesa-dev] [PATCH 01/22] i965: Silence unused parameter warnings

Patches 1-10 are, Reviewed-by: Samuel Iglesias Gonsálvez Sam On 24/02/18 00:55, Ian Romanick wrote: > From: Ian Romanick > > Reduces my build from 7119 warnings to 7005 warnings by silencing 114 > instances of > > In file included from > ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_cont

Re: [Mesa-dev] [PATCH 12/22] nir: Replace an odd comparison involving fmin of -b2f

Reviewed-by: Samuel Iglesias Gonsálvez On 24/02/18 00:55, Ian Romanick wrote: > From: Ian Romanick > > I noticed the fge version while looking at a shader for an unrelated > reason. The feq version prevents a regression in a later change that > performs strength reduction of some compares. > >

Re: [Mesa-dev] [PATCH 13/22] nir: Pull b2f out of bcsel

Reviewed-by: Samuel Iglesias Gonsálvez On 24/02/18 00:55, Ian Romanick wrote: > From: Ian Romanick > > All platforms had similar results. (Skylake shown) > total instructions in shared programs: 14516592 -> 14516586 (<.01%) > instructions in affected programs: 500 -> 494 (-1.20%) > helped: 2 >

Re: [Mesa-dev] [PATCH 14/22] nir: Replace fmin(b2f(a), b) with a bcsel

Reviewed-by: Samuel Iglesias Gonsálvez On 24/02/18 00:55, Ian Romanick wrote: > From: Ian Romanick > > All of the affected shaders are HDR mappers from Serious Sam 3. > > All Gen7+ platforms had similar results. (Skylake shown) > total instructions in shared programs: 14516285 -> 14516273 (<.01

Re: [Mesa-dev] [PATCH 16/22] nir: Simplify some comparisons like a+b < a

Reviewed-by: Samuel Iglesias Gonsálvez Patches 12-14 were also reviewed but I clicked on Reply List, instead of Reply all. Sam On 24/02/18 00:56, Ian Romanick wrote: > From: Ian Romanick > > All Gen7+ platforms had similar results. (Skylake shown) > total instructions in shared programs: 14514

Re: [Mesa-dev] [PATCH] draw: don't needlessly iterate through all sampler view slots

On 27/02/18 02:35, srol...@vmware.com wrote: From: Roland Scheidegger We already stored the highest (potentially) used number. --- src/gallium/auxiliary/draw/draw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/draw/draw_context.c b/src/ga

Re: [Mesa-dev] [RFC] opencl: mega-cl

On 27 February 2018 at 00:26, Rob Clark wrote: > On Mon, Feb 26, 2018 at 6:12 PM, Francisco Jerez > wrote: >> Rob Clark writes: >> >>> On Sun, Feb 25, 2018 at 3:00 PM, Francisco Jerez >>> wrote: Seems like a serious hack to me to work around broken linking... IMO we should just fix

Re: [Mesa-dev] [PATCH] r600/egd_tables.py: added support for python 3

On 23 February 2018 at 15:03, Stefan Dirsch wrote: > Patch by "Tomas Chvatal" with modifications > by "Michal Srb" to not break python 2. > https://bugzilla.suse.com/show_bug.cgi?id=1082303 > > Signed-off-by: Stefan Dirsch > --- > src/gallium/drivers/r600/egd_tables.py | 52 >

Re: [Mesa-dev] [PATCH 17/22] nir: Narrow some dot product operations

Reviewed-by: Samuel Iglesias Gonsálvez On 24/02/18 00:56, Ian Romanick wrote: > From: Ian Romanick > > On vector platforms, this helps elide some constant loads. > > No changes on Broadwell or Skylake. > > Haswell > total instructions in shared programs: 13093793 -> 13060163 (-0.26%) > instruct

Re: [Mesa-dev] [PATCH] configure.ac: Link to libLLVMCodegen to fix cyclic linking problems

On 23 February 2018 at 15:02, Stefan Dirsch wrote: > Patch by "Ismail Doenmez" > https://bugzilla.suse.com/show_bug.cgi?id=1082307 Can anyone provide some information about the cyclic linking problem? Stuff like - mesa configure options, LLVM version and/or actual error will be appreciated. Tha

Re: [Mesa-dev] [PATCH 22/22] nir: Don't i2b a value that is already Boolean

Reviewed-by: Samuel Iglesias Gonsálvez On 24/02/18 00:56, Ian Romanick wrote: > From: Ian Romanick > > A bunch of shaders have sequences like: > > i2b(u2i(floatBitsToUint(intBitsToFloat(x == y ? -1 : 0 > > Other optimizations (and NIR's typeless nature) reduce this to > > i2b(x == y

Re: [Mesa-dev] [RFC PATCH mesa 5/5] WIP - meson: add a message block at the end of the configuration stage

On Friday, 2018-02-23 16:49:14 -0800, Dylan Baker wrote: > Quoting Eric Engestrom (2018-02-23 10:08:48) > > The messages are basically the same as the ones in configure.ac > > > > Signed-off-by: Eric Engestrom > > --- > > Sent out because it's as much as I could do before the weekend, and > > bef

Re: [Mesa-dev] [PATCH 05/21] intel/isl: Use a 4D physical total extent for size calculations

On Thu, Feb 22, 2018 at 11:06:45PM -0800, Jason Ekstrand wrote: > With Yf and Ys tiling, everything is actually four dimensional because > we can have multiple depth or multisampled array slices in the same > tile. This commit just enhances the calculations so they can handle it. > --- > src/inte

Re: [Mesa-dev] [PATCH] glsl/linker: fix bug when checking precision qualifier

On 01/30/2018 09:50 AM, Samuel Iglesias Gonsálvez wrote: According to GLSL ES 3.2 spec, see table in 9.2.1 "Linked Shaders" section, the precision qualifier should match for uniform variables. This also applies to previous GLSL ES 3.x specs. This 'if' checks the condition for uniform variables

Re: [Mesa-dev] [PATCH 06/21] intel/isl: Expose isl_tiling_get_info

On Thu, Feb 22, 2018 at 11:06:46PM -0800, Jason Ekstrand wrote: > --- > src/intel/isl/isl.c | 7 +-- > src/intel/isl/isl.h | 7 +++ > 2 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index 46aff46..95c1271 100644 > --- a/src/in

[Mesa-dev] [RFC PATCH] nir: add support for tg4 with multiple offsets

Just want quick feedback on this. Nouveau can make use of it, which would eliminate the need of having 4 seperate tg4 instructions. The current code runs into the assert when PIPE_CAP_TEXTURE_GATHER_OFFSETS is enabled. Signed-off-by: Karol Herbst --- src/compiler/glsl/glsl_to_nir.cpp

Re: [Mesa-dev] [PATCH] glsl/linker: fix bug when checking precision qualifier

On 27/02/18 13:37, Tapani Pälli wrote: > > > On 01/30/2018 09:50 AM, Samuel Iglesias Gonsálvez wrote: >> According to GLSL ES 3.2 spec, see table in 9.2.1 "Linked Shaders" >> section, the precision qualifier should match for uniform variables. >> This also applies to previous GLSL ES 3.x specs. >

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Tue, Feb 27, 2018 at 6:47 AM, Emil Velikov wrote: > On 27 February 2018 at 00:26, Rob Clark wrote: >> On Mon, Feb 26, 2018 at 6:12 PM, Francisco Jerez >> wrote: >>> Rob Clark writes: >>> On Sun, Feb 25, 2018 at 3:00 PM, Francisco Jerez wrote: > Seems like a serious hack to m

[Mesa-dev] [PATCH v2 4/8] i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layout

Restrict the use of untyped_surface_write with 16-bit pairs in ssbo to the cases where we can guarantee that offset is multiple of 4. Taking into account that VK_KHR_relaxed_block_layout is available in ANV we can only guarantee that when we have a constant offset that is multiple of 4. For non co

[Mesa-dev] [PATCH v2 2/8] i965/fs: shuffle_32bit_load_result_to_16bit_data now skips components

This helper used to load 16bit components from 32-bits read now allows skipping components with the new parameter first_component. The semantics now skip components until we reach the first_component, and then reads the number of components passed to the function. All previous uses of the helper a

[Mesa-dev] [PATCH v2 5/8] anv: Enable VK_KHR_16bit_storage for SSBO and UBO

Enables storageBuffer16BitAccess and uniformAndStorageBuffer16BitAccesss features of VK_KHR_16bit_storage for Gen8+. --- src/intel/vulkan/anv_device.c | 5 +++-- src/intel/vulkan/anv_extensions.py | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan/anv_devi

[Mesa-dev] [PATCH v2 1/8] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit

The surfaces that backup the GPU buffers have a boundary check that considers that access to partial dwords are considered out-of-bounds. For example, buffers with 1,3 16-bit elements has size 2 or 6 and the last two bytes would always be read as 0 or its writting ignored. The introduction of 16-b

[Mesa-dev] [PATCH v2 0/8] anv: VK_KHR_16bit_storage enabling SSBO/UBO/PushConstant

This v2 series includes several fixes to allow enabling the VK_KHR_16bit_storage features in ANV that have already landed but are currently disabled. Main differences with V1 [1] are: * Now UBO/SSBO padding for buffers size not multiple of 4 [1/8] is done in isl and the calculus to get th

[Mesa-dev] [PATCH v2 3/8] i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layout

16-bit load_ubo/ssbo operations that call do_untyped_read_vector don't guarantee that offsets are multiple of 4-bytes as required by untyped_read message. This happens for example in the case of f16mat3x3 when then VK_KHR_relaxed_block_layout is enabled. Vectors reads when we have non-constant off

[Mesa-dev] [PATCH v2 7/8] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

The introduction of 16-bit types with VK_KHR_16bit_storages implies that push constant offsets could be multiple of 2-bytes. Some assertions are updated so offsets should be just multiple of size of the base type but in some cases we can not assume it as doubles aren't aligned to 8 bytes in some ca

[Mesa-dev] [PATCH v2 8/8] anv: Enable VK_KHR_16bit_storage for PushConstant

Enables storagePushConstant16 features of VK_KHR_16bit_storage for Gen8+. --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index a7b586c79c7..7c8b768c589 100644 --- a/src/intel/vulkan

[Mesa-dev] [PATCH v2 6/8] spirv: Calculate properly 16-bit vector sizes

Range in 16-bit push constants load was being calculated wrongly using 4-bytes per element instead of 2-bytes as it should be. v2: Use glsl_get_bit_size instead of if statement (Jason Ekstrand) Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_variables.c | 7 ++- 1 file changed, 2

Re: [Mesa-dev] [PATCH] glsl/linker: fix bug when checking precision qualifier

On 27.02.2018 15:07, Samuel Iglesias Gonsálvez wrote: On 27/02/18 13:37, Tapani Pälli wrote: On 01/30/2018 09:50 AM, Samuel Iglesias Gonsálvez wrote: According to GLSL ES 3.2 spec, see table in 9.2.1 "Linked Shaders" section, the precision qualifier should match for uniform variables. Thi

Re: [Mesa-dev] [PATCH 08/21] intel/isl: Implement correct tile size calculations for Ys/Yf

On Thu, Feb 22, 2018 at 11:06:48PM -0800, Jason Ekstrand wrote: > The tile size calculations use a clever bit of math to make them short > and simple. We add unit tests to assert that they identically match the > tables in the PRM. > --- > src/intel/Makefile.isl.am | 9 +- > src

[Mesa-dev] [PATCH] drm/amdgpu:Fixed wrong emit frame size for enc

Emit frame size should match with corresponding function, uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/driver

Re: [Mesa-dev] [PATCH] drm/amdgpu:Fixed wrong emit frame size for enc

wrong tag, re-submit again On 2018-02-27 10:00 AM, James Zhu wrote: Emit frame size should match with corresponding function, uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [Mesa-dev] [PATCH] radv/gfx9: add a workaround for viewing a slice of 3D as a 2D image

On Mon, Feb 26, 2018 at 11:50 PM, Dave Airlie wrote: > On 26 February 2018 at 23:04, Samuel Pitoiset > wrote: >> Ported from RadeonSI. >> >> That doesn't fix anything known but I think we need it. > > I'd really like it to fix something :-) > > How come we don't also need it for the TXF path? T

Re: [Mesa-dev] [PATCH] configure.ac: Link to libLLVMCodegen to fix cyclic linking problems

On Tue, Feb 27, 2018 at 11:59:22AM +, Emil Velikov wrote: > On 23 February 2018 at 15:02, Stefan Dirsch wrote: > > Patch by "Ismail Doenmez" > > https://bugzilla.suse.com/show_bug.cgi?id=1082307 > > Can anyone provide some information about the cyclic linking problem? > Stuff like - mesa con

Re: [Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

On Tue, Feb 27, 2018 at 3:45 AM, Roland Scheidegger wrote: > Am 27.02.2018 um 03:38 schrieb srol...@vmware.com: >> From: Roland Scheidegger >> >> Some state trackers require 128. >> (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl >> state tracker it's unlikely more than 32 wi

Re: [Mesa-dev] [PATCH 1/2] i965: Add debugging code to dump the validation list.

On Tuesday, February 27, 2018 2:03:52 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-26 23:54:59) > > When anything goes wrong with this code, dumping the validation list > > is a useful way to figure out what's happening. > > --- > > src/mesa/drivers/dri/i965/intel_batchbuffer.c |

Re: [Mesa-dev] [PATCH 2/2] i965: Shorten the name of the workaround BO.

On Tuesday, February 27, 2018 2:04:36 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-26 23:55:00) > > This makes the name shorter in debug printouts. If "workaround_bo" > > is good enough for the code, it's probably good enough for debugging. > > brw->wa_bo and "w/a"? :) > -Chris

Re: [Mesa-dev] [PATCH] st/mesa: ensure that images don't try to reference non-existent levels

Reviewed-by: Marek Olšák Marek On Tue, Feb 27, 2018 at 6:19 AM, Ilia Mirkin wrote: > Ideally the st_finalize_texture call would take care of that, but it > doesn't seem to with KHR-GL45.shader_image_size.advanced-nonMS-*. This > assertions makes sure that no such values are passed to the driver

Re: [Mesa-dev] [PATCH] radeonsi: set some context vars for nir path

Reviewed-by: Marek Olšák Marek On Mon, Feb 26, 2018 at 10:47 AM, Timothy Arceri wrote: > --- > src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 16 ++-- > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c > b

Re: [Mesa-dev] [PATCH] draw: don't needlessly iterate through all sampler view slots

On 02/26/2018 07:35 PM, srol...@vmware.com wrote: From: Roland Scheidegger We already stored the highest (potentially) used number. --- src/gallium/auxiliary/draw/draw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/draw/draw_context.c b/s

Re: [Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

On 02/26/2018 07:45 PM, Roland Scheidegger wrote: Am 27.02.2018 um 03:38 schrieb srol...@vmware.com: From: Roland Scheidegger Some state trackers require 128. (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl state tracker it's unlikely more than 32 will be needed, if you ne

Re: [Mesa-dev] [PATCH 1/2] st/glsl_to_nir: gather next_stage in shader_info

On Mon, Feb 26, 2018 at 10:43 AM, Timothy Arceri wrote: > --- > src/compiler/shader_info.h| 5 + > src/mesa/state_tracker/st_glsl_to_nir.cpp | 13 + > 2 files changed, 18 insertions(+) > > diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h > inde

Re: [Mesa-dev] [PATCH 2/2] radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADER

On Mon, Feb 26, 2018 at 10:43 AM, Timothy Arceri wrote: > --- > src/gallium/drivers/radeonsi/si_shader_nir.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c > b/src/gallium/drivers/radeonsi/si_shader_nir.c > index d410a6c2d6..57f8dc6

Re: [Mesa-dev] [PATCH] ac: fix nir_op_fdd{x,y} handling

Reviewed-by: Marek Olšák Marek On Tue, Feb 27, 2018 at 6:49 AM, Timothy Arceri wrote: > radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as > fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation > decide how it should be handled and radv was previously going > for the h

Re: [Mesa-dev] [PATCH] meson: Add default DRI drivers for ARM/AArch64

Quoting Daniel Stone (2018-02-27 02:08:29) > On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as > 'aarch64'), only build swrast for DRI drivers. The only classic drivers > which could be used are r200 and NV20 cards, which seems unlikely enough > that it shouldn't be the default

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

Quoting Thierry Reding (2018-02-27 02:29:22) > On Mon, Feb 26, 2018 at 12:05:51PM -0800, Dylan Baker wrote: > > Quoting Thierry Reding (2018-02-23 05:18:28) > > > From: Thierry Reding > > > > > > The disk cache implementation uses 64-bit atomic operations. For some > > > architectures, such as 32

Re: [Mesa-dev] [RFC PATCH mesa 5/5] WIP - meson: add a message block at the end of the configuration stage

Quoting Eric Engestrom (2018-02-27 04:12:37) > On Friday, 2018-02-23 16:49:14 -0800, Dylan Baker wrote: > > Quoting Eric Engestrom (2018-02-23 10:08:48) > > > The messages are basically the same as the ones in configure.ac > > > > > > Signed-off-by: Eric Engestrom > > > --- > > > Sent out because

Re: [Mesa-dev] [PATCH] meson: Add default DRI drivers for ARM/AArch64

Hi Dylan, On Tue, 2018-02-27 at 09:13 -0800, Dylan Baker wrote: > Quoting Daniel Stone (2018-02-27 02:08:29) > > --- a/meson.build > > +++ b/meson.build > > @@ -100,6 +100,8 @@ if _drivers == 'auto' > > # TODO: PPC, Sparc > > if ['x86', 'x86_64'].contains(host_machine.cpu_family()) > >

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Mon, Feb 26, 2018 at 05:04:37PM -0800, Jason Ekstrand wrote: > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli > > wrote: > > The size of the clear color struct (expected by the hardware) is 8 > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > track the s

Re: [Mesa-dev] [PATCH] r600/egd_tables.py: added support for python 3

Quoting Emil Velikov (2018-02-27 03:56:30) > On 23 February 2018 at 15:03, Stefan Dirsch wrote: > > Patch by "Tomas Chvatal" with modifications > > by "Michal Srb" to not break python 2. > > https://bugzilla.suse.com/show_bug.cgi?id=1082303 > > > > Signed-off-by: Stefan Dirsch > > --- > > src/

Re: [Mesa-dev] [PATCH] meson: Add default DRI drivers for ARM/AArch64

Quoting Daniel Stone (2018-02-27 09:26:04) > Hi Dylan, > > On Tue, 2018-02-27 at 09:13 -0800, Dylan Baker wrote: > > Quoting Daniel Stone (2018-02-27 02:08:29) > > > --- a/meson.build > > > +++ b/meson.build > > > @@ -100,6 +100,8 @@ if _drivers == 'auto' > > > # TODO: PPC, Sparc > > > i

[Mesa-dev] [PATCH v2 1/2] meson: Add default DRI drivers for ARM/AArch64

On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as 'aarch64'), only build swrast for DRI drivers. The only classic drivers which could be used are r200 and NV20 cards, which seems unlikely enough that it shouldn't be the default. Signed-off-by: Daniel Stone Reported-by: Javier

[Mesa-dev] [PATCH v2 2/2] meson: Don't build svga on ARM/AArch64

VMware has no (published) support for Arm-architecture guests. Signed-off-by: Daniel Stone Cc: Dylan Baker --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index c349e9e5f85..92200a3d64a 100644 --- a/meson.build +++ b/meson.build @@ -

Re: [Mesa-dev] [PATCH v2 1/2] meson: Add default DRI drivers for ARM/AArch64

For the series: Reviewed-by: Dylan Baker Quoting Daniel Stone (2018-02-27 10:01:11) > On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as > 'aarch64'), only build swrast for DRI drivers. The only classic drivers > which could be used are r200 and NV20 cards, which seems unlikel

Re: [Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

Am 27.02.2018 um 17:39 schrieb Brian Paul: > On 02/26/2018 07:45 PM, Roland Scheidegger wrote: >> Am 27.02.2018 um 03:38 schrieb srol...@vmware.com: >>> From: Roland Scheidegger >>> >>> Some state trackers require 128. >>> (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl >>> st

Re: [Mesa-dev] [PATCH] configure.ac: Link to libLLVMCodegen to fix cyclic linking problems

B41;308;0cOn Tue, Feb 27, 2018 at 04:24:04PM +0100, Stefan Dirsch wrote: > On Tue, Feb 27, 2018 at 11:59:22AM +, Emil Velikov wrote: > > On 23 February 2018 at 15:02, Stefan Dirsch wrote: > > > Patch by "Ismail Doenmez" > > > https://bugzilla.suse.com/show_bug.cgi?id=1082307 > > > > Can anyo

Re: [Mesa-dev] [RFC] opencl: mega-cl

Rob Clark writes: > On Mon, Feb 26, 2018 at 6:12 PM, Francisco Jerez > wrote: >> Rob Clark writes: >> >>> On Sun, Feb 25, 2018 at 3:00 PM, Francisco Jerez >>> wrote: Seems like a serious hack to me to work around broken linking... IMO we should just fix the linking issue. The sym

[Mesa-dev] [Bug 105274] Possible buffer overflow in in gallium/auxiliary/hud/hud_cpufreq.c

https://bugs.freedesktop.org/show_bug.cgi?id=105274 Bug ID: 105274 Summary: Possible buffer overflow in in gallium/auxiliary/hud/hud_cpufreq.c Product: Mesa Version: unspecified Hardware: All OS: All

[Mesa-dev] [Bug 105274] Possible buffer overflow in gallium/auxiliary/hud/hud_cpufreq

https://bugs.freedesktop.org/show_bug.cgi?id=105274 vesim...@gmail.com changed: What|Removed |Added Summary|Possible buffer overflow in |Possible buffer overflow in

[Mesa-dev] [Bug 105274] Buffer overflow in gallium/auxiliary/hud/hud_cpufreq

https://bugs.freedesktop.org/show_bug.cgi?id=105274 vesim...@gmail.com changed: What|Removed |Added Summary|Possible buffer overflow in |Buffer overflow in

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

On 27 February 2018 at 05:43, Tapani Pälli wrote: > > > On 02/26/2018 07:55 PM, Emil Velikov wrote: >> >> On 15 February 2018 at 09:12, Tapani Pälli wrote: >>> >>> From: Simon Hausmann >>> >>> When looking up known glsl_type instances in the various hash tables, we >>> end up leaking the key ins

Re: [Mesa-dev] [PATCH v2 1/8] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit

On Tue, Feb 27, 2018 at 5:27 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. > For example, buffers with 1,3 16-bit elements has size 2 or 6

[Mesa-dev] [Bug 105274] Buffer overflow in gallium/auxiliary/hud/hud_cpufreq.c

https://bugs.freedesktop.org/show_bug.cgi?id=105274 vesim...@gmail.com changed: What|Removed |Added Summary|Buffer overflow in |Buffer overflow in

Re: [Mesa-dev] [PATCH v2 2/8] i965/fs: shuffle_32bit_load_result_to_16bit_data now skips components

On Tue, Feb 27, 2018 at 5:27 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > This helper used to load 16bit components from 32-bits read now allows > skipping components with the new parameter first_component. The semantics > now skip components until we reach the first_component,

Re: [Mesa-dev] [PATCH v2 3/8] i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layout

On Tue, Feb 27, 2018 at 5:27 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > 16-bit load_ubo/ssbo operations that call do_untyped_read_vector don't > guarantee that offsets are multiple of 4-bytes as required by untyped_read > message. This happens for example in the case of f16ma

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

Thanks for testing. I'm going to land the build fix with your Tested-by's if nobody raises any concerns in the next 24h. "Kyriazis, George" writes: > It also fixes the errors that I was getting with gcc 5.4.0 with configure > build on ubuntu 16.04. > > Tested-By: George Kyriazis > mailto:geor

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

Please don't wait any longer. We really want appveyor (and some of our own build systems) going again... Roland Am 27.02.2018 um 19:58 schrieb Francisco Jerez: > Thanks for testing. I'm going to land the build fix with your > Tested-by's if nobody raises any concerns in the next 24h. > > "Kyria

Re: [Mesa-dev] [PATCH 2/2] nir: add lower_ldexp to nir compiler options

For the series: Reviewed-by: Marek Olšák Marek On Tue, Feb 27, 2018 at 9:40 AM, Timothy Arceri wrote: > --- > src/broadcom/compiler/nir_to_vir.c | 1 + > src/compiler/nir/nir.h | 2 ++ > src/compiler/nir/nir_opt_algebraic.py | 4 ++-- > src/gallium/drivers/

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

Do you care enough to give me a reviewed-by so I could land it right away? Roland Scheidegger writes: > Please don't wait any longer. We really want appveyor (and some of our > own build systems) going again... > > Roland > > Am 27.02.2018 um 19:58 schrieb Francisco Jerez: >> Thanks for testing.

Re: [Mesa-dev] [PATCH 2/2] ac/radeonsi: add load_base_vertex() to the abi

For the series: Reviewed-by: Marek Olšák Marek On Mon, Feb 26, 2018 at 12:29 PM, Timothy Arceri wrote: > Fixes the following piglit tests: > > ./bin/arb_shader_draw_parameters-basevertex basevertex -auto -fbo > ./bin/arb_shader_draw_parameters-basevertex basevertex-baseinstance -auto -fbo > --

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