[Mesa-dev] [PATCH] r600/atomic: add cayman version of atomic save/restore from GDS (v2)

From: Dave Airlie On Cayman we don't use the append/consume counters (fglrx doesn't) and they don't seem to work well with compute shaders. This just uses GDS instead to do the atomic operations. v1.1: remove unused line. v2: use EOS on cayman, it appears to work. Signed-off-by: Dave Airlie -

Re: [Mesa-dev] [PATCH] radeon/vcn: determine idr by pic type

Am 04.12.2017 um 21:12 schrieb Zhang, Boyuan: Am 30.11.2017 um 22:18 schrieb Leo Liu: On 11/30/2017 04:12 PM, boyuan.zh...@amd.com wrote: From: Boyuan Zhang Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr fr

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

Hi, On 18 November 2017 at 00:10, Jason Ekstrand wrote: > This fixes a bug where we were taking the tiling from the BO regardless > of what the modifier said. When we got images in from Vulkan where it > doesn't set the tiling on the BO, we would treat them as linear even > though the modifier e

Re: [Mesa-dev] [PATCH] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

On Sat, Dec 2, 2017 at 4:43 AM, Rob Herring wrote: > On Fri, Dec 1, 2017 at 8:44 AM, Tomasz Figa wrote: >> On Fri, Dec 1, 2017 at 11:20 PM, Rob Herring wrote: >>> On Fri, Dec 1, 2017 at 7:30 AM, Robert Foss >>> wrote: On Thu, 2017-11-30 at 11:14 -0600, Rob Herring wrote: > On Thu, Nov

Re: [Mesa-dev] [PATCH] nvir: Always split 64-bit IMAD/IMUL operations

On Tue, Dec 5, 2017 at 12:51 AM, Pierre Moreau wrote: > Those operations do not map to actual hardware instructions, therefore > those should always be lowered to 32-bit instructions. > > Fixes: 009c54aa7af "nv50/ir: Split 64-bit integer MAD/MUL operations" > Signed-off-by: Pierre Moreau Reviewe

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 05, 2017 at 05:41:56AM +, Rogovin, Kevin wrote: > Hi, > > The patch series I have submitted handles the case of needing to resolve > texture surfaces when a draw (or compute) accesses a texture which is > astc5x5. As it is quite clear you understand the issue and know the code o

Re: [Mesa-dev] [PATCH] r600/atomic: add cayman version of atomic save/restore from GDS (v2)

On 05.12.2017 09:16, Dave Airlie wrote: From: Dave Airlie On Cayman we don't use the append/consume counters (fglrx doesn't) and they don't seem to work well with compute shaders. This just uses GDS instead to do the atomic operations. v1.1: remove unused line. v2: use EOS on cayman, it appea

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

Hi, >> Here are my comments of the patch posted: >> >> 1. it is essentially replication and moving around of the code of the >> patch series posted earlier but missing various >> important bits: preventing the sampler from using the auxiliary buffer >> (this requires to modify surface

[Mesa-dev] r600 ssbo/image fixes

I've been running deqp-gles31 over the r600 ssbo/image code it uses compute shaders, but I've found a few bugs in the in-tree code, so just sending some fixes out for those first. ssbo seems to pass all the tests, images have some heisenbug where they pass sometimes and not others. Dave. ___

[Mesa-dev] [PATCH 1/6] r600/shader: fix thread id loading.

From: Dave Airlie This just changes how thread id loading is done, it makes smaller shaders if we don't use thread id gprs. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 6/6] r600/ssbo: refactor out buffer coord calcs and use for atomic path.

From: Dave Airlie The atomic rat path has a bug in the ssbo path, refactor out the address calcs from the load/store paths and reuse to fix the bug in the buffer rat atomic path. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 71 ++ 1 fi

[Mesa-dev] [PATCH 3/6] r600: refactor out the immediate setup code.

From: Dave Airlie This just refactors the same code out of the images/buffers paths. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 66 +- 1 file changed, 28 insertions(+), 38 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen

[Mesa-dev] [PATCH 5/6] r600/ssbo: fix multi-dword buffer loads.

From: Dave Airlie This fixes loading from different channels. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c

[Mesa-dev] [PATCH 2/6] r600/shader: fix ssbo atomic operations formats.

From: Dave Airlie Don't try and use the image format for ssbo, just 32-bit uint. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/dri

[Mesa-dev] [PATCH 4/6] r600/ssbo: use r32ui format for ssbo resources.

From: Dave Airlie This works best for returning the correct values and sizes in tests. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/d

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 05, 2017 at 10:26:33AM +, Rogovin, Kevin wrote: > Hi, > > > >> Here are my comments of the patch posted: > >> > >> 1. it is essentially replication and moving around of the code of the > >> patch series posted earlier but missing various > >> important bits: preventing t

[Mesa-dev] [PATCH 1/2] nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUse

In the sched data calculator we have to track first use of defs by iterating over all defs of an instruction, not just the first one. Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 26 -- 1 file changed, 14 insertions(+), 12 deletions(-)

[Mesa-dev] [PATCH 2/2] nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

currently while insterting barriers, writes and reads to FILE_FLAGS aren't considered. This can lead to WaR hazards in some situations. Fixes OpenCL CTS tests on Maxwell+: basic/test_basic.intmath_long.LONG_MAD basic/test_basic.intmath_long2.LONG_MAD basic/test_basic.intmath_long4.LONG_MAD Signed

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 05, 2017 at 01:00:28PM +0200, Pohjolainen, Topi wrote: > On Tue, Dec 05, 2017 at 10:26:33AM +, Rogovin, Kevin wrote: > > Hi, > > > > > > >> Here are my comments of the patch posted: > > >> > > >> 1. it is essentially replication and moving around of the code of the > > >> patc

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

> If you take a look at brw_update_texture_surface(), just in the end before > brw_emit_surface_state() the logic explictly consults for > intel_miptree_texture_aux_usage(). > This in turn tells if the auxiliary buffer is resolved and it doesn't need to > be programmed. The full stack trace is

Re: [Mesa-dev] Fwd: errors for mesa master Android build 1698

On 4 December 2017 at 23:12, Rob Herring wrote: > Looks like Jason is the actual culprit here. Unfortunately, the build > can't keep up with every commit. Looks to me like these should be > fixed. > > I wonder how long until I give up and just set Android back to -Wno-error... > Please go back to

Re: [Mesa-dev] [PATCH] Android: enable noreturn and returns_nonnull attributes

On 5 December 2017 at 02:21, Rob Herring wrote: > Commit 94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers") broke > Android builds which have -Werror enabled with the following errors: > > external/mesa3d/src/compiler/spirv/spirv_to_nir.c:272:1: error: control may > reach end of non-void

Re: [Mesa-dev] [PATCH] Android: gallium/radeon: fix libmesa_amd_common dependency

On 4 December 2017 at 15:13, Marek Olšák wrote: > Reviewed-by: Marek Olšák > ... and pushed to master. Thanks gents. Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

This is a bit sad/annoying. But with current GPU firmware (at least on a5xx) we can support both draw-indirect and base-instance. But we can't support draw-indirect with a non-zero base-instance specified. So add a driconf option to hide the extension from games that are known to use both. Sign

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On Tue, Dec 5, 2017 at 7:54 AM, Rob Clark wrote: > This is a bit sad/annoying. But with current GPU firmware (at least on > a5xx) we can support both draw-indirect and base-instance. But we can't > support draw-indirect with a non-zero base-instance specified. So add a That means you should on

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On Tue, Dec 5, 2017 at 8:02 AM, Ilia Mirkin wrote: > On Tue, Dec 5, 2017 at 7:54 AM, Rob Clark wrote: >> This is a bit sad/annoying. But with current GPU firmware (at least on >> a5xx) we can support both draw-indirect and base-instance. But we can't >> support draw-indirect with a non-zero bas

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

Hi Rob, On 5 December 2017 at 12:54, Rob Clark wrote: > This is a bit sad/annoying. But with current GPU firmware (at least on > a5xx) we can support both draw-indirect and base-instance. But we can't > support draw-indirect with a non-zero base-instance specified. So add a > driconf option to

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov wrote: > Hi Rob, > > On 5 December 2017 at 12:54, Rob Clark wrote: >> This is a bit sad/annoying. But with current GPU firmware (at least on >> a5xx) we can support both draw-indirect and base-instance. But we can't >> support draw-indirect with a no

[Mesa-dev] [PATCH] nvir/nvc0: fix CVT lowering for dType == sType

The lowering code can't really handle that situation well and we just get away with converting it to OP_MOV in this case. Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/nou

Re: [Mesa-dev] [PATCH] nvir/nvc0: fix CVT lowering for dType == sType

uhh, seems like this code isn't in master yet, so ignore this please. On Tue, Dec 5, 2017 at 3:17 PM, Karol Herbst wrote: > The lowering code can't really handle that situation well and we just get away > with converting it to OP_MOV in this case. > > Signed-off-by: Karol Herbst > --- > src/gal

Re: [Mesa-dev] [PATCH] nvir/nvc0: fix CVT lowering for dType == sType

An in any case, CVT with stype == dtype is illegal - whatever generates that should be fixed. On Tue, Dec 5, 2017 at 9:23 AM, Karol Herbst wrote: > uhh, seems like this code isn't in master yet, so ignore this please. > > On Tue, Dec 5, 2017 at 3:17 PM, Karol Herbst wrote: >> The lowering code c

Re: [Mesa-dev] [PATCH] Android: enable noreturn and returns_nonnull attributes

On Tue, Dec 5, 2017 at 5:56 AM, Emil Velikov wrote: > On 5 December 2017 at 02:21, Rob Herring wrote: >> Commit 94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers") broke >> Android builds which have -Werror enabled with the following errors: >> >> external/mesa3d/src/compiler/spirv/spirv_

[Mesa-dev] [PATCH] mesa/st: move cloning of NIR shader for compute

Since in the NIR case, driver takes ownership of the NIR shader, we need to clone what is passed to the driver. Normally this is done as part of creating the shader variant (where is clone is anyways needed). But compute shaders have no variants, so we were cloning earlier. The problem is that a

Re: [Mesa-dev] [PATCH 3/8] glapi/check_table: Remove 'extern "C"' block

On 4 December 2017 at 23:57, Dylan Baker wrote: > Quoting Emil Velikov (2017-11-23 11:04:34) >> On 20 November 2017 at 23:12, Dylan Baker wrote: >> > This doesn't actually accomplish what it's meant to do, as extern C >> > doesn't undefine __cplusplus, so the included headers define a template >>

Re: [Mesa-dev] [PATCH] nvir/nvc0: fix CVT lowering for dType == sType

On Tue, Dec 5, 2017 at 9:34 AM, Ilia Mirkin wrote: > An in any case, CVT with stype == dtype is illegal - whatever > generates that should be fixed. Without source modifiers, that is :) "cvt f32 dst neg src" is just fine of course. ___ mesa-dev mailing

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 Bug ID: 104119 Summary: radv: OpBitFieldInsert produces 0 with a loop counter for Insert Product: Mesa Version: git Hardware: Other OS: All Sta

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 --- Comment #1 from James Legg --- Created attachment 135981 --> https://bugs.freedesktop.org/attachment.cgi?id=135981&action=edit SPIR-V disassembly of test shader -- You are receiving this mail because: You are the QA Contact for the bug.

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 --- Comment #2 from James Legg --- Created attachment 135982 --> https://bugs.freedesktop.org/attachment.cgi?id=135982&action=edit Output from RADV_DEBUG=shaders -- You are receiving this mail because: You are the assignee for the bug. You a

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

On Tue, Dec 5, 2017 at 1:22 AM, Daniel Stone wrote: > Hi, > > On 18 November 2017 at 00:10, Jason Ekstrand wrote: > > This fixes a bug where we were taking the tiling from the BO regardless > > of what the modifier said. When we got images in from Vulkan where it > > doesn't set the tiling on t

[Mesa-dev] [PATCH] glx: GLX_MESA_multithread_makecurrent is direct-only

This extension is not defined for indirect contexts. Marking it as "client only", as the old code did here, would make the extension available in indirect contexts, even though the server would certainly not have it in its extension list. Cc: Signed-off-by: Adam Jackson --- src/glx/glxextension

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

On Tue, Dec 5, 2017 at 7:57 AM, Jason Ekstrand wrote: > On Tue, Dec 5, 2017 at 1:22 AM, Daniel Stone wrote: >> >> Hi, >> >> On 18 November 2017 at 00:10, Jason Ekstrand wrote: >> > This fixes a bug where we were taking the tiling from the BO regardless >> > of what the modifier said. When we go

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

On Tue, Dec 5, 2017 at 8:23 AM, Kristian Høgsberg wrote: > On Tue, Dec 5, 2017 at 7:57 AM, Jason Ekstrand > wrote: > > On Tue, Dec 5, 2017 at 1:22 AM, Daniel Stone > wrote: > >> > >> Hi, > >> > >> On 18 November 2017 at 00:10, Jason Ekstrand > wrote: > >> > This fixes a bug where we were takin

[Mesa-dev] [PATCH] swr/scons: Fix another intermittent build failure

gen_BackendPixelRate*.cpp depends on gen_ar_eventhandler.hpp. Fix missing dependency. --- src/gallium/drivers/swr/SConscript | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/swr/SConscript b/src/gallium/drivers/swr/SConscript index 9204ecb..eca4830 100644 --- a/src/gallium/

[Mesa-dev] [PATCH 1/3] st/mesa: whitespace fixes in st_format.c

--- src/mesa/state_tracker/st_format.c | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/mesa/state_tracker/st_format.c b/src/mesa/state_tracker/st_format.c index 1ae677d..da8b5e2 100644 --- a/src/mesa/state_tracker/st_format.c +++ b/src/mesa/state_tracke

[Mesa-dev] [PATCH 3/3] st/mesa: remove unneeded #include in st_format.h

--- src/mesa/state_tracker/st_format.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/state_tracker/st_format.h b/src/mesa/state_tracker/st_format.h index 3dd9c10..466b5d0 100644 --- a/src/mesa/state_tracker/st_format.h +++ b/src/mesa/state_tracker/st_format.h @@ -33,7 +33,6 @@ #inc

[Mesa-dev] [PATCH 2/3] st/mesa: rename a few vars to 'bindings'

To be consistent. --- src/mesa/state_tracker/st_format.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mesa/state_tracker/st_format.c b/src/mesa/state_tracker/st_format.c index da8b5e2..3f7e55e 100644 --- a/src/mesa/state_tracker/st_format.c +++ b/

[Mesa-dev] [PATCH 3/4] mesa: simplify/improve some _mesa_error() calls in teximage.c

--- src/mesa/main/teximage.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index 41de966..572e380 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -5778,14 +5778,10 @@ texture_image_mult

[Mesa-dev] [PATCH 1/4] mesa: add const qualifier in test_attachment_completeness()

--- src/mesa/main/fbobject.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index 8116563..f7702f1 100644 --- a/src/mesa/main/fbobject.c +++ b/src/mesa/main/fbobject.c @@ -793,7 +793,7 @@ test_attachment_completeness(const st

[Mesa-dev] [PATCH 2/4] mesa: trivial whitespace fixes in transformfeedback.c

--- src/mesa/main/transformfeedback.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mesa/main/transformfeedback.c b/src/mesa/main/transformfeedback.c index a5ea2a5..e4cc1db 100644 --- a/src/mesa/main/transformfeedback.c +++ b/src/mesa/main/transformfee

[Mesa-dev] [PATCH 4/4] mesa: s/%u/%d/ in _mesa_error() call in check_layer()

The layer parameter is signed. Fixes the error message seen when running the arb_texture_multisample-errors test which checks a negative layer value. --- src/mesa/main/fbobject.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobjec

Re: [Mesa-dev] [PATCH] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

On Tue, 2017-12-05 at 18:22 +0900, Tomasz Figa wrote: > On Sat, Dec 2, 2017 at 4:43 AM, Rob Herring wrote: > > On Fri, Dec 1, 2017 at 8:44 AM, Tomasz Figa > > wrote: > > > On Fri, Dec 1, 2017 at 11:20 PM, Rob Herring > > > wrote: > > > > On Fri, Dec 1, 2017 at 7:30 AM, Robert Foss > > > ora.com

Re: [Mesa-dev] [PATCH 3/3] st/mesa: remove unneeded #include in st_format.h

Series is Reviewed-by: Ilia Mirkin On Tue, Dec 5, 2017 at 11:59 AM, Brian Paul wrote: > --- > src/mesa/state_tracker/st_format.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/mesa/state_tracker/st_format.h > b/src/mesa/state_tracker/st_format.h > index 3dd9c10..466b5d0 100644 >

[Mesa-dev] [PATCH 1/1] radv: use a faster version for nir_op_pack_half_2x16

This patch is ported from RadeonSI and it has two effects. It fixes a rendering issue which affects F1 2017 and Dawn of War 3 (Vega only) because LLVM was ending up by generating the new v_mad_mix_{hi,lo} instructions which appear to be buggy in some way. Not sure if Mesa is generating something w

[Mesa-dev] [PATCH 0/1] radv: bugfix for F1 2017 and DOW3 on Vega

Hi folks, It took me a while to figure out the issue which is addressed by the following patch, but I think it should be the right one (see the patch description for more explanations). Keep in mind that DOW3 is still affected by one other issue (Vega only). Hopefully, I will be able to write a p

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

El 30/11/17 a las 23:58, Jason Ekstrand escribió: > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit > surface format defined. So when reading 16-bit components with the

Re: [Mesa-dev] [PATCH] i965: Enable disk shader cache by default

Jordan Justen writes: > On 2017-11-08 17:26:47, Timothy Arceri wrote: >> Reviewed-by: Timothy Arceri >> >> Mark may want to consider adding some of the once a day type CI runs for >> this. For example running the test suite for two consecutive runs on the >> same build so that the second run

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 --- Comment #3 from Samuel Pitoiset --- Something is wrong in the NIR. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailin

Re: [Mesa-dev] [PATCH v4 00/44] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

El 05/12/17 a las 06:16, Jason Ekstrand escribió: > A couple of notes: > >  1) I *think* I gave you enough reviews to land the UBO/SSBO part and > the optimizations in 26-28.  If reviews are still missing anywhere, > please let me know.  If not, let's try and get that part landed. The series is al

Re: [Mesa-dev] [PATCH 3/8] glapi/check_table: Remove 'extern "C"' block

Quoting Emil Velikov (2017-12-05 07:36:25) > On 4 December 2017 at 23:57, Dylan Baker wrote: > > Quoting Emil Velikov (2017-11-23 11:04:34) > >> On 20 November 2017 at 23:12, Dylan Baker wrote: > >> > This doesn't actually accomplish what it's meant to do, as extern C > >> > doesn't undefine __cp

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 --- Comment #4 from Samuel Pitoiset --- Possible fix: diff --git i/src/amd/vulkan/radv_shader.c w/src/amd/vulkan/radv_shader.c index 4a3fdfa80e..0b19d23fa2 100644 --- i/src/amd/vulkan/radv_shader.c +++ w/src/amd/vulkan/radv_shader.c @@ -66,6 +6

[Mesa-dev] [Bug 103126] glthread doesn't offload anything in Witcher 2

https://bugs.freedesktop.org/show_bug.cgi?id=103126 --- Comment #2 from Alexander Tsoy --- I had the same problem with other eON ports: Spec Ops: The Line and Overlord at least. It's turned out that it's due to disabled assembly in my 32-bit mesa build (--disable-asm). Not sure if it worth fixing

[Mesa-dev] [PATCH] meson: Fix building gallium media targets with gallium-xlib glx

Signed-off-by: Dylan Baker --- meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 3e8ea7d17e0..bf6bd551f08 100644 --- a/meson.build +++ b/meson.build @@ -1107,9 +1107,9 @@ if with_platform_x11 dep_xcb_glx = dependency('xcb-gl

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

On Tue, Dec 5, 2017 at 8:49 AM, Jason Ekstrand wrote: > On Tue, Dec 5, 2017 at 8:23 AM, Kristian Høgsberg > wrote: >> >> On Tue, Dec 5, 2017 at 7:57 AM, Jason Ekstrand >> wrote: >> > On Tue, Dec 5, 2017 at 1:22 AM, Daniel Stone >> > wrote: >> >> >> >> Hi, >> >> >> >> On 18 November 2017 at 00:1

Re: [Mesa-dev] [PATCH 2/2] i965/miptree: Use the tiling from the modifier instead of the BO

On Tue, Dec 5, 2017 at 9:43 AM, Kristian Høgsberg wrote: > On Tue, Dec 5, 2017 at 8:49 AM, Jason Ekstrand wrote: >> On Tue, Dec 5, 2017 at 8:23 AM, Kristian Høgsberg >> wrote: >>> >>> On Tue, Dec 5, 2017 at 7:57 AM, Jason Ekstrand >>> wrote: >>> > On Tue, Dec 5, 2017 at 1:22 AM, Daniel Stone >

[Mesa-dev] [PATCH 2/2] radv: enable lowering of nir_op_bitfield_extract

This instruction should also be lowered correctly. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 0b19d23fa2..044bcd0641 100644 --- a/src/amd/vulkan/radv_shader.

[Mesa-dev] [PATCH 1/2] radv: enable lowering of nir_op_bitfield_insert

Otherwise it's replaced by "vec1 32 ssa_108 = load_const (0x /* 0.00 */)", which looks clearly wrong. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104119 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/

[Mesa-dev] [Bug 104119] radv: OpBitFieldInsert produces 0 with a loop counter for Insert

https://bugs.freedesktop.org/show_bug.cgi?id=104119 --- Comment #5 from Samuel Pitoiset --- Patch is on the list. https://patchwork.freedesktop.org/series/34930/ -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___

Re: [Mesa-dev] [PATCH] mesa/st: move cloning of NIR shader for compute

Reviewed-by: Marek Olšák Marek On Tue, Dec 5, 2017 at 4:05 PM, Rob Clark wrote: > Since in the NIR case, driver takes ownership of the NIR shader, we need > to clone what is passed to the driver. Normally this is done as part of > creating the shader variant (where is clone is anyways needed).

[Mesa-dev] [Bug 104035] When will the egl introp for vaapi be implemented

https://bugs.freedesktop.org/show_bug.cgi?id=104035 Vedran Miletić changed: What|Removed |Added CC||ved...@miletic.net -- You are receivi

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 05, 2017 at 10:26:33AM +, Rogovin, Kevin wrote: > Hi, > > > >> Here are my comments of the patch posted: > >> > >> 1. it is essentially replication and moving around of the code of the > >> patch series posted earlier but missing various > >> important bits: preventing t

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 5, 2017 at 10:17 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Tue, Dec 05, 2017 at 10:26:33AM +, Rogovin, Kevin wrote: > > Hi, > > > > > > >> Here are my comments of the patch posted: > > >> > > >> 1. it is essentially replication and moving around of the code

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

> Are you saying that this bug extends over hardware context? Different HW contexts imply different execbuffer2 ioctl's. The kernel inserts a full blown flush of everything after (or before, I cannot remember) each execbuffer2 call. This way there is context isolation in HW buggineness. -Kevin

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

Hi, >This isn't true.  100% of the intel_mipmap_tree -> blorp_surf translations are >handled by that function.  > It's a perfectly reasonable place to handle these things.  It could also be > handled in genX(blorp_exec) if that makes someone more comfortable. This is where I placed the ASTC en

Re: [Mesa-dev] [PATCH v2] st/mesa: swizzle argument when there's a vector size mismatch

Reviewed-by: Marek Olšák Marek On Tue, Dec 5, 2017 at 5:26 AM, Ilia Mirkin wrote: > GLSL IR operation arguments can sometimes have an implicit swizzle as a > result of a vector arg and a scalar arg, where the scalar argument is > implicitly expanded to the size of the vector argument. > > Bugzi

Re: [Mesa-dev] [PATCH 4/4] mesa: s/%u/%d/ in _mesa_error() call in check_layer()

For the series: Reviewed-by: Marek Olšák Marek On Tue, Dec 5, 2017 at 6:00 PM, Brian Paul wrote: > The layer parameter is signed. Fixes the error message seen when > running the arb_texture_multisample-errors test which checks a > negative layer value. > --- > src/mesa/main/fbobject.c | 3 +-

Re: [Mesa-dev] [PATCH] RFC: Workaround for gen9 hw astc5x5 sampler bug

On Tue, Dec 5, 2017 at 10:34 AM, Rogovin, Kevin wrote: > Hi, > > >This isn't true. 100% of the intel_mipmap_tree -> blorp_surf > translations are handled by that function. > > It's a perfectly reasonable place to handle these things. It could > also be handled in genX(blorp_exec) if that makes

Re: [Mesa-dev] [PATCH 3/3] st/mesa: remove unneeded #include in st_format.h

For the series: Reviewed-by: Marek Olšák Marek On Tue, Dec 5, 2017 at 5:59 PM, Brian Paul wrote: > --- > src/mesa/state_tracker/st_format.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/mesa/state_tracker/st_format.h > b/src/mesa/state_tracker/st_format.h > index 3dd9c10..466b5

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

On Tue, Dec 5, 2017 at 9:08 AM, Chema Casanova wrote: > El 30/11/17 a las 23:58, Jason Ekstrand escribió: > > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > > mailto:jmcasan...@igalia.com>> wrote: > > > > load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit > >

[Mesa-dev] [PATCH 2/6] radeonsi: print the buffer list for CHECK_VM

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_debug.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 22609b7..385ce39 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drive

[Mesa-dev] [PATCH 3/6] winsys/amdgpu: make IBs use read-only memory

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 089a358..63cd632 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/galli

[Mesa-dev] [PATCH 5/6] radeonsi: use a separate allocator for fine fences

From: Marek Olšák --- src/gallium/drivers/radeon/r600_pipe_common.c | 7 +++ src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeonsi/si_fence.c | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c

[Mesa-dev] [PATCH 4/6] radeonsi/gfx9: make shader binaries use read-only memory

From: Marek Olšák --- src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++ src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 2 ++ src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_shader.c| 9

[Mesa-dev] [PATCH 1/6] radeonsi: allow DMABUF exports for local buffers

From: Marek Olšák Cc: 17.3 --- src/gallium/drivers/radeon/r600_texture.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 2aa47b5..07f7c33 100644 --- a/src/gallium/drivers/radeon

[Mesa-dev] [PATCH 6/6] radeonsi: make const and stream uploaders allocate read-only memory

From: Marek Olšák and anything that clones these uploaders, like u_threaded_context. --- src/gallium/drivers/radeon/r600_pipe_common.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_

[Mesa-dev] [PATCH 1/2] mesa: add const qualifier on _mesa_base_fbo_format()

--- src/mesa/main/fbobject.c | 2 +- src/mesa/main/fbobject.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index 30287ab..d23916d 100644 --- a/src/mesa/main/fbobject.c +++ b/src/mesa/main/fbobject.c @@ -1804,7 +1804,7 @@

[Mesa-dev] [PATCH 2/2] mesa: add const qualifier on _mesa_is_renderable_texture_format()

--- src/mesa/main/teximage.c | 3 ++- src/mesa/main/teximage.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index 572e380..e5f8bb0 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -5712,7 +5712,8

Re: [Mesa-dev] [PATCH 1/2] radv: enable lowering of nir_op_bitfield_insert

lower_bitfield_insert lowers nir_op_bitfield_insert to DX10-style nir_op_bfi and nir_op_bfm, both of which aren't handled by ac_nir_to_llvm, so unless I'm missing something this will just break them even harder. We probably should use this lowering after adding support for bfi and bfm, since AMD do

Re: [Mesa-dev] [PATCH 2/2] radv: enable lowering of nir_op_bitfield_extract

Same comment as the previous patch. On Tue, Dec 5, 2017 at 12:50 PM, Samuel Pitoiset wrote: > This instruction should also be lowered correctly. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_shader.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/amd/vulkan/radv_s

Re: [Mesa-dev] [PATCH 6/6] glx: Implement GLX_EXT_no_config_context (v3)

On Thu, 2017-11-30 at 16:10 +, Emil Velikov wrote: > On 14 November 2017 at 20:13, Adam Jackson wrote: > > > @@ -562,6 +562,10 @@ dri2_convert_glx_attribs(unsigned num_attribs, > > const uint32_t *attribs, > > return false; > > } > > break; > > + case GLX

Re: [Mesa-dev] [PATCH] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

On Tue, Dec 5, 2017 at 11:01 AM, Robert Foss wrote: > On Tue, 2017-12-05 at 18:22 +0900, Tomasz Figa wrote: >> On Sat, Dec 2, 2017 at 4:43 AM, Rob Herring wrote: >> > On Fri, Dec 1, 2017 at 8:44 AM, Tomasz Figa >> > wrote: >> > > On Fri, Dec 1, 2017 at 11:20 PM, Rob Herring >> > > wrote: >> > >

Re: [Mesa-dev] [PATCH] i965: Enable disk shader cache by default

On 2017-12-05 09:13:11, Mark Janes wrote: > Jordan Justen writes: > > > On 2017-11-08 17:26:47, Timothy Arceri wrote: > >> Reviewed-by: Timothy Arceri > >> > >> Mark may want to consider adding some of the once a day type CI runs for > >> this. For example running the test suite for two consec

[Mesa-dev] [PATCH 1/2] radv: fix a case statement in GetMemoryFdPropertiesKHR

The handle type in the case statement is supposed to be VK_EXTERNAL_- MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT. Signed-off-by: Fredrik Höglund --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.

[Mesa-dev] [PATCH 2/2] anv: fix a case statement in GetMemoryFdPropertiesKHR

The handle type in the case statement is supposed to be VK_EXTERNAL_- MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT. Signed-off-by: Fredrik Höglund --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_devi

Re: [Mesa-dev] [PATCH 2/2] anv: fix a case statement in GetMemoryFdPropertiesKHR

Oops. Both are Reviewed-by: Jason Ekstrand On Tue, Dec 5, 2017 at 12:51 PM, Fredrik Höglund wrote: > The handle type in the case statement is supposed to be VK_EXTERNAL_- > MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT. > > Signed-off-by: Fredrik Höglund > --- > src/intel/vulkan/anv_device.c | 2 +- >

[Mesa-dev] [PATCH 1/3] glx: Move vertex array protocol state into the indirect backend (v2)

Only relevant for indirect contexts, so let's get that code out of the common path. v2: Add the necessary context setup before calling GetString Signed-off-by: Adam Jackson --- src/glx/glxcurrent.c | 12 src/glx/indirect_glx.c | 26 ++ 2 files changed, 22

[Mesa-dev] [PATCH 2/3] glx: Lift sending the MakeCurrent request to top-level code (v2)

Somewhat terrifyingly, we never sent this for direct contexts, which means the server never knew the context/drawable bindings. To handle this sanely, pull the request code up out of the indirect backend, and rewrite the context switch path to call it as appropriate. This attempts to preserve the

[Mesa-dev] [PATCH 3/3] glx: Implement GLX_EXT_no_config_context (v4)

This more or less ports EGL_KHR_no_config_context to GLX. v2: Enable the extension only for those backends that support it. v3: Fix glvnd path and dri2_convert_glx_attribs() v4: Screeching signedness correctness, and disable a now inappropriate test. Khronos: https://github.com/KhronosGroup/O

[Mesa-dev] [PATCH 0/3] GLX_EXT_no_config_context v4

With one exception (noted in 2/3) this is now regression-free in piglit, and passes make check. - ajax ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

On 05/12/17 19:53, Jason Ekstrand wrote: > On Tue, Dec 5, 2017 at 9:08 AM, Chema Casanova > wrote: > > El 30/11/17 a las 23:58, Jason Ekstrand escribió: > > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > > mailto:jmcasan...@igalia.com> >

[Mesa-dev] [PATCH v4 28/44] i965/fs: Use untyped_surface_read for 16-bit load_ssbo (v2)

SSBO loads were using byte_scattered read messages as they allow reading 16-bit size components. byte_scattered messages can only operate one component at a time so we needed to emit as many messages as components. But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the untyped_su

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