On 02/05/16 09:02, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:15PM +0200, Samuel Iglesias Gons?lvez wrote:
>> From: Iago Toral Quiroga
>>
>> ---
>> src/mesa/drivers/dri/i965/brw_shader.cpp | 28 ++--
>> 1 file changed, 22 insertions(+), 6 deletions(-)
>>
>>
On 02/05/16 09:56, Iago Toral wrote:
> On Mon, 2016-05-02 at 10:54 +0300, Pohjolainen, Topi wrote:
>> On Mon, May 02, 2016 at 09:42:14AM +0200, Iago Toral wrote:
>>> On Mon, 2016-05-02 at 10:34 +0300, Pohjolainen, Topi wrote:
On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
>
Am 03.05.2016 um 08:39 schrieb Mathieu Malaterre:
AGP mode is unstable on PowerPC
Your signed of by line is missing, but apart from that the patch is
Reviewed-by: Christian König .
Regards,
Christian.
---
drivers/gpu/drm/radeon/radeon_drv.c | 5 +
1 file changed, 5 insertions(+)
di
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 02/05/16 09:13, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:20PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> From: Connor Abbott
>>
>> v2 (Iago): - Squashed bits from 'support double precission
>> constant operands for the implem
On Mon, May 2, 2016 at 12:42 AM, Iago Toral wrote:
> On Mon, 2016-05-02 at 10:34 +0300, Pohjolainen, Topi wrote:
>> On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
>> > On Mon, 2016-05-02 at 10:08 +0300, Pohjolainen, Topi wrote:
>> > > On Mon, May 02, 2016 at 10:02:50AM +0300, Pohjolai
From: Dave Airlie
GL43-CTS.compute_shader.work-group-size does
uniform uint g_uniform[gl_WorkGroupSize.z + 20] = {
1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24 };
we crash in here, returning false, makes things work.
I've no idea if this is in any way correct.
Signed-off-by:
On 02/05/16 09:22, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:23PM +0200, Samuel Iglesias Gons?lvez wrote:
>> From: Connor Abbott
>>
>> v2 (Sam):
>> - Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float()
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12
On 02/05/16 09:22, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:23PM +0200, Samuel Iglesias Gons?lvez wrote:
>> From: Connor Abbott
>>
>> v2 (Sam):
>> - Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float()
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12
On Tue, May 03, 2016 at 09:22:23AM +0200, Samuel Iglesias Gons?lvez wrote:
>
>
> On 02/05/16 09:22, Pohjolainen, Topi wrote:
> > On Fri, Apr 29, 2016 at 01:29:23PM +0200, Samuel Iglesias Gons?lvez wrote:
> >> From: Connor Abbott
> >>
> >> v2 (Sam):
> >> - Add bitsize to brw_type_for_nir_type() i
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 02/05/16 10:17, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:27PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> From: Connor Abbott
>>
>> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 1
>> file changed, 12 insertion
From: Dave Airlie
This prevents GL43-CTS.khr_debug.labels_non_debug from
memcpying all over the stack, it doesn't fix the test,
but it stops the crash.
Signed-off-by: Dave Airlie
---
src/mesa/main/objectlabel.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/main/objectlabel.
-BEGIN PGP SIGNED MESSAGE-
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On 02/05/16 10:38, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:29PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> From: Iago Toral Quiroga
>>
>> When we are actually unpacking from a double that we have
>> previously packed from its 3
From: Dave Airlie
This prevents GL43-CTS.khr_debug.labels_non_debug from
memcpying all over the stack and crashing.
v2: actually fix the test.
Signed-off-by: Dave Airlie
---
src/mesa/main/objectlabel.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/main/objectlabel.c b/src/
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On 02/05/16 11:01, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:40PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> From: Connor Abbott
>>
>> --- src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +- 1 file
>> changed, 1 insertion(+), 1 delet
-BEGIN PGP SIGNED MESSAGE-
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On 02/05/16 14:33, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:55PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> Signed-off-by: Samuel Iglesias Gonsálvez
>> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 ++-- 1 file
>> changed, 2 i
On Tue, May 03, 2016 at 09:35:42AM +0200, Samuel Iglesias Gons?lvez wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
>
>
> On 02/05/16 10:38, Pohjolainen, Topi wrote:
> > On Fri, Apr 29, 2016 at 01:29:29PM +0200, Samuel Iglesias Gons?lvez
> > wrote:
> >> From: Iago Toral Quiroga
> >
As far as I see the spec itself doesn't include what happens if bufSize
is zero (note that is included as a big commet) (spec bug?), but I agree
that the more reasonable is applying what happens when src is null but
label is not.
Or in other words: LGTM
Reviewed-by: Alejandro Piñeiro
On 03/05/1
Reviewed-by: Marek Olšák
Marek
On Mon, May 2, 2016 at 11:24 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This tells LLVM to always use SMEM loads for descriptors. It fixes a
> regression in piglit's
> arb_shader_storage_buffer_object/execution/indirect.shader_test
> that was caused by
-BEGIN PGP SIGNED MESSAGE-
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On 02/05/16 23:50, Mark Janes wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> Hello,
>>
>> This patch series continues adding arb_gpu_shader_fp64 support to
>> the Intel driver. Specifically, this targets the i965 scalar
>> backend for BDW+ har
On Mon, May 2, 2016 at 10:21 PM, Dave Airlie wrote:
>
> From: Dave Airlie
>
> GL43-CTS.texture_view.errors checks for GL_INVALID_VALUE
> here but we catch these problems in the dimensionsOK check
> and return the wrong error value.
>
> This fixes:
> GL43-CTS.texture_view.errors.
>
> Signed-off-by
On Mon, May 2, 2016 at 11:11 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes
> GL43-CTS.copy_image.samples_missmatch
> which otherwise asserts in the radeonsi driver.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/main/copyimage.c | 14 ++
> 1 file changed, 14 insertions(
Reviewed-by: Emil Velikov and pushed to master.
Thanks Knut !
Emil
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Hello,
This series adds the final bits to support arb_gpu_shader_fp64 in the
i965 scalar backend for BDW+ hardware. It sits on top of the previous
series we sent last week [0] and which is going through review at the
moment. Specifically, this series adds:
1. Fixes to copy propagation required fo
From: Iago Toral Quiroga
This can happen if the register already has a non-zero subreg_offset
when byte_offset() is called.
---
src/mesa/drivers/dri/i965/brw_ir_fs.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
b/src/mesa/drivers/dri/i965/brw_ir_
From: Iago Toral Quiroga
We should not offset into them based on the relative offset of
our source and the destination of the instruction we are copy
propagating from, so we don't turn this:
mov(16) vgrf6:F, vgrf7+0.0<0>:F
(...)
load_payload(8) vgrf28:F, vgrf6+1.0:F 2ndhalf
mov(8) vgrf29:DF, vgr
From: Iago Toral Quiroga
When source modifiers are present and the types of the source and
the entry's source are different, there are certain cases in which
we allow copy-propagation to change the type of source by the type
of the entry's source we are copy propagating from.
However, it is not
From: Iago Toral Quiroga
Specifically, consider the size of the data type of the operand to compute
the number of registers written.
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy
From: Iago Toral Quiroga
We were not invalidating entries with a src that reads more than one register
when we find writes that overwrite any register read by entry->src after
the first. This leads to incorrect copy propagation because we re-use
entries from the ACP that have been partially inval
From: Iago Toral Quiroga
We were not accounting for reg_suboffset in the check for the start
of the region. This meant that would allow copy-propagation even if
the dst wrote to sub_regoffset 4 and our source read from
sub_regoffset 0, which is not correct. This was observed in fp64 code,
since t
From: Iago Toral Quiroga
The current code ignores the suboffet in the instruction's source
and just uses the one from the constant. This is not correct
when the instruction's source is accessing the constant with a
different type and using the suboffset to select a specific
chunk of the constant.
From: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 49 ++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bc81a80..0e69be8 100644
--- a/src/mesa/dr
From: Iago Toral Quiroga
Because the stride is in units for the type, if we copy-propagate from
a another instruction using a larger type, then we need to make sure
that the source in that instruction, the one we will be copy-propagating
from, sources consecutive elements, otherwise, when sourced
From: Iago Toral Quiroga
We were not considering the case where the load payload is writing to
a destination with a reg_offset > 0.
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_
From: Iago Toral Quiroga
The transposition needs to set exec_all() but it writes directly to the
original instruction's destination, which can lead to execmasking
problems if the original instruction did not have force_writemask_all
set. In that case, write the result of the operation to a tempor
From: Iago Toral Quiroga
UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4 starting at a
constant offset that is 16-byte aligned. If we need to access an unaligned
offset we emit a load with an aligned offset and use the remaining constant
offset to select the component into the vec4 r
From: Iago Toral Quiroga
UBO loads with constant offset use the UNIFORM_PULL_CONSTANT_LOAD
instruction, which reads 16 bytes (a vec4) of data from memory. For dvec
types this only provides components x and y. Thus, if we are reading
more than 2 components we need to issue a second load at offset+
From: Iago Toral Quiroga
---
docs/GL3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index bb2bb6e..a8219a4 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -124,7 +124,7 @@ GL 4.0, GLSL 4.00 --- all DONE: nvc0, r600, radeonsi
- Enhanced per
From: Iago Toral Quiroga
We are going to need the same logic that we use to handle ssbo loads
of doubles in other places, like shared variable loads, which also
use emit_untyped_read. Pull the logic to a separate helper function
that we can share.
---
src/mesa/drivers/dri/i965/brw_fs.h |
From: Iago Toral Quiroga
This does the inverse operation of SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA
and we will use it when we need to write 64-bit data in the layout expected
by untyped write messages.
Again, this needs to operate with WE_all set for the same reasons as the
inverse operation.
-
From: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 820d573..7ef3a7c 100644
--- a/src/mesa/drivers/dri/i965/intel_extension
From: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 87 +---
1 file changed, 80 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a23d830..5a12d63 100644
--- a/src
From: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 2c11783..fa1c30e 100644
--- a/src/mesa/drivers/dri/i965/br
From: Iago Toral Quiroga
This is pretty much the same we do with SSBOs.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 32 +++-
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_
From: Iago Toral Quiroga
There are a few places where we need to shuffle the result of a 32-bit load
into valid 64-bit data, so extract this logic into a separate helper that we
can reuse.
Also, the shuffling needs to operate with WE_all set, which we were missing
before, because we are changing
From: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 37
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index fa1c30e..9479850 100644
--- a/src
From: Iago Toral Quiroga
ARB_gpu_shader_fp64 was the only feature missing.
---
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++-
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
On 02/05/16 06:15, Jan Vesely wrote:
From: Jan Vesely
Signed-off-by: Jan Vesely
---
src/gallium/auxiliary/util/u_blitter.c| 10 +-
src/gallium/auxiliary/util/u_cpu_detect.c | 2 +-
src/gallium/auxiliary/util/u_format.c | 4 ++--
src/gallium/auxiliary/util/u_f
https://bugs.freedesktop.org/show_bug.cgi?id=93551
Vladimir Usikov changed:
What|Removed |Added
Status|RESOLVED|CLOSED
--- Comment #19 from Vladimir U
https://bugs.freedesktop.org/show_bug.cgi?id=93551
Vladimir Usikov changed:
What|Removed |Added
Resolution|FIXED |---
Status|CLOSED
Reviewed-by: Iago Toral Quiroga
On Tue, 2016-05-03 at 16:47 +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> resource just appears in GLSL 4.20 without any fanfare.
>
> Fixes GL43-CTX.CommonBugs.CommonBug_ReservedNames
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/glsl/glsl_lexer.ll
This commit broke Weston/KMS, and presumably also xf86-video-modesetting.
In order to use Y-tiled buffers, the kernel requires the tiling mode to
be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
it disallows any attempt to infer the buffer's tiling mode.
As the GBM API doe
On Mon, Feb 01, 2016 at 12:48:52PM +0900, Michel Dänzer wrote:
> On 29.01.2016 21:36, Daniel Stone wrote:
> > On 29 January 2016 at 03:44, Michel Dänzer wrote:
> >> It still sounds like significant work (particularly for somebody like me
> >> who isn't very familiar with Wayland details yet). It s
On Mon, May 02, 2016 at 06:44:34AM -0400, Rob Clark wrote:
> On Mon, May 2, 2016 at 2:15 AM, Michel Dänzer wrote:
> > On 25.04.2016 21:36, Daniel Stone wrote:
> >> On 20 April 2016 at 00:32, Rob Clark wrote:
> >>> On Tue, Apr 19, 2016 at 7:04 PM, Matt Turner wrote:
> Let's let people add th
On Tue, May 03, 2016 at 09:07:59AM +0200, Christian König wrote:
> Am 03.05.2016 um 08:39 schrieb Mathieu Malaterre:
> >AGP mode is unstable on PowerPC
>
> Your signed of by line is missing, but apart from that the patch is
> Reviewed-by: Christian König .
This should also be resubmitted to dri-d
Looks good to me,
Reviewed-by: Iago Toral Quiroga
On Tue, 2016-05-03 at 14:39 +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes two of the cases in
> GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types
>
> Signed-off-by: Dave Air
On Tue, 2016-05-03 at 14:39 +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes a crash in
> GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/glsl/ast_function.cpp | 5 -
>
Stacking frames is for driver that's capable to do dual instances
encoding. Such feature is not enabled for B frames currently.
Signed-off-by: Leo Liu
Cc: "11.1 11.2"
---
src/gallium/state_trackers/omx/vid_enc.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --
On Tue, May 3, 2016 at 9:56 AM, Daniel Vetter wrote:
> On Mon, May 02, 2016 at 06:44:34AM -0400, Rob Clark wrote:
>> On Mon, May 2, 2016 at 2:15 AM, Michel Dänzer wrote:
>> > On 25.04.2016 21:36, Daniel Stone wrote:
>> >> On 20 April 2016 at 00:32, Rob Clark wrote:
>> >>> On Tue, Apr 19, 2016 at
On Tue, May 3, 2016 at 10:52 AM, Leo Liu wrote:
> Stacking frames is for driver that's capable to do dual instances
> encoding. Such feature is not enabled for B frames currently.
>
> Signed-off-by: Leo Liu
> Cc: "11.1 11.2"
Reviewed-by: Alex Deucher
> ---
> src/gallium/state_trackers/omx/vi
On Tue, 2016-05-03 at 13:50 +0100, Jose Fonseca wrote:
> On 02/05/16 06:15, Jan Vesely wrote:
> >
> > From: Jan Vesely
> >
> > Signed-off-by: Jan Vesely
> > ---
> > src/gallium/auxiliary/util/u_blitter.c| 10 +-
> > src/gallium/auxiliary/util/u_cpu_detect.c | 2 +-
> >
Fix windows in 32-bit mode when hyperthreading is disabled on Xeons.
Some support for asymmetric processor topologies.
---
.../drivers/swr/rasterizer/core/threads.cpp| 64 --
1 file changed, 47 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/swr/raster
Smallish changes this time around, some changes that hopefully
start improving coverity's opinion of the rasterizer, and a small
performance tweak.
Tim Rowley (11):
swr: [rasterizer] Whitespace cleanup and misc changes
swr: [rasterizer core] Fix threadviz support in buckets
swr: [rasterizer
Storing color hot tile to 8bit w-major stencil format.
---
src/gallium/drivers/swr/rasterizer/memory/StoreTile.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.cpp
b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.
---
src/gallium/drivers/swr/rasterizer/common/os.h | 1 +
src/gallium/drivers/swr/rasterizer/jitter/blend_jit.h | 1 -
src/gallium/drivers/swr/rasterizer/jitter/jit_api.h | 1 -
src/gallium/drivers/swr/rasterizer/scripts/templates/knobs.template |
---
.../drivers/swr/rasterizer/common/formats.cpp | 25 --
.../drivers/swr/rasterizer/common/formats.h| 1 +
.../drivers/swr/rasterizer/core/format_traits.h| 22 +++
3 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/src/gallium/dr
Need to do lazy eval of the threadviz knob since order of globals
is undefined.
---
src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.cpp | 12
src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.h | 12 +---
src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
---
src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
index ba1096d..42b1c3e 100644
--- a/src/gallium/drivers/swr/rasterize
---
src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 5 -
src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 7 ---
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
b/src/gallium/drivers/swr/rasterizer/core/f
---
.../drivers/swr/rasterizer/common/simdintrin.h | 20 +
.../drivers/swr/rasterizer/core/backend.cpp| 26 +-
src/gallium/drivers/swr/rasterizer/core/backend.h | 7 --
3 files changed, 31 insertions(+), 22 deletions(-)
diff --git a/src/galliu
Avoid % operator, since we know that curVertex is always incrementing.
---
src/gallium/drivers/swr/rasterizer/core/pa.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h
b/src/gallium/drivers/swr/rasterizer/core/pa.h
index d3ed279
Fix static code analysis errors found by coverity on Linux
---
.../drivers/swr/rasterizer/common/swr_assert.h | 50 +++---
src/gallium/drivers/swr/rasterizer/core/arena.h| 16 +++
2 files changed, 52 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/swr/r
---
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 105 +
1 file changed, 24 insertions(+), 81 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
index 486dad8..3a304ec 100644
Hi,
On 3 May 2016 at 14:52, Daniel Vetter wrote:
> On Mon, Feb 01, 2016 at 12:48:52PM +0900, Michel Dänzer wrote:
>> As I said before, looking at intel_validate_usage, I suspect the latter.
>
> Just jumping in here, but it's correct atm. Well if we ignore a recent bug
> to enable Y-tiling where m
On 2016-05-03 05:21:49, Samuel Iglesias Gonsálvez wrote:
> Hello,
>
> This series adds the final bits to support arb_gpu_shader_fp64 in the
> i965 scalar backend for BDW+ hardware. It sits on top of the previous
> series we sent last week [0] and which is going through review at the
> moment. Spec
On 2016-05-03 05:21:50, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> This can happen if the register already has a non-zero subreg_offset
> when byte_offset() is called.
> ---
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a
On Monday, May 2, 2016 6:48:18 PM PDT Francisco Jerez wrote:
> This only works if reg.stride == 0 or 1, we need to honour the stride of
> the original register (e.g. by doing reg.stride *= stride) or you'll end
> up taking components not part of the region given as argument. It gets
> messy with A
On Tuesday, May 3, 2016 12:09:33 PM PDT Samuel Iglesias Gonsálvez wrote:
>
> On 02/05/16 23:50, Mark Janes wrote:
> > Samuel Iglesias Gonsálvez writes:
> >
> >> Hello,
> >>
> >> This patch series continues adding arb_gpu_shader_fp64 support to
> >> the Intel driver. Specifically, this targets the
On 2016-05-03 05:21:51, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> We should not offset into them based on the relative offset of
> our source and the destination of the instruction we are copy
> propagating from, so we don't turn this:
>
> mov(16) vgrf6:F, vgrf7+0.0<0>:F
>
On Monday, April 25, 2016 9:08:38 AM PDT Samuel Iglesias Gonsálvez wrote:
> From: "Juan A. Suarez Romero"
>
> When computing the offset in the uniform storage table, take into account
> the size multiplier so double precision matrices are handled correctly.
>
> Signed-off-by: Juan A. Suarez Rome
On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Connor Abbott
>
> Work based on registers read/written instead of dispatch_width, so that
> the interferences are added for 64-bit sources/destinations as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate
Other than patches 37, 56, and ones you agreed to drop, the series is:
Reviewed-by: Kenneth Graunke
I think you can go ahead and land all except those, and we can land
new solutions for those problems afterwards.
We still need to fix the horiz_offset problem, and I think Curro's
subscript() help
On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>> From: Connor Abbott
>>
>> Work based on registers read/written instead of dispatch_width, so that
>> the interferences are added for 64-bit sources/destinations as
It seems that the intention was to check both for null as they are
dereferenced immediately after.
Added in d3636da9
---
src/compiler/nir/nir_lower_var_copies.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_var_copies.c
b/src/compiler/nir/nir_lowe
Tested-by: Mark Janes
Matt Turner writes:
> Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
> Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
> implement a full work around for the restriction (dispatch_width == 16
> is an imperfect proxy).
>
> Evidentl
On Tue, May 3, 2016 at 3:13 PM, Connor Abbott wrote:
> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke wrote:
>> On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>>> From: Connor Abbott
>>>
>>> Work based on registers read/written instead of dispatch_width, so that
>>> t
On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
wrote:
> It seems that the intention was to check both for null as they are
> dereferenced immediately after.
>
> Added in d3636da9
> ---
> src/compiler/nir/nir_lower_var_copies.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
On Tuesday, May 3, 2016 3:13:26 PM PDT Connor Abbott wrote:
> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke
wrote:
> > On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
> >> From: Connor Abbott
> >>
> >> Work based on registers read/written instead of dispatch_width, so
On Fri, Apr 29, 2016 at 4:29 AM, Samuel Iglesias Gonsálvez
wrote:
> From: Connor Abbott
>
> Work based on registers read/written instead of dispatch_width, so that
> the interferences are added for 64-bit sources/destinations as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 6
On Tue, May 3, 2016 at 3:46 PM, Kenneth Graunke wrote:
> On Tuesday, May 3, 2016 3:13:26 PM PDT Connor Abbott wrote:
>> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke
> wrote:
>> > On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>> >> From: Connor Abbott
>> >>
>> >> Wo
Brian Paul writes:
> On 05/02/2016 06:15 PM, Ilia Mirkin wrote:
>> I know I've been sticking commas at the end of enums left and right
>> for the past several years, and haven't heard any complaints. The nice
>> thing about the trailing comma is that you avoid having to change
>> unrelated lines
On Tue, May 03, 2016 at 02:38:39PM +0100, Daniel Stone wrote:
> This commit broke Weston/KMS, and presumably also xf86-video-modesetting.
>
> In order to use Y-tiled buffers, the kernel requires the tiling mode to
> be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
> it disa
Jason Ekstrand writes:
> From: Connor Abbott
Reviewed-by: Eric Anholt
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On Tue, May 3, 2016 at 9:46 PM, Ilia Mirkin wrote:
> On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
> wrote:
> > It seems that the intention was to check both for null as they are
> > dereferenced immediately after.
> >
> > Added in d3636da9
> > ---
> > src/compiler/nir/nir_lowe
On Tue, May 3, 2016 at 4:38 PM, Thomas H.P. Andersen wrote:
>
>
> On Tue, May 3, 2016 at 9:46 PM, Ilia Mirkin wrote:
>>
>> On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
>> wrote:
>> > It seems that the intention was to check both for null as they are
>> > dereferenced immediatel
From: Dave Airlie
This fixes both:
GL43-CTS.khr_debug.receiveing_messages
GL43-CTS.khr_debug.groups
which reported off by ones.
Signed-off-by: Dave Airlie
---
src/mesa/main/debug_output.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/debug_output.c b/src/me
This prevents a crash when a NULL src is passed with a non-NULL length.
fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252
Signed-off-by: Mark Janes
---
src/mesa/main/objectlabel.c | 7 ---
1 file changed, 4 inser
Oops,
Reviewed-by: Dave Airlie
On 4 May 2016 at 07:01, Mark Janes wrote:
> This prevents a crash when a NULL src is passed with a non-NULL length.
>
> fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252
>
> Signed-o
If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors. Instead of asserting on
a null pointer, just no-op.
---
src/gallium/auxiliary/util/u_bitmask.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/
On 03/05/16 22:10, Brian Paul wrote:
If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors. Instead of asserting on
a null pointer, just no-op.
---
src/gallium/auxiliary/util/u_bitmask.c | 8
1 file changed, 4 inserti
This will be used so we can implement a better validateUsage, which
takes neither a screen nor a context.
Signed-off-by: Daniel Stone
Cc: Daniel Vetter
---
src/mesa/drivers/dri/i965/intel_image.h | 2 ++
src/mesa/drivers/dri/i965/intel_screen.c | 22 --
2 files changed, 18
1 - 100 of 157 matches
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