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On 02/05/16 09:13, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:20PM +0200, Samuel Iglesias Gons?lvez
> wrote:
>> From: Connor Abbott <connor.w.abb...@intel.com>
>>
>> v2 (Iago): - Squashed bits from 'support double precission
>> constant operands for the implementation of 64-bit
>> emit_load_const'. - Do not use BRW_REGISTER_TYPE_D for all 32-bit
>> registers since that breaks asserts and functionality for some
>> piglit tests. Just keep 32-bit types untouched and add 64-bit
>> support. - Use DF instead of Q for 64-bit registers. Otherwise
>> the code we generate will use Q sometimes and DF others and we
>> hit unwanted DF/Q conversions, so always use DF.
>>
>> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
>> Signed-off-by: Tapani Palli <tapani.pa...@intel.com>
>> Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
>> Signed-off-by: Iago Toral Quiroga <ito...@igalia.com> ---
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
>> ++++++++++++++++++++++++-------- 1 file changed, 25
>> insertions(+), 8 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 360e2c9..333ca2b
>> 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++
>> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -365,7 +365,9 @@
>> fs_visitor::nir_emit_impl(nir_function_impl *impl) unsigned
>> array_elems = reg->num_array_elems == 0 ? 1 :
>> reg->num_array_elems; unsigned size = array_elems *
>> reg->num_components; - nir_locals[reg->index] =
>> bld.vgrf(BRW_REGISTER_TYPE_F, size); + brw_reg_type reg_type
>> =
>
> Could be 'const', and the same for the three similar occurrences
> further down.
>
OK, thanks. I will change them to be 'const'.
Sam
>> + reg->bit_size == 32 ? BRW_REGISTER_TYPE_F :
>> BRW_REGISTER_TYPE_DF; + nir_locals[reg->index] =
>> bld.vgrf(reg_type, size); }
>>
>> nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg, @@
>> -1201,10 +1203,21 @@ void fs_visitor::nir_emit_load_const(const
>> fs_builder &bld, nir_load_const_instr *instr) { - fs_reg reg =
>> bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components); +
>> brw_reg_type reg_type = + instr->def.bit_size == 32 ?
>> BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_DF; + fs_reg reg =
>> bld.vgrf(reg_type, instr->def.num_components);
>>
>> - for (unsigned i = 0; i < instr->def.num_components; i++) -
>> bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); +
>> switch (instr->def.bit_size) { + case 32: + for (unsigned
>> i = 0; i < instr->def.num_components; i++) +
>> bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i])); +
>> break; + + case 64: + for (unsigned i = 0; i <
>> instr->def.num_components; i++) + bld.MOV(offset(reg,
>> bld, i), brw_imm_df(instr->value.f64[i])); + break; + }
>>
>> nir_ssa_values[instr->def.index] = reg; } @@ -1212,8 +1225,10 @@
>> fs_visitor::nir_emit_load_const(const fs_builder &bld, void
>> fs_visitor::nir_emit_undef(const fs_builder &bld,
>> nir_ssa_undef_instr *instr) { -
>> nir_ssa_values[instr->def.index] = bld.vgrf(BRW_REGISTER_TYPE_D,
>> -
>> instr->def.num_components); + brw_reg_type reg_type = +
>> instr->def.bit_size == 32 ? BRW_REGISTER_TYPE_D :
>> BRW_REGISTER_TYPE_DF; + nir_ssa_values[instr->def.index] = +
>> bld.vgrf(reg_type, instr->def.num_components); }
>>
>> fs_reg @@ -1240,8 +1255,10 @@ fs_reg
>> fs_visitor::get_nir_dest(nir_dest dest) { if (dest.is_ssa) { -
>> nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F, -
>> dest.ssa.num_components); + brw_reg_type reg_type = +
>> dest.ssa.bit_size == 32 ? BRW_REGISTER_TYPE_F :
>> BRW_REGISTER_TYPE_DF; + nir_ssa_values[dest.ssa.index] = +
>> bld.vgrf(reg_type, dest.ssa.num_components); return
>> nir_ssa_values[dest.ssa.index]; } else { /* We don't handle
>> indirects on locals */ -- 2.5.0
>>
>> _______________________________________________ mesa-dev mailing
>> list mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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