On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote:
> On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote:
> > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote:
> >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> > Hi ilia,
> >> >
> >> > On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin
On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote:
> Ilia Mirkin writes:
>
> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> Hi ilia,
> >>
> >> On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote:
> >>> Hi Samuel, and any other onlookers,
> >>>
> >>> I was wondering why the dec
The initial glGetUniformdv support didn't cover all the
casting cases that are apparantly legal, and cts seems to
test for them.
I've updated the piglit test to cover these cases now.
cc: "11.0"
Signed-off-by: Dave Airlie
---
src/mesa/main/uniform_query.cpp | 39 +--
On 30/09/15 00:26, Chad Versace wrote:
On Mon 28 Sep 2015, Martin Peres wrote:
On 28/09/15 17:27, Emil Velikov wrote:
Hi all,
On 17 August 2015 at 19:06, Chad Versace wrote:
On Fri 14 Aug 2015, Chris Wilson wrote:
On Thu, Aug 13, 2015 at 09:58:52PM -0700, Kenneth Graunke wrote:
On Thursday
Both the vec4 and scalar VS backends had virtually identical URB entry
size and read length calculations. We can move those up a level to
backend-agnostic code and reuse it for both.
Unfortunately, the backends need to know nr_attributes to compute
first_non_payload_grf, so I had to store that in
Unlike the vs/wm structs, brw_gs_compile is actually useful: it contains
the input VUE map and information about the control data headers.
Passing this in allows us to share that code in brw_gs.c, and calculate
them before deciding on vec4 vs. scalar mode, as it's independent of
that choice.
Signe
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 2997e51..774ce86 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
The next commit will introduce a new intrinsic for shaders which process
multiple vertices (i.e. geometry, tessellation). This plumbing allows
us to generate different intrinsics based on the shader stage.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_io.c | 18 ++
1
Reading this output was really confusing. reg represents attribute
slots; reg_offset is the x/y/z/w component (0..3) within a vec4 slot.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/d
Previously, we used nir_lower_io with the scalar type_size function,
which mapped VERT_ATTRIB_* locations to...some numbers. Then, in
fs_visitor::nir_setup_inputs(), we created temporaries indexed by
those numbers, and emitted MOVs from the actual ATTR registers to
those temporaries.
This patch r
Geometry and tessellation shaders process multiple vertices; their
inputs are arrays indexed by the vertex number. While GLSL makes
this look like a normal array, it can be very different behind the
scenes.
On Intel hardware, all inputs for a particular vertex are stored
together - as if they wer
The GS will emit a bunch of vertices, and we don't want to do an EOT
prematurely. We'll emit GS_OPCODE_THREAD_END when we want to terminate
the thread.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
In scalar mode, geometry shader inputs can easily take up hundreds of
registers. This makes pushing VUE entries impractical; we'll need to
resort to the pull model in some cases.
To support this, we introduce a new opcode corresponding to the "URB
Read SIMD8" message.
Signed-off-by: Kenneth Grau
We have a nir_deref_var, but it doesn't actually need that. Upcoming
patches will make us call get_io_offset further down the dereference
chain, so handling an arbitrary dereference will be nice.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_io.c | 8
1 file changed, 4 inse
We may want to use different type_size functions for (e.g.) inputs
vs. uniforms. Passing in -1 for mode ignores this, handling all
modes as before.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir.h | 1 +
src/glsl/nir/nir_lower_io.c | 21 +
src/
Hello,
Here's a respin of my SIMD8 VS input refactors, new GS input refactors,
and finally the long-awaited SIMD8 GS support.
Patches 1-10 are input refactoring. Patches 11-23 are SIMD8 GS support.
To try out SIMD8 GS, set the INTEL_SCALAR_GS=1 environment variable.
Note that the feature requir
We really ought to compute the VUE map at link time and stash it, rather
than recomputing it here, but with the mess of program structures I
wasn't sure where to put it. We can improve that later.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_nir.c | 44 ++
In the vec4 backend, we have a vec4_instruction::urb_write_flags field.
There are many kinds of flags for SIMD4x2 messages.
However, there are really only two (per-slot offset, use channel masks)
for SIMD8 messages. Rather than adding a boolean flag for per-slot
offsets (polluting all instruction
Tessellation shaders and SIMD8 geometry shaders may need to resort to
the pull model for inputs at times. When set, the state upload code
will tell the hardware to provide URB handles for input data.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
src/mesa/
Geometry shaders have additional header data at the beginning of their
output URB entries. Shaders that use EndPrimitive() or multiple streams
have a control data header; shaders with a dynamic vertex count have an
additional vec4 slot to hold the 32-bit vertex count (and 96 bits of
padding).
Sig
It's stored in bits 31:27 of g1 (along with the URB handles).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index
This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs,
which controls whether or not to use SIMD8 geometry shaders.
For now, we control it via a new environment variable, INTEL_SCALAR_GS.
This provides a convenient way to try it out.
Signed-off-by: Kenneth Graunke
---
src/mesa/
GS doesn't have ClampVertexColor, and we don't want to go through VS
structures.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/
nr_attributes is used to compute first_non_payload_grf, which is the
first register we're allowed to use for ordinary register allocation.
The hardware requires us to read at least one pair of values, but we're
completely free to overwrite that garbage register with whatever we like.
Instead of a
Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of
compilation, assign_vs_urb_setup() translated those into GRF units,
and converted ATTR to HW_REGs.
This patch moves the transslation earlier, making ATTR work in terms of
GRF units from the beginning. assign_vs_urb_setup() simply
The code for input lowering is going to get significantly more
complicated shortly, so I wanted to pull it out. Vertex shader inputs
are handled nearly identically regardless of vec4/scalar mode, so I
opted to not split that.
I thought about having each function actually do the lowering, but one
For scalar VS, I'll need this in brw_fs.cpp as well. It seems silly to
redeclare it in three places.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 2 --
src/mesa/drivers/dri/i965/gen6_gs_visitor.c
Reviewed-by: Samuel Iglesias Gonsálvez
On 30/09/15 02:12, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 2 +-
> src/mesa/drivers/dri/i965/brw_state.h| 1 +
> src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
>
Iago Toral writes:
> On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote:
>> Ilia Mirkin writes:
>>
>> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
>> >> Hi ilia,
>> >>
>> >> On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote:
>> >>> Hi Samuel, and any other onlookers,
>> >>>
>>
On Mon, Sep 28, 2015 at 4:39 PM, Roland Scheidegger wrote:
>
> In short, for simplicity, only things were sharable which were really
> required to be shared (pretty much just actual resources - and yes that
> doesn't work too well for GL neither as you can't share sampler/rt
> views, let's face it
On Wed, 2015-09-30 at 11:54 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote:
> >> Ilia Mirkin writes:
> >>
> >> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> >> Hi ilia,
> >> >>
> >> >> On Tue, 2015-09-29 at 03:53 -0
This fixes a bug that Curro pointed out: we only allocate entries for
UBOs at the moment. This a problem when a shader defines more
than 12 combined UBO and SSBO surfaces. This is done with patch 3.
patch 4 simply adds an assertion to make sure that we never try to exceed
that limit for some reaso
These share the space with UBO surfaces but we need to make sure we
allocate enough space for both sets (12 of each)
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
in
Instead of using hard-coded values.
---
src/mesa/drivers/dri/i965/brw_context.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 5 -
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 4d499
In theory we can't break this assertion since the compiler frontend checks
that we don't exceed any of the individual limits, but it does not hurt to
be extra safe.
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
2 files changed, 4 insertions(+
Instead of using hard-coded values.
---
src/mesa/drivers/dri/i965/brw_context.c | 14 +++---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
On 29 September 2015 at 23:53, Dave Airlie wrote:
> On 30 September 2015 at 01:34, Laurent Carlier wrote:
>> llvm can be built with cmake in a libray with the name libLLVM.so.$version
>> Tested with both llvm-3.7.0 and llvm-3.8.0svn
>>
>> v2: check and use llvm build-system feature, update commen
Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
format specifier that operates on GLintptr indirect within the function
_mesa_DispatchComputeIndirect().
This patch mitigates the introduced GCC warning:
src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':
s
Chris Wilson writes:
> Only walk through the set of enabled TextureUnits looking for a texture
> that needs to be resolved if the context state flags a new texture.
>
> Note that this will miss if the client is rendering into a texture that
> it is reading from, though that needs explicit barrier
Ian Romanick writes:
> On 09/09/2015 06:39 AM, Chris Wilson wrote:
>> Having checked whether the base class (gl_texture_object) is NULL, we
>> know that intel_texture_object itself cannot be NULL.
>>
>> Signed-off-by: Chris Wilson
>> Cc: Jordan Justen
>> Cc: Jason Ekstrand
>> Cc: Kenneth Grau
2015-09-30 19:15 GMT+08:00 Rhys Kidd :
> Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
> format specifier that operates on GLintptr indirect within the function
> _mesa_DispatchComputeIndirect().
>
> This patch mitigates the introduced GCC warning:
>
> src/mesa/main/comput
On Wed, Sep 30, 2015 at 5:51 AM, Michel Dänzer wrote:
> On 29.09.2015 23:54, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> This can cause incorrect address calculations and hangs.
>>
>> Cc: mesa-sta...@lists.freedesktop.org
>
> IIRC without "10.6 11.0" this only makes it a candidate for the 11.0
On 09/30/2015 12:19 AM, Tapani Pälli wrote:
https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx
Signed-off-by: Tapani Pälli
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
---
src/mesa/main/imports.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/main/imports
Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
format specifier that operates on GLintptr indirect within the function
_mesa_DispatchComputeIndirect().
This patch mitigates the introduced GCC warning:
src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':
s
On 09/27/2015 04:20 PM, Marek Olšák wrote:
From: Marek Olšák
Nothing overrides it.
---
src/mesa/drivers/common/driverfuncs.c | 1 -
src/mesa/drivers/dri/common/dri_util.c | 3 ++-
src/mesa/main/dd.h | 7 ---
3 files changed, 2 insertions(+), 9 deletions(-)
diff --
Am 30.09.2015 um 11:41 schrieb Erik Faye-Lund:
> On Mon, Sep 28, 2015 at 4:39 PM, Roland Scheidegger
> wrote:
>>
>> In short, for simplicity, only things were sharable which were really
>> required to be shared (pretty much just actual resources - and yes that
>> doesn't work too well for GL neit
Right now nir_instrs_equal() is tied pretty tightly to CSE, but we're
going to introduce the idea of an instruction set and tie it to that
instead. In anticipation of that, move this into its own file where
we'll add the rest of the instruction set implementation later.
v2: Rebase on texture supp
This replaces an O(n^2) algorithm with an O(n) one, while allowing us to
import most of the infrastructure required for GVN. The idea is to walk
the dominance tree depth-first, similar when converting to SSA, and
remove the instructions from the set when we're done visiting the
sub-tree of the domi
v2: rebase, don't constify nir_srcs_equal() as it's pass-by-value
anyways
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir_instr_set.c | 6 +++---
src/glsl/nir/nir_instr_set.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/glsl/nir/nir_instr_set.c b/src/glsl/nir/nir_
This was previously tied to CSE, since it would only work for
instructions where nir_can_cse() (now instr_can_rewrite()) returned
true. Now that CSE uses the instruction set abstraction which only uses
this internally, we can make it local to nir_instr_set.c.
Signed-off-by: Connor Abbott
---
src
This is a v2 of my series to make the NIR CSE pass use a hash table
internally. The big difference from the last revision is that the
entire implementation is in one file, nir_instr_set.c, with one public
API (nir_instrs_equal() isn't publically exposed anymore), rather than
being split across two
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 4f45770..58a86f7 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -722,7 +722,7 @@ nir_alu_instr_channel_used(nir_alu_in
This will replace direct usage of nir_instrs_equal() in the CSE pass,
which reduces an O(n^2) algorithm with an effectively O(n) one. It'll
also be useful for implementing GVN on top of GCM.
v2:
- Add texture support.
- Add more comments.
- Rename instr_can_hash() to instr_can_rewrite() since it's
This was originally added to nir_instrs_equal() instead of
nir_instr_can_cse() incorrectly, but this was fixed when moving to the
instruction set API (as it had to be, otherwise hashing wouldn't work).
Now, this is dead code since instr_can_rewrite() will only return true
for texture instructions t
On Wed, Sep 30, 2015 at 3:18 AM, Iago Toral wrote:
> On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote:
>> On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote:
>> > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote:
>> >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
>> >> > Hi ilia,
>>
On Wed, Sep 30, 2015 at 3:53 PM, Roland Scheidegger wrote:
> Am 30.09.2015 um 11:41 schrieb Erik Faye-Lund:
>> On Mon, Sep 28, 2015 at 4:39 PM, Roland Scheidegger
>> wrote:
>>>
>>> In short, for simplicity, only things were sharable which were really
>>> required to be shared (pretty much just a
On Wed, Sep 30, 2015 at 8:11 AM, Connor Abbott wrote:
> This will replace direct usage of nir_instrs_equal() in the CSE pass,
> which reduces an O(n^2) algorithm with an effectively O(n) one. It'll
> also be useful for implementing GVN on top of GCM.
>
> v2:
> - Add texture support.
> - Add more c
On Wed, Sep 30, 2015 at 8:11 AM, Connor Abbott wrote:
> This is a v2 of my series to make the NIR CSE pass use a hash table
> internally. The big difference from the last revision is that the
> entire implementation is in one file, nir_instr_set.c, with one public
> API (nir_instrs_equal() isn't p
On Sat 12 Sep 2015, Chris Wilson wrote:
> On Thu, Sep 10, 2015 at 08:41:37AM +0100, Chris Wilson wrote:
> > http://people.freedesktop.org/~ickle/vbo/
> >
> > ministat 63c4b7e_bench_synmark:OglBatch7 2fbce8b_bench_synmark:OglBatch7
> > x 63c4b7e_bench_synmark:OglBatch7
> > + 2fbce8b_bench_synmark:O
GLSL IR vs. NIR shader-db results for vec4 programs on i965:
total instructions in shared programs: 1499328 -> 1388354 (-7.40%)
instructions in affected programs: 1245199 -> 1134225 (-8.91%)
helped:7469
HURT: 2440
GL
Jason open coded this in 60befc63 when cleaning up some ugly code;
using our existing helper tidies it up a bit more.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 51 +---
1 file changed, 20 insertions(+), 31 deletions(-)
diff --git a
On Wed, Sep 30, 2015 at 9:59 AM, Kenneth Graunke wrote:
> Jason open coded this in 60befc63 when cleaning up some ugly code;
> using our existing helper tidies it up a bit more.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 51
> +-
On Wed, Sep 30, 2015 at 10:08 AM, Matt Turner wrote:
> On Wed, Sep 30, 2015 at 9:59 AM, Kenneth Graunke
> wrote:
>> Jason open coded this in 60befc63 when cleaning up some ugly code;
>> using our existing helper tidies it up a bit more.
Sorry about that.
Reviewed-by: Jason Ekstrand
>> Signed
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> We may want to use different type_size functions for (e.g.) inputs
> vs. uniforms. Passing in -1 for mode ignores this, handling all
> modes as before.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/nir/nir.h | 1
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> The next commit will introduce a new intrinsic for shaders which process
> multiple vertices (i.e. geometry, tessellation). This plumbing allows
> us to generate different intrinsics based on the shader stage.
It's actually two patches l
Reviewed-by: Jordan Justen
and committed.
On 2015-09-30 06:18:52, Rhys Kidd wrote:
> Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
> format specifier that operates on GLintptr indirect within the function
> _mesa_DispatchComputeIndirect().
>
> This patch mitigates the i
https://bugs.freedesktop.org/show_bug.cgi?id=92173
Tapani Pälli changed:
What|Removed |Added
Component|Drivers/Gallium/r600|Mesa core
Assignee|dri-devel@li
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c61b385..121e698 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cp
On 09/30/2015 04:06 PM, Brian Paul wrote:
On 09/30/2015 12:19 AM, Tapani Pälli wrote:
https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx
Signed-off-by: Tapani Pälli
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
---
src/mesa/main/imports.h | 3 +++
1 file changed, 3 insert
https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx
v2: use _WIN32 instead of _MSC_VER (Brian Paul)
Signed-off-by: Tapani Pälli
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
---
src/mesa/main/imports.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/main/import
I'm not sure if this makes sense. I can see how it would be useful
(less information lost when going src_reg -> dst_reg -> src_reg).
However, it seems wrong to me to assume that dst_reg.abs or
dst_reg.negate means anything useful. Matt?
--Jason
On Wed, Sep 30, 2015 at 10:32 AM, Alejandro Piñeiro
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> Previously, we used nir_lower_io with the scalar type_size function,
> which mapped VERT_ATTRIB_* locations to...some numbers. Then, in
> fs_visitor::nir_setup_inputs(), we created temporaries indexed by
> those numbers, and emitted MOVs
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of
> compilation, assign_vs_urb_setup() translated those into GRF units,
> and converted ATTR to HW_REGs.
>
> This patch moves the transslation earlier, making ATTR work in te
https://bugs.freedesktop.org/show_bug.cgi?id=92173
--- Comment #2 from Tapani Pälli ---
(In reply to Tapani Pälli from comment #1)
> this bug is likely a duplicate for #92122
having said that it seems unlikely that the bug would cause gpu hangs or slow
downs but likely just wrong rendering, ther
On Wed, Sep 30, 2015 at 10:38 AM, Jason Ekstrand wrote:
> I'm not sure if this makes sense. I can see how it would be useful
> (less information lost when going src_reg -> dst_reg -> src_reg).
> However, it seems wrong to me to assume that dst_reg.abs or
> dst_reg.negate means anything useful. M
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> Hello,
>
> Here's a respin of my SIMD8 VS input refactors, new GS input refactors,
> and finally the long-awaited SIMD8 GS support.
>
> Patches 1-10 are input refactoring. Patches 11-23 are SIMD8 GS support.
1-4 and 6-11 are
Reviewed-by
On 30/09/15 19:38, Jason Ekstrand wrote:
> I'm not sure if this makes sense. I can see how it would be useful
> (less information lost when going src_reg -> dst_reg -> src_reg).
> However, it seems wrong to me to assume that dst_reg.abs or
> dst_reg.negate means anything useful.
Hmm, true. FWI
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> Geometry and tessellation shaders process multiple vertices; their
> inputs are arrays indexed by the vertex number. While GLSL makes
> this look like a normal array, it can be very different behind the
> scenes.
>
> On Intel hardware, al
On Wed, Sep 30, 2015 at 11:03 AM, Alejandro Piñeiro
wrote:
>
>
> On 30/09/15 19:38, Jason Ekstrand wrote:
>> I'm not sure if this makes sense. I can see how it would be useful
>> (less information lost when going src_reg -> dst_reg -> src_reg).
>> However, it seems wrong to me to assume that dst_
On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote:
> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
> b/src/mesa/drivers/dri/i965/brw_inst.h
> index c5132ba..b551334 100644
> --- a/src/mesa/drivers/dri/i965/brw_inst.h
> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
> @@ -386,6 +386,7 @@ FF(
On Wednesday, September 30, 2015 11:23:48 AM Matt Turner wrote:
> On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke
> wrote:
> > diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
> > b/src/mesa/drivers/dri/i965/brw_inst.h
> > index c5132ba..b551334 100644
> > --- a/src/mesa/drivers/dri/i965/brw_
From: Marek Olšák
This can cause incorrect address calculations and hangs.
v2: do it properly
Cc: mesa-sta...@lists.freedesktop.org
Tested-and-Reviewed-by: Christian König
---
src/gallium/drivers/radeonsi/si_descriptors.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --g
On Fri, 25 Sep 2015 16:40:31 -0700
Ian Romanick wrote:
> On 09/20/2015 01:15 PM, Gregory Hainaut wrote:
> > Current GLSL badly optimizes the code making it incompatible with the
> > GL_ARB_separate_shader_objects extension.
> >
> > Typical example of the current behavior:
> >
> > VS:
> > out SH
On Sun, Sep 27, 2015 at 8:02 AM, Albert Freeman
wrote:
> On 25 September 2015 at 23:49, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> Not needed and it can be NULL.
>>
>> Cc: 10.6 11.0
>> ---
>> src/gallium/state_trackers/dri/dri2.c | 6 --
>> 1 file changed, 4 insertions(+), 2 deletions(-
On Mon, Sep 28, 2015 at 5:56 AM, Michel Dänzer wrote:
> On 03.09.2015 07:26, Marek Olšák wrote:
>> On Wed, Sep 2, 2015 at 10:56 PM, Kenneth Graunke
>> wrote:
>>> On Wednesday, September 02, 2015 02:26:56 AM Marek Olšák wrote:
From: Marek Olšák
A user can be using Mesa 11.0, but /
I'm working on libglvnd, a vendor-neutral dispatch library for OpenGL,
and I wanted to see if anyone had any comments or suggestions about it.
Right now, I'm trying to get the GLX interface wrapped up, but I'd like
to get some feedback from the Mesa community before I'd be confidant in
calling
This fixes a race condition in the glx-multithreaded-shader-compile
test.
v2:
- Replace gallivm_init_llvm_{begin,end}() with gallivm_init_llvm_targets().
CC: "10.6 11.0"
---
src/gallium/drivers/radeon/radeon_llvm_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers
CC: "10.6 11.0"
---
src/gallium/drivers/radeon/radeon_llvm_emit.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index 0002559..5d93a4d 100644
--- a/src/
Drivers and state trackers that use LLVM for generating code, must
register the targets they use with LLVM's global TargetRegistry.
The TargetRegistry is not thread-safe, so all targets must be added
to the registry before it can be queried for target information.
When drivers and state trackers i
On 09/30/2015 11:38 AM, Tapani Pälli wrote:
https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx
v2: use _WIN32 instead of _MSC_VER (Brian Paul)
Signed-off-by: Tapani Pälli
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
---
src/mesa/main/imports.h | 3 +++
1 file changed, 3
From: Rob Clark
Not actually working yet, ie. doesn't even compile yet, but an idea.
Initial motivation was for drm_gralloc/pipe, which is essentially a sort
of mini state-tracker, that needs to be able to share pipe_screen with
libGL linked into the same process (to ensure we didn't end up with
This is the last of the t_dd_dmatmp janitor work that I plan to do.
The first patch is a change suggested by Ville while I was reviewing
some of his patches to t_dd_dmatmp earlier this year. I re-found
Ville's patches while I was searching my inbox for reviews to my
previous t_dd_dmatmp series.
From: Ville Syrjälä
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so we can just as well use COPY_DWORDS().
Signed-off-by:
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/radeon/radeon_common.c | 21 -
src/mesa/drivers/dri/radeon/radeon_common.h | 1 -
src/mesa/drivers/dri/radeon/radeon_screen.h | 1 -
src/mesa/drivers/dri/radeon/radeon_span.c | 7 +--
4 files ch
From: Ville Syrjälä
When rendering quad strips via tri strips we can't get the provoking
vertex right, so disallow flat shading.
v2: Major rebase on top of Ian's other t_dd_dmatmp.h work.
Signed-off-by: Ville Syrjälä
Signed-off-by: Ian Romanick
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 7 ++-
From: Ville Syrjälä
When drawing quads using triangles we need to be careful to make
the provoking vertices match when flat shading.
v2: Major rebase on top of Ian other t_dd_dmatmp.h work.
Signed-off-by: Ville Syrjälä
Signed-off-by: Ian Romanick
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 46 ++
From: Ian Romanick
While this file lives in src/mesa/tnl_dd, it is built only in drivers
that live in src/mesa/drivers/dri. We don't generally allow C99-isms in
common code, but we have allowed C99-isms in src/mesa/drivers/dri for
quite some time.
Signed-off-by: Ian Romanick
---
src/mesa/tnl_
From: Ville Syrjälä
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so if we don't need it in intel_tris.c we don't need it in
From: Ville Syrjälä
Flip the cull bits when rendering to a user fbo on gen2. This
was already done on gen3 (since before git history starts)
but was missing from the gen2 code.
Fixes rendering of the driver+kart model in supertuxkart kart
selection screen.
Signed-off-by: Ville Syrjälä
Reviewed
From: Ville Syrjälä
We can allow rendering flat shaded polygons using tri fans if we check
the provoking vertex convention.
v2 (idr): Remove _EXT suffixes from GL_FIRST_VERTEX_CONVENTION.
Signed-off-by: Ville Syrjälä
Reviewed-by: Ian Romanick
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 6 --
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